CN106772269A - A kind of equivalent sampling circuit of application ground penetrating radar echo signals collection - Google Patents

A kind of equivalent sampling circuit of application ground penetrating radar echo signals collection Download PDF

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CN106772269A
CN106772269A CN201710122963.2A CN201710122963A CN106772269A CN 106772269 A CN106772269 A CN 106772269A CN 201710122963 A CN201710122963 A CN 201710122963A CN 106772269 A CN106772269 A CN 106772269A
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triode
signal
circuit
sampling
pulse
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CN106772269B (en
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蔡志匡
石国伟
王吉
程景清
肖建
郭宇锋
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Nanjing Post and Telecommunication University
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28Details of pulse systems
    • G01S7/285Receivers
    • G01S7/292Extracting wanted echo-signals
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01VGEOPHYSICS; GRAVITATIONAL MEASUREMENTS; DETECTING MASSES OR OBJECTS; TAGS
    • G01V3/00Electric or magnetic prospecting or detecting; Measuring magnetic field characteristics of the earth, e.g. declination, deviation
    • G01V3/12Electric or magnetic prospecting or detecting; Measuring magnetic field characteristics of the earth, e.g. declination, deviation operating with electromagnetic waves

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Remote Sensing (AREA)
  • General Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Geology (AREA)
  • Environmental & Geological Engineering (AREA)
  • General Life Sciences & Earth Sciences (AREA)
  • Electromagnetism (AREA)
  • Geophysics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The invention discloses a kind of new sequential equivalent circuit for processing radar echo signal, whole sample circuit includes Digital Signals circuit, ps grades of pulse-generating circuit, sampling hold circuit, ADC change-over circuits;Described digital controlled signal is to produce an adjustable square-wave signal of time delay using programmable gate array combination external crystal-controlled oscillation;Described ps pulse-generating circuits are will to be converted into a pulse signal for carry time delay ps grades by the square-wave signal of time delay;Sampling hold circuit is connected with ps pulses, using ps pulses as sampling and holding signal;The pulse signal of high frequency is elongated and is connected with ADC by sampling hold circuit, is ultimately delivered to modulus conversion chip.This sequential sampling circuit is well suited for carrying out A/D conversions to high-frequency signal using low speed ADC, advantageously reduces the cost of whole sample circuit design.

Description

A kind of equivalent sampling circuit of application ground penetrating radar echo signals collection
Technical field
The present invention relates to electronic applications, more particularly to high-frequency signal collection is adopted with the application ground penetrating radar echo signals for the treatment of The equivalent sampling circuit of collection.
Background technology:
In recent years, ultra-wideband ground-penetrating radar (uw-gpr) is applied to the structure detection of means of transportation as a kind of Dynamic Non-Destruction Measurement, It is ultra wide band due to receiving signal, its pulse is extremely narrow, and frequency is extremely broad.If the reality used using traditional ground penetrating radar system When the mode sampled gather the signal frequency that Gpr Signal, i.e. sample frequency are at least greater than 2 times.Should for ultra wide band With the band of such as signal is wider than 1GHz, due to being limited by sampling thheorem, generally requires high speed of the sample rate more than 2GHz Integrated A/D chips or high-speed sampling equipment.And the integrated A/D chip costs of 2GHz sample rates are very high at present, general hundreds of dollars. The shortcomings of high-speed sampling equipment there is also high cost, volume is larger.What A/D was changed in addition refers mainly to indicate sampling rate and adopts Sample precision, and the two indexs are the developing conflicts of A/D, so A/D chips are often sampling rate high, precision It is low, or sampling precision is high but sampling rate is relatively low, or compromise considers.
From present technology and product, low speed, low resolution data acquisition technology it is quite ripe, realize To be easier, monolithic ADC can meet requirement, and the stability and reliability of product are unquestionable.And the data of high speed are adopted Collection technology is the forward position of Information base.Current China High speed data acquisition relatively falls behind, and is China's information technology Bottleneck, this of research and development technology has the good wide prospect of important value for the dual-use field of China.Mesh Preceding most popular high speed output technology has many AD parallel samplings technologies and random sampling technique.But both technologies Sampling techniques data dependence all is accurately controlled circuit and signal restructuring circuit, therefore in terms of control and signal transacting Method comparison is complicated.
External existing data acquisition is expensive, volume is larger, complex operation, sample frequency and two kinds of sampling precision not Can unify well.Therefore, although external relatively early using technology development, a kind of relatively inexpensive, behaviour does simple Sample circuit still requires study.
In sum, substantial amounts of work has been done by domestic and international researcher, company in terms of the research of high-speed data acquistion system Make, but it is domestic also very big with external difference tool in terms of High speed data acquisition.Domestic high-speed sampling technology is immature And the feasibility of acquisition system is not high.But it is and the High speed data acquisition feasibility complex operation high of foreign countries, expensive. So, design the specific larger meaning of a simple high speed output system.
The content of the invention
It is an object of the present invention to provide it is a kind of can simple efficient sampling ground penetrating radar echo signals equivalent sampling circuit.
To achieve these goals, the present invention uses following technical scheme:One kind application ground penetrating radar echo signals collection Equivalent sampling circuit, including:Two-stage low-noise amplifier, high-speed sampling gate circuit, ADC change-over circuits, Digital Signals Circuit and ps pulse-generating circuits;
The two-stage low-noise amplifier, high-speed sampling gate circuit, ADC change-over circuits are sequentially connected, and the ps pulses are produced Raw circuit is connected with Digital Signals circuit, high-speed sampling gate circuit respectively;
Wherein two-stage low-noise amplifier connection receives the antenna of radar echo signal, for by the signal on antenna It is amplified, the signal of amplification is sampled by the input that coupled capacitor is sent to high-speed sampling gate circuit;
The Digital Signals circuit is can using one time delay of generation of programmable gate array combination external crystal-controlled oscillation The square-wave signal of tune;
The ps pulse-generating circuits are used to be converted into by the square-wave signal of time delay ps grades with time delay of pulse Signal;
The high-speed sampling gate circuit is used to for time delay ps grades of pulse signal to form the sampling of opposite in phase and keeps signal, ADC change-over circuits are sent into the radar signal collection high-frequency signal part for amplifying and after elongating.
Further, Digital Signals circuit controls the D0- of MC100E195B chips using programmable gate array D9 controls the time delay of square-wave signal.
Further, time delay is 10ps stepping time delays.
Further, ps pulse-generating circuits include snowslide circuit, and snowslide circuit includes avalanche transistor, direct current biasing electricity Road and differential shaping network, stepping time delay square-wave signal extract the edge of pulse by differential shaping network, reduce square-wave signal Dutycycle, the square-wave signal of time delay as avalanche transistor input signal using avalanche transistor avalanche multiplication effect knot Ps grades of pulse signal of time delay is formed after closing shaping network shaping.
Further, width of the derivative constant τ of differential shaping network less than positive pulse edge.
Further, high-speed sampling gate circuit includes triode Q2 and sampling door circuit, the ground level connection ps of triode Q2 Pulse-generating circuit, colelctor electrode connection sampling door circuit, grounded emitter.
Further, sampling door circuit includes triode Q3, triode Q4, triode Q5 and holding capacitor, triode The ground level of the colelctor electrode connecting triode Q4 of Q2, the emitter stage of the emitter stage connecting triode Q3 of triode Q4, triode Q4's The emitter stage of colelctor electrode connecting triode Q5, the colelctor electrode of triode Q3 and the ground level connection two-stage low noise of triode Q5 are put Big device, the emitter stage of triode Q5 is connected with holding capacitor.
Further, when time delay ps grades of pulse signal is high, triode Q2 conductings, now triode Q3 conductings, triode Q4 ends, and the radar signal being exaggerated when triode Q3 is turned on is protected by triode Q3 to ground, the now voltage in holding capacitor Hold constant, now whole circuit is in hold mode;When time delay ps grades of pulse signal is 0, triode Q2 cut-offs, triode Q3 Cut-off, triode Q5 conductings, the radar signal being now exaggerated are sampled electricity by triode Q5 to output end, i.e. radar signal Sampling is gone on road.
Further, insulating gate type field effect tube Q6 is connected after holding capacitor, triode Q6 connection differential amplifiers amplify The output end of signal is connected with ADC change-over circuits.
Further, the f of triode Q2 to Q6tMore than 10Ghz.
Ground penetrating radar echo signals by antenna reception after, by several millivolts that dual-stage amplifier receives antenna of echo Signal is amplified to hundreds of millivolts, transfers to sampling door circuit to process.
The whole main FPGA controls stepping delay chip of numerical portion, it can be seen from MC100E195B chip handbooks, can be with The time delay of square wave is adjusted by the control disciplined chip D9-D0, by square-wave signal and the ps pulse-generating circuits of time delay It is connected, now forms ps grades of pulse signal of 10ps stepping time delays.Ps pulse-generating circuits are connected with high-speed sampling gate circuit Connect;Pulse signal by Q2 formed a pair of samplings of opposite in phase with keep signal, sampling door circuit be made up of triode Q3, Q4, Q5 and holding capacitor are constituted;The Q3 conductings Q4 cut-offs when ps pulses are exported, Q5 is in cut-off state, is now in keeping State, the now Q3 cut-offs when ps is 0, Q4 conductings, Q5 is in the conduction state, and collection follower is penetrated in formation, and emitter follower is by two The sample of signal that level amplifying circuit amplifies out is charged to holding capacitor C20, and now circuit is in sampling state;Sampling and holding Circuit interacts, by the letter in reply waveform stretch of radar signal.Sample-and-hold circuit as described above is connected with ADC, so We provide for a relatively low signal of frequency and are gathered to ADC, final the data signal for gathering is processed using FPGA, The final upper waveform for recovering radar signal.
The collection effectively realized using simple circuit to high-speed data of the invention, the low cost of whole sampling system, Feasibility is high, is advantageous to collection and treatment to radar signal.
Brief description of the drawings
Fig. 1 is the structured flowchart of equivalent sampling circuit.
Fig. 2 is two-stage amplifier circuit in low noise figure.
Fig. 3 is delay chip catenation principle figure.
Fig. 4 is differential amplifier schematic diagram.
Fig. 5 is sampling system schematic diagram.
Fig. 6 is the final simulation result figure of whole equivalent sampling circuit.
Fig. 7 is sampling pulse amplitude and width.
Specific embodiment:
In order to further illustrate the effect of the technological means taken of the present invention and acquirement, below in conjunction with the accompanying drawings with specifically Embodiment, to technical scheme, carries out clear and complete description.
As the whole sampling systems of Fig. 1 are divided into:Two-stage low-noise amplifier, high-speed sampling gate circuit, Digital Signals electricity The parts such as road, ps pulse-generating circuits, ADC change-over circuits.
Two-stage low noise amplifier circuit is connected with the antenna for receiving radar echo signal, and the signal on antenna is put Greatly.As shown in Fig. 2 using MGA62563, normal range of operation increases in 20mA~80mA, working frequency in 0.1~3Ghz, single-stage Benefit constitutes dual-stage amplifier for 22db, and the signal of tens millivolts that antenna is received is amplified to hundreds of millivolts, transfers to take at a high speed Sample gate circuit is sampled;
Two-stage amplifying circuit is connected with high-speed sampling gate circuit, the signal of amplification is sent to by coupled capacitor C23 to be adopted The input of sample circuit is sampled, Fig. 5;
Such as Fig. 3, whole delay circuit uses MC100E195B, it is possible to use the D9-D0 pipes of FPGA control chip compared with Just 10ps stepping time delays can be realized;The square-wave signal that crystal oscillator is produced is produced with 10ps stepping time delays by MC100E195B Square-wave signal.
Such as Fig. 5, stepping time delay square-wave signal is by differential shaping network (C12, R14) the extraction pulse in ps generation circuits Edge, reduce square-wave signal dutycycle, preferably excite avalanche transistor.Its derivative constant τ is less than positive pulse edge Width.Snowslide circuit is made up of avalanche transistor, DC bias circuit and shaping network, and it can produce Gaussian pulse. We coordinate shaping network (C16, R19) we can obtain ps grades of pulse signal, the width of pulse after Gaussian pulse is produced Determined by the RC constant, τs of shaping network with amplitude.
After ps pulses generations, ps pulse signals and DC bias signal are superimposed, are on the one hand given to holding pipe and make To keep signal, while inputing to the base stage of Q2, there is a sampled signal for opposite in phase in the colelctor electrode by Q2, so just A pair of the holding signals and sampled signal of opposite in phase can be obtained.
Such as Fig. 5, sampling keeps signal to be connected with sample circuit, when pulse signal is high, Q2 conductings, and now Q3 leads Logical, Q4 cut-offs, the radar signal being exaggerated when Q3 is turned on keeps constant by Q3 to ground, the now voltage in holding capacitor, this When whole circuit be in hold mode;With should signal pulse be 0 when, Q2 cut-off, now Q3 cut-off, Q5 conducting, now put Big radar signal is sampled circuit and goes sampling by Q5 to output end, i.e. radar signal, and the voltage on holding capacitor C20 depends on In the voltage on collection follower is penetrated, whole circuit is in sampling state, here by we are used to 1Ghz's or so Signal is acquired, therefore our f of transistor for being usedtHave to be larger than 10Ghz;
Holding capacitor is connected with JFET (Q6), now just equivalent to having connect high impedance behind holding capacitor Resistance, the holding of the voltage being so more beneficial in holding capacitor, be unlikely to can be because can put in holding and sampling to rear class Electricity, and cause whole circuit to keep not living.Voltage in holding capacitor is formed by JFET and penetrates collection follower, and now we can be with The amplitude about 200mv or so for the holding voltage for obtaining.In order to make full use of the dose rate of ADC by the signal of 200mv or so and one The differential amplifier LMH6550 of individual double-input double-output is connected and the multiplication factor as shown in figure 4, differential circuit is amplified to it:
The output end for amplifying signal is connected with ADS822E, just can finally realize the place with low speed ADC to high-frequency signal Reason.
The output of circuit equivalent sample circuit emulate being exported eventually through the ADS simulation softwares of Agilent company Waveform is as shown in Figure 6.
Theoretically the speed of whole on-off circuit mainly depend on the performance of whole switching tube and the width of ps pulses and The minimum time delay of delay chip;As long as enough narrow and selected of the switching speed of triode is sufficiently fast, produce ps pulses Delay chip can provide sufficiently small time delay, we just can signal high infinite to frequency be acquired;
Finally keep signal to transfer to ADC treatment sampling, finally realize the signal that high frequency is processed with the ADC of low speed.
It should be appreciated that the part that this specification is not elaborated belongs to prior art.
Although the foregoing describing specific embodiment of the invention, it should be appreciated to those skilled in the art that these are only It is for example, various modifications or deformation can be made to these implementation methods, without departing from principle of the invention and essence.This The scope of invention is only limited by the claims that follow.

Claims (10)

1. the equivalent sampling circuit that a kind of application ground penetrating radar echo signals are gathered, it is characterised in that including:Two-stage low noise is put Big device, high-speed sampling gate circuit, ADC change-over circuits, Digital Signals circuit and ps pulse-generating circuits;
The two-stage low-noise amplifier, high-speed sampling gate circuit, ADC change-over circuits are sequentially connected, the ps pulses generations electricity Road is connected with Digital Signals circuit, high-speed sampling gate circuit respectively;
Wherein described two-stage low-noise amplifier connection receives the antenna of radar echo signal, for the signal on antenna to be carried out Amplify, the signal of amplification is sampled by the input that coupled capacitor is sent to high-speed sampling gate circuit;
The Digital Signals circuit is to produce a time delay adjustable using programmable gate array combination external crystal-controlled oscillation Square-wave signal;
The ps pulse-generating circuits are used to be converted into by the square-wave signal of time delay ps grades with time delay of pulse signal;
The high-speed sampling gate circuit is used to for time delay ps grades of pulse signal to form the sampling of opposite in phase and keeps signal, to putting ADC change-over circuits are sent into after big radar signal collection high-frequency signal part and elongation.
2. equivalent sampling circuit according to claim 1, it is characterised in that:Digital Signals circuit use can be compiled The D0-D9 of journey logic gate array control MC100E195B chips controls the time delay of square-wave signal.
3. equivalent sampling circuit according to claim 2, it is characterised in that:The time delay is 10ps stepping time delays.
4. equivalent sampling circuit according to claim 1, it is characterised in that:The ps pulse-generating circuits include snowslide electricity Road, snowslide circuit includes avalanche transistor, DC bias circuit and differential shaping network, and stepping time delay square-wave signal is by differential Shaping network extracts the edge of pulse, reduces the dutycycle of square-wave signal, and the square-wave signal of time delay is used as the defeated of avalanche transistor Enter signal using formation ps grades of pulse signal of time delay after the avalanche multiplication effect combination shaping network shaping of avalanche transistor.
5. equivalent sampling circuit according to claim 4, it is characterised in that:The derivative constant τ of the differential shaping network Less than the width at positive pulse edge.
6. equivalent sampling circuit according to claim 1, it is characterised in that:The high-speed sampling gate circuit includes triode Q2 and sampling door circuit, the ground level connection ps pulse-generating circuits of triode Q2, colelctor electrode connection sampling door circuit, emitter stage connect Ground.
7. equivalent sampling circuit according to claim 6, it is characterised in that:The sampling door circuit include triode Q3, Triode Q4, triode Q5 and holding capacitor, the ground level of the colelctor electrode connecting triode Q4 of triode Q2, the hair of triode Q4 The emitter stage of emitter-base bandgap grading connecting triode Q3, the emitter stage of the colelctor electrode connecting triode Q5 of triode Q4, the current collection of triode Q3 The ground level connection two-stage low-noise amplifier of pole and triode Q5, the emitter stage of triode Q5 is connected with holding capacitor.
8. equivalent sampling circuit according to claim 7, it is characterised in that:When the time delay ps grades of pulse signal is high, Triode Q2 is turned on, now triode Q3 conductings, triode Q4 cut-offs, when triode Q3 turn on exaggerated radar signal by Triode Q3 keeps constant to ground, the now voltage in holding capacitor, and now whole circuit is in hold mode;When time delay ps grades When pulse signal is 0, triode Q2 cut-offs, triode Q3 cut-offs, triode Q5 conductings, the radar signal being now exaggerated are passed through Triode Q5 is sampled circuit and goes sampling to output end, i.e. radar signal.
9. equivalent sampling circuit according to claim 8, it is characterised in that:Insulated-gate type is connected after the holding capacitor Effect pipe Q6, triode Q6 connection differential amplifier, the output end for amplifying signal is connected with ADC change-over circuits.
10. equivalent sampling circuit according to claim 9, it is characterised in that:The f of triode Q2 to the Q6tIt is more than 10Ghz。
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CN107272485A (en) * 2017-06-16 2017-10-20 中国科学院苏州生物医学工程技术研究所 A kind of pulse signal acquisition device and method based on low speed ADC
CN108459304A (en) * 2018-06-04 2018-08-28 南京邮电大学 A kind of ultra-wideband pulse generation circuit can be used for Ground Penetrating Radar detection
CN109633569A (en) * 2018-12-25 2019-04-16 北京华航无线电测量研究所 Larger Dynamic Ground Penetrating Radar sampling front-end gain control method and circuit
CN109901472A (en) * 2019-03-20 2019-06-18 电子科技大学 A kind of sequential equivalent system based on FPGA
CN110347096A (en) * 2019-08-08 2019-10-18 南京邮电大学 A kind of equivalent sampling circuit based on delays time to control
CN112180220A (en) * 2020-08-31 2021-01-05 山东信通电子股份有限公司 Time domain reflection signal data acquisition method and device

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CN107272485A (en) * 2017-06-16 2017-10-20 中国科学院苏州生物医学工程技术研究所 A kind of pulse signal acquisition device and method based on low speed ADC
CN108459304A (en) * 2018-06-04 2018-08-28 南京邮电大学 A kind of ultra-wideband pulse generation circuit can be used for Ground Penetrating Radar detection
CN109633569A (en) * 2018-12-25 2019-04-16 北京华航无线电测量研究所 Larger Dynamic Ground Penetrating Radar sampling front-end gain control method and circuit
CN109901472A (en) * 2019-03-20 2019-06-18 电子科技大学 A kind of sequential equivalent system based on FPGA
CN110347096A (en) * 2019-08-08 2019-10-18 南京邮电大学 A kind of equivalent sampling circuit based on delays time to control
CN112180220A (en) * 2020-08-31 2021-01-05 山东信通电子股份有限公司 Time domain reflection signal data acquisition method and device

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