CN112180220B - Time domain reflection signal data acquisition method and device - Google Patents
Time domain reflection signal data acquisition method and device Download PDFInfo
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- CN112180220B CN112180220B CN202010897130.5A CN202010897130A CN112180220B CN 112180220 B CN112180220 B CN 112180220B CN 202010897130 A CN202010897130 A CN 202010897130A CN 112180220 B CN112180220 B CN 112180220B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
- G01R31/11—Locating faults in cables, transmission lines, or networks using pulse reflection methods
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
- G01R31/081—Locating faults in cables, transmission lines, or networks according to type of conductors
- G01R31/086—Locating faults in cables, transmission lines, or networks according to type of conductors in power transmission or distribution networks, i.e. with interconnected conductors
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Abstract
The application discloses a time domain reflection signal data acquisition method and a time domain reflection signal data acquisition device, which aim to solve the problem that the existing time domain reflection signal sampling equipment is high in cost. The method comprises the following steps: the processor controls the gate array device to transmit pulse signals to the fault line to be detected, and the gate array device synchronously starts delay timing for sampling reflected signals corresponding to the transmitted signals; the transmitting signal is used for detecting the fault position of the fault line to be detected; the delay is timing relative to the transmission time of the transmission signal, and the delay time is different for each sampling; when the time is delayed to a preset sampling time point, the gate array device sends a Trig trigger signal to the low-speed ADC converter and the high-speed sampling holder so as to trigger the low-speed ADC converter to carry out single-point sampling on a reflection signal output by the high-speed sampling holder; the number of samples is related to the number of times the transmitted signal is emitted. According to the method, the low-speed ADC is adopted, and the purpose of reducing cost and realizing high-speed sampling is achieved by increasing sampling time and times.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for acquiring time domain reflection signal data.
Background
The Time-Domain Reflectometry (TDR) technology is widely applied in the fields of radar, cable fault testing and optical cable fault testing.
The existing time domain reflection signal acquisition is carried out in real time by amplifying and conditioning the signal and then transmitting the signal to an acquisition end of a high-speed ADC (Analog-to-Digital Converter) Converter. The acquisition frequency of the high-speed ADC converter needs to reach 100Mhz or even higher according to the measurement accuracy requirement. At present, high-speed signal acquisition is realized by increasing the number of ADC converters and staggering sampling time, and the method has the disadvantages of requiring a plurality of ADC converters, being higher in price and being more complex for controlling time sequence.
The existing technology aims at the collection of various high-speed signals, and under the measurement scene of time domain reflection, the cost performance of the existing sampling mode is not high, the price is high, and the overall price of the corresponding product cannot be reduced. The method is particularly not suitable for high-speed sampling of signals in the power transmission line.
Disclosure of Invention
The embodiment of the application provides a time domain reflection signal data acquisition method and a time domain reflection signal data acquisition device, which are used for solving the technical problem that the existing time domain reflection signal acquisition method is high in cost.
In one aspect, an embodiment of the present application provides a time domain reflection signal data acquisition method. The processor controls the gate array device to transmit pulse signals to the fault line to be detected, and the gate array device synchronously starts delay timing for sampling reflected signals corresponding to the transmitted signals; the transmitting signal is used for detecting the position of the fault line to be detected; the delay is timing started relative to the emission time of the emission signal, and the corresponding delay duration is different when the reflected signal is sampled each time; when the delay reaches a preset sampling time point, the gate array device sends a Trig trigger signal to the low-speed ADC converter and the high-speed sampling holder so as to trigger the low-speed ADC converter to perform single-point sampling on a reflection signal output from the high-speed sampling holder at the preset sampling time point; the number of single-point samples is related to the number of times the transmission signal is emitted.
In the instant of sending the emission signal, the embodiment of the application simultaneously starts the time delay timing for sampling the reflection signal corresponding to the emission signal so as to realize the sampling at different time delays for the reflection signal corresponding to the emission signal sent at each time. And each sampling is performed by triggering the low-speed ADC through the Trig trigger signal at a preset sampling point. So that the time point of sampling and the interval time of two samplings can be better controlled. And then by increasing the sending times of the transmitting signals, the sampling times and the sampling time of the reflected signals are increased, so that the aim of carrying out high-speed sampling by adopting a low-speed ADC with lower equipment cost is fulfilled.
In one implementation of the present application, before single-point sampling the reflected signal output in the high-speed sample-and-hold device, the method further comprises: the gate array device determines the Trig trigger signal generation time according to (n-1) x t; wherein t is a first preset time value of the Trig trigger signal delayed than the emission signal, and n is the acquisition frequency.
According to the embodiment of the application, the Trig trigger signal generation time is determined through a formula (n-1) x t, and then the time for sampling the reflection signals corresponding to the emission signals sent each time is determined. In this way, the sampling effect that the interval time between two adjacent sampling points is t can be obtained. And according to different test signals, properly adjusting the sampling points of the corresponding reflection signals. That is, by adjusting the size of t, higher measurement accuracy can be obtained, so that a more accurate sampling result can be obtained.
In one implementation of the present application, after single-point sampling of a reflection signal output in a high-speed sample-and-hold device, a method thereof includes: the processor receives a plurality of single-point sampling results from the low-speed ADC converter; and determining the fault position of the fault line to be detected according to the plurality of single-point sampling results.
In one implementation manner of the present application, before single-point sampling the reflection signal output from the high-speed sample holder, the method further includes: the gate array device generates Trig trigger signals at a preset sampling time point, so that the Trig trigger signals simultaneously trigger the high-speed sample holder, and the high-speed sample holder outputs sample hold signals.
The embodiment of the application generates the Trig trigger signal to trigger the low-speed ADC, and simultaneously outputs the sample-hold signal by the high-speed sample-holder. The output of the sample-and-hold signal and the sampling thereof can be synchronously performed. And then make the sampling point more accurate, the sampling result is also more accurate.
In one implementation manner of the present application, before the low-speed ADC converter performs single-point sampling on the reflection signal output from the high-speed sample holder at a preset sampling time point, the method further includes: after the gate array device controls the current transmitting signal to be sent out, the time interval between the current transmitting signal and the transmitting signal to be transmitted again is larger than or equal to a second preset threshold value; the second preset threshold is a time value required by the low-speed ADC for single-point sampling.
In the embodiment of the application, the low-speed ADC converter adopts single-point sampling, and the sampling speed is high. And the transmission interval time between two transmission signals is larger than or equal to the time value required by the low-speed ADC converter for carrying out single-point sampling. Therefore, the transmitted signal sent each time can be quickly sampled, so that the whole sampling process is simple and clear. The problem of more reflected signals accumulated in the high-speed sample holder is not caused.
In an implementation manner of the present application, the number of times of single-point sampling is related to the number of times of emission of the emission signal, which specifically includes: the number of single-point samples is the same as the number of transmitted signals.
In an implementation manner of the present application, after the processor controls the gate array device to transmit the pulse signal to the fault line to be tested, the method further includes: the gate array device controls the low-speed ADC to perform first single-point sampling on the head end of the reflected signal; and controlling the low-speed ADC to finish the last single-point sampling at the tail end of the reflected signal; the reflected signal is a periodic signal, the head end of the reflected signal refers to the start end point of the periodic signal, and the tail end of the reflected signal refers to the tail end point of the periodic signal.
According to the embodiment of the application, the initial end of the reflection signal corresponding to the first emission signal is sampled for the first time, and the tail end of the reflection signal corresponding to the last emission signal is sampled for the last time. Therefore, the head end and the tail end of the measurement signal are sampled, and the integrity of the whole sampling process can be ensured.
In one implementation manner of the present application, the method further includes: the holding signal end of the high-speed sampling holder is connected with the trigger end of the low-speed ADC converter and one output end of the gate array device.
In one implementation manner of the present application, before single-point sampling of the reflection signal output from the high-speed sample holder, the method further includes: the gate array device determines the time of delay according to the length of the reflected signal, and controls the longest time of delay not to exceed the length of the reflected signal; wherein the maximum time of the delay is the delay time required for the last sampling.
According to the embodiment of the application, the time of delay is controlled not to exceed the length of the reflection signal, so that the sampling time point of the low-speed ADC converter is ensured to be in the reflection signal, the data sampled every time are all data on the reflection signal, and the sampling accuracy is improved.
The embodiment of the application is connected with the trigger end of the low-speed ADC converter and one output end of the gate array device through the signal holding end of the high-speed sampling holder. The high-speed sample holder may be triggered and output a sample-and-hold signal at the same time that the Trig trigger signal triggers the low-speed ADC converter to sample the reflected signal. The output of the sampling holding signal and the sampling of the low-speed ADC are synchronously carried out, so that the sampling point in the sampling is more accurate, and the sampling result is more accurate.
The embodiment of the present application further provides a time domain reflection signal data acquisition device, including: the pulse transmitting equipment is used for transmitting a pulse signal to a fault line to be detected; the low-speed ADC is used for sampling a reflection signal corresponding to the transmission signal; a high-speed sample holder for holding the reflected signal; the gate array device is used for transmitting a pulse signal to a fault line to be detected after receiving the instruction of the processor, and synchronously starting delay timing for sampling a reflection signal corresponding to the transmission signal; the transmission signal is used for detecting the position of the transmission line with a fault; the delay is timing started relative to the emission time of the emission signal, and the corresponding delay duration is different when the reflected signal is sampled each time; the sampling device is used for sending Trig trigger signals to the low-speed ADC converter and the high-speed sampling holder when the time is delayed to a preset sampling time point so as to trigger the low-speed ADC converter to perform single-point sampling on the reflected signals output from the high-speed sampling holder at the preset sampling time point; the number of single point samples is related to the number of times the transmission signal is emitted.
According to the time domain reflection signal data acquisition method and the time domain reflection signal data acquisition device, the emission signals are sent to the power transmission line for multiple times, so that the sampling times of the signals to be detected are increased. By carrying out sampling delay timing on the reflected signal corresponding to each transmitted signal, different sampling points can be set for the reflected signal to be measured. Meanwhile, each time delay time is in a multiple relation, and finally a sampling effect graph with the same interval time of two adjacent sampling points can be presented. And after the preset sampling point is reached, the high-speed sampling holder is triggered to output a sampling holding signal through the Trig trigger signal, and the low-speed ADC converter is triggered to sample the signal output by the high-speed sampling holder, so that the accuracy of sampling the reflected signal is improved. According to the embodiment of the application, the sampling times and the sampling time are increased, so that the purpose of carrying out high-speed acquisition by using the low-speed ADC is achieved, and the cost of sampling equipment is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic structural diagram of a time domain reflection signal data acquisition device according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a time domain reflection signal data acquisition method according to an embodiment of the present disclosure;
fig. 3 is a pulse diagram of a time domain reflection signal data acquisition method according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of the number of sampling points provided in the embodiment of the present application;
fig. 5 is a schematic diagram of sampling time provided in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, time domain reflection signals are collected in real time after being amplified and conditioned and then transmitted to a collecting end of a high-speed ADC (Analog-to-Digital Converter) Converter. The sampling frequency of the high-speed ADC converter needs to reach 100Mhz or even higher depending on the measurement accuracy requirement. The high-speed ADC converter is expensive and difficult to purchase, has a higher requirement on the timing control speed of the ADC, and needs to be matched with an expensive FIFO (First Input First Output First in First out data buffer) memory. Currently, high-speed signal acquisition is realized by increasing the number of ADC conversions and staggering sampling time. The disadvantage of this method is that it requires a plurality of ADC converters, the price is also high, and the control sequence is also complicated.
In order to solve the above problems, the present application provides a method and an apparatus for acquiring time domain reflection signal data. By sending the transmitting signal for multiple times, the sampling times are increased, and the sampling accuracy is improved. The delay timing for sampling the reflection signal corresponding to the emission signal is synchronously started when the emission signal is emitted, and then the low-speed ADC converter is used for sampling. The sampling rate and speed requirements of the sample data processing are reduced in a manner that increases the sampling time. High-speed ADC converter and FIFO memory are not needed, and the equipment cost is reduced while higher measurement accuracy is obtained.
The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a time domain reflected signal data acquisition device according to an embodiment of the present application.
As shown in fig. 1, the time domain reflected signal data acquisition device is composed of a high speed sample holder 110, a low speed ADC converter 120, a gate array device 130, a pulse transmitting and receiving and signal conditioning circuit 140, and a processor 150. The gate array device 130 is designed by a programmable logic device. Programmable logic devices are emerging as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs). The gate array device of the embodiment of the application is realized by a programmable logic device, and a gate array device circuit with the required functions of the embodiment of the application is programmed by a programming language.
As shown in fig. 1, one output of the gate array device 130 is connected to an input of the pulse transmission and reception and signal conditioning circuit 140. The output of the pulse transmit and receive and signal conditioning circuit 140 is connected to the input of the high speed sample holder 110. The output terminal and the hold signal terminal of the high-speed sample holder 110 are connected to the input terminal and the trigger terminal of the low-speed ADC converter 120, respectively. Meanwhile, the hold signal terminal of the high-speed sample holder 110 is connected in parallel with the trigger terminal of the low-speed ADC converter 120 and another output terminal of the gate array device 130 as the Trig trigger signal output terminal. The data output of the low-speed ADC converter 120 is coupled to an input of a processor 150, and an output of the processor 150 is coupled to an input of a gate array device.
Those skilled in the art will appreciate that the pulse transmit and receive and signal conditioning circuitry 140 is implemented by a combination of circuitry having transmit, receive and signal conditioning functions.
According to the embodiment of the application, the low-speed ADC 120 is adopted for sampling data, so that the cost of sampling equipment is reduced. Furthermore, the signal holding end of the high-speed sample holder 110, the trigger end of the low-speed ADC converter 120, and the other output end of the gate array device 130 are connected in parallel to form a Trig trigger signal output end, so that the signal holding in the high-speed sampler 110 and the sampling in the low-speed ADC converter 120 can be synchronized, and the sampled data can be more accurate.
In another embodiment of the present application, the hold signal terminal of the high-speed sample-and-hold device 110 is connected to one output terminal of the gate array device 130; meanwhile, the data output terminal of the low-speed ADC converter 120 is connected to the other output terminal of the gate array device 130.
The connection mode of the embodiment of the present application may be a mode in which the gate array device 130 simultaneously sends out two Trig trigger signals to respectively trigger the high-speed sample holder 110 and the low-speed ADC converter 120. Therefore, the signal in the high-speed sampler 110 is kept synchronous with the sampling of the low-speed ADC converter 120, and the accuracy of the sampled data is ensured.
In one embodiment of the present application, the processor 150 controls the gate array device 130 to transmit a pulse signal to the line to be tested, and the transmitted signal reflects back a reflected signal when encountering a fault point in the power transmission line. The transmission signal in the embodiment of the application is used for detecting the position of the power transmission line with a fault. The gate array device 130 controls the transmission and reception of pulses and the transmission of signals by the signal conditioning circuit 140. The signal conditioning circuitry in pulse transmit and receive and signal conditioning circuitry 140 conditions the corresponding reflected signals, for example: the reflected signal is filtered, amplified, etc. The conditioned reflected signal enters the input of the high speed sample and hold unit 110 holds the input reflected signal.
In one embodiment of the present application, the gate array device 130 synchronously starts the delay timing of sampling the reflection signal corresponding to the transmission signal at the same time as the transmission signal is sent out. When the delay time reaches the sampling time point, the gate array device 130 triggers the Trig trigger signal to trigger the low-speed ADC converter 120 to perform single-point sampling on the signal output by the high-speed sample holder.
Specifically, the delay timing of the gate array device 130 sampling the reflection signal corresponding to each transmission signal is different. And the corresponding delay time of each transmitting signal is in a multiple relation. And the gate array device 130 controls the low-speed ADC sampler 120 through the delay to sample the reflected signal corresponding to the transmitted signal at a single point only when the delay-timed time arrives.
In the embodiment of the present application, by controlling the time of each time delay to be different, the low-speed ADC converter 120 can be controlled to sample different points of the reflected signal. Meanwhile, a delay sampling mode is adopted, proper delay time can be set according to the length of the reflected signal, multiple single-point sampling is carried out on the reflected signal, and therefore the effect of sampling of the high-speed ADC converter is achieved through the low-speed ADC converter.
In one embodiment of the present application, the processor 150 determines the location of the fault point in the power transmission line according to the data sampled by the plurality of low-speed ADC converters 120 at a single point.
Fig. 2 is a flowchart of a time domain reflection signal data acquisition method according to an embodiment of the present disclosure. As shown in fig. 2, the method for acquiring time domain reflection signal data specifically includes the following steps:
step S201, the processor 150 controls the gate array device 130 to transmit a pulse signal to the fault line to be detected, and the gate array device 130 synchronously starts delay timing for sampling a reflection signal corresponding to the transmission signal.
In one embodiment of the present application, the gate array device 130 controls a pulse transmitting apparatus in the pulse transmitting and receiving and signal conditioning circuit 140 to transmit a pulse signal to the power transmission line. When the transmission signal meets a fault point in the power transmission line, a corresponding reflection signal can be reflected. Pulse transmit and receive and signal conditioning circuitry 140 conditions the reflected signal and delivers it to the input of high speed sample holder 110 for signal retention.
In one embodiment of the present application, after the gate array device 130 receives the instruction from the processor 150, the emission signal is controlled to be emitted, and the delay timing for sampling the reflection signal corresponding to the emission signal is synchronously started.
Specifically, when the transmission signal is sent out, the gate array device 130 uses a programmable logic device to complete the function of delay timing by using assembly language. The delay time for sampling the reflected signals corresponding to different transmitting signals is different. And also sets the duration of each delay by the formula (n-1) × t. Wherein n is the acquisition times, and t is the time value of delay of the Trig trigger signal compared with the emission signal. And t is pre-calculated by the processor 150 based on the sample period to be achieved.
For example, when calculating the delay time of the second sampling of the low-speed ADC converter 120, the sampling number 2 is substituted into the above formula, and the delay time is calculated as t. Or, when calculating the delay time for sampling the third time by the low-speed ADC converter 120, the sampling number 3 is substituted into the above formula, and the delay time can be calculated to be 2 t.
It should be noted that, when the first transmission signal is sent out, the sampling of the corresponding reflection signal is synchronously started. Therefore, the delay time of the first sampling is 0.
The embodiment of the application performs different delay timing on the sampling time of the reflection signal corresponding to the transmission signal every time when the transmission signal is sent. The data acquisition can be carried out at different positions of the reflected signal, so that the aim of realizing high-speed sampling with smaller sampling interval by using a low-speed ADC (analog to digital converter) can be fulfilled.
In one embodiment of the present application, the processor 150 adjusts the sampling times and the delay timing of the reflected signals corresponding to different transmitted signals according to different signals to be measured. Where the delay is a timing relative to the start of the transmission time of the transmission signal. And, the number of transmission of the transmission signal coincides with the number of sampling by the low-speed ADC converter 120. Meanwhile, the processor 150 determines a time delay according to the length of the reflected signal, and controls the maximum time delay not to exceed the length of the reflected signal, wherein the maximum time delay is the time delay required by the last sampling.
For example, when the transmission signal is transmitted for the first time, the low-speed ADC converter 120 will then sample the start end of the corresponding reflection signal. When the transmission signal is transmitted for the second time, the gate array device 130 delays and times by 10ns to trigger the low-speed ADC converter 120 to sample the reflection signal corresponding to the second transmission signal. When the transmission signal is transmitted for the third time, the gate array device 130 delays and times 20ns to trigger the low-speed ADC converter 120 to sample the reflection signal corresponding to the third transmission signal. Thereby, an effect of sampling the reflected signal once every 10ns is achieved.
According to the embodiment of the application, the delay timing for sampling the corresponding reflection signal of the transmission signal is adjusted according to the difference of the transmission signal. Therefore, the problems of low analog-to-digital conversion speed and poor sampling effect of the low-speed ADC 120 are solved. Therefore, a more accurate sampling result can be obtained, and the specific position of the fault in the fault line to be detected can be accurately determined.
In step S202, the processor 150 controls the gate array device 130 to emit a Trig trigger signal, so that the Trig trigger signal triggers the low-speed ADC converter 120 to sample the reflected signal output by the high-speed sample holder 110.
In an embodiment of the present application, the gate array device 130 controls the Trig trigger signal to trigger the low-speed ADC converter 120 to sample the signal output by the high-speed sample holder 110 after the time of reaching the preset sampling point according to the formula (n-1) × t. Because, the present embodiment performs sampling based on the connection of the signal holding end of the high-speed sample holder 110, the trigger end of the low-speed ADC converter 120 and one output end of the gate array device 130. Alternatively, the gate array device 130 may synchronously issue two Trig trigger signals to trigger the high-speed sample holder 110 and the low-speed ADC converter 120 for sampling. Therefore, the Trig trigger signal generated when the preset sampling time point is reached simultaneously triggers the high-speed sample holder 110 to output the sample-and-hold signal. I.e., the signal sampled by the low-speed ADC converter 120.
The embodiment of the present application outputs the reflection signal and samples the reflection signal by triggering the high-speed sample holder 110 and the low-speed ADC converter 120 at the same time, respectively. The output of the sampling and holding signal and the sampling of the low-speed ADC converter can be synchronized, so that the sampling result is more accurate.
In one embodiment of the present application, the low-speed ADC converter 120 samples the reflected signal a single point as many times as the and gate array device 130 controls the emission of the transmitted signal.
In the embodiment of the present application, the low-speed ADC converter 120 samples only one reflection signal at a time. Therefore, in order to ensure that the sampling times are sufficient, a large number of transmission signals need to be transmitted, and different points of a plurality of reflection signals corresponding to the plurality of transmission signals need to be sampled. In this way, the low-speed ADC 120 can be used to perform single-point sampling on the signal to be measured at different sampling points, so as to obtain a sampling result with a smaller sampling point interval. The method and the device solve the problem that the sampling precision is low because the low-speed ADC 120 is low in conversion speed and cannot sample the signal to be detected for multiple times.
In one embodiment of the present application, the time interval between the emission of the current emission signal and the emission of the emission signal again controlled by the gate array device 130 is greater than or equal to the time value required by the low-speed ADC converter 120 to perform one single-point sampling on the reflection signal corresponding to the current emission signal.
In the embodiment of the present application, the time interval between the emission of the emission signal and the emission of the emission signal again is greater than or equal to the time value required for the low-speed ADC converter 120 to perform single-point sampling on the reflection signal corresponding to the current emission signal. Thereby ensuring that the low-speed ADC converter 120 has sufficient time for data conversion.
In an embodiment of the present application, when the low-speed ADC converter 120 samples the reflection signal, it needs to sample the starting end point of the reflection signal corresponding to the first transmitted transmission signal. In addition, the end point of the whole sampling process is the end point of the reflection signal corresponding to the transmission signal sent out at the last time.
The reflection signal in the embodiment of the application is a periodic signal, and the integrity of the sampling process can be realized by acquiring data of the starting endpoint and the ending endpoint of the reflection signal, so that the sampling result is more accurate.
And S203, the processor 150 determines the specific position of the fault in the power transmission line according to the sampling result of the low-speed ADC 120.
In one embodiment of the present application, the processor 150 determines the location of the fault point in the power transmission line according to the data sampled by the plurality of low-speed ADC converters 120 at a single point.
Fig. 3 is a pulse diagram of a time domain reflection signal data acquisition method according to an embodiment of the present application.
As shown in fig. 3, the triggering time of the Trig pulse signal is determined by the formula (n-1) × t compared with the time of the transmission signal.
In one embodiment of the present application, the time of the 1 st sample is when the gate array device 130 first sends out a transmit signal. The synchronous trigger Trig pulse signal triggers the low-speed ADC converter 120 to sample the reflected signal corresponding to the first transmitted signal.
In the embodiment of the present application, the time of the 2 nd sampling is to synchronously start the delay timing when the gate array device 130 sends the transmission signal for the second time. And when the preset delay time t is reached, the falling edge or low level of the Trig pulse signal is effective. Thereby triggering the low-speed ADC converter 120 to sample the reflected signal corresponding to the second transmitted signal.
In the embodiment of the present application, the 3 rd sampling time is the time when the gate array device 130 sends the transmission signal for the third time, and the delay timing is synchronously started. When the preset delay time 2t is reached, the falling edge or the low level of the Trig pulse signal is valid, so as to trigger the low-speed ADC converter 120 to sample the reflected signal corresponding to the third transmission signal.
According to the above delay law, the nth sampling time in the embodiment of the present application is to synchronously start the delay timing when the gate array device 130 sends the nth transmission signal. When the preset delay time (n-1) x t is reached, the falling edge or low level of the Trig pulse signal is valid, so as to trigger the low-speed ADC converter 120 to sample the reflected signal corresponding to the nth transmission signal.
In the embodiment of the application, the pulse is transmitted through the pulse transmitting equipment, and the transmitting time of the pulse signal and the Trig trigger signal is accurately controlled. The gate array device 130 starts delay timing at the same time when transmitting the pulse signal each time, and triggers the Trig pulse signal after delaying for different time lengths, so that the purpose of sampling the reflected signal at different time points can be realized. And the preset delay time is determined according to (n-1) x t, and the duration of t can be adjusted. Therefore, the number of the sampling points can be adjusted according to the time length of the signal to be measured, the sampling result is more accurate, and the position of the fault point is more accurately determined.
Fig. 4 is a schematic diagram of the number of sampling points provided in the embodiment of the present application. The sampling effect achieved is illustrated by a specific embodiment, as shown in fig. 4.
In one embodiment of the present application, in the image shown in fig. 4, the abscissa is the number of sampling points, and the ordinate is the amplitude of the sampled data. The sampling time interval of two adjacent sampling points is 10 ns.
In the embodiment of the present application, the number of sampling data points of the reflection signal in the abscissa is 47, and then the processor 150 controls the gate array device 130 to send the transmission signal 47 times.
Specifically, the abscissa sampling points 1 to 47 of the sampling point number diagram are sampling points for performing data acquisition after the corresponding reflection signals respectively delay different times from the first time of the transmission signal to the 47 th time of the transmission signal. The ordinate corresponding to the number of abscissa sampling points 1 is a data value obtained by sampling the start end of the reflected signal corresponding to the first transmission signal by the low-speed ADC converter 120.
The abscissa in the embodiment of the present application samples the ordinate corresponding to the number 2. The synchronous delay is timed 10ns after the low-speed ADC converter 120 sends out the second transmission signal. And sampling the reflected signal corresponding to the second emission signal to obtain a data value.
The abscissa in the embodiment of the present application corresponds to the sampling point number 3. The low-speed ADC converter 120 is synchronized 20ns later when the third transmission signal is sent. And sampling the reflected signal corresponding to the third transmitted signal to obtain a data value.
Similarly, the delay time law is counted. The ordinate corresponding to the abscissa sampling point number 47 in the embodiment of the present application is when the low-speed ADC converter 120 transmits the signal in the fourth seventeenth transmission. And after the synchronous delay timing is 460ns, sampling the reflection signal corresponding to the forty-seventh transmission signal to obtain a data value.
In one embodiment of the present application, a reflected signal corresponding to the first transmitted signal is reflected to a reflected signal corresponding to the seventeenth transmitted signal. Respectively delaying for 0ns, 10ns, 20ns, 30ns and the like, and delaying for 10ns more than the last time. The reflected signal corresponding to the seventeenth transmission signal is sampled with the delay of 460 ns. And arranging all sampled data according to the sampling sequence. The sampling effect of 47 data acquisition points sampled every 10ns is achieved.
In the embodiment of the present application, the sampling manner adopted in the embodiment of the present application can be clearly and clearly explained by listing specific data of 47 times of sampling. The sampling interval can be controlled by delaying different time, thereby solving the problems that the low-speed ADC converter has low conversion rate and less sampling times of the signal to be detected. According to the embodiment of the application, a relatively accurate sampling result can be obtained by using the low-speed ADC. Therefore, the problem that the cost of equipment required by data sampling by adopting a high-speed ADC converter is high in the prior art is solved.
Fig. 5 is a schematic diagram of sampling time provided in an embodiment of the present application. As shown in fig. 5, the abscissa is the number of sampling points for sampling the reflection signal at a time, and the ordinate is the magnitude of the amplitude. The bar is the time period for which the high speed sample holder 110 signal holds and the low speed ADC converter 120 samples.
Specifically, the embodiment of the present application is further described on the basis of the embodiment of the sampling data described in fig. 4. By sampling data 47 times, the number of sampling points on the abscissa is 47 times. The sampling time between two adjacent sampling points is 10 ns. And the data collected by the low-speed ADC converter 120 each time is set to DATAn, and n is the number of sampling times. Wherein the value range of n in the embodiment of the application is 1-47.
In one embodiment of the present application, a bar between the number of abscissa sample points 1 and the number of sample points 2. Is the time period during which the high speed sample holder 110 holds the signal and the low speed ADC converter 120 samples the reflected signal corresponding to the first transmitted signal. A time period 1 is set, the time period 1 of which is shorter than the time interval between the first transmission signal and the second transmission signal. The ordinate of the time period 1 is a data value obtained by sampling the reflected signal corresponding to the first transmitted signal in the current time period 1.
In one embodiment of the present application, the abscissa samples the bar between points 2 and 3. Is the time period during which the high speed sample holder 110 holds the signal and the low speed ADC converter 120 samples the reflected signal corresponding to the second transmitted signal. A time period 2 is set, the time period 2 of which is shorter than the time interval between the second transmission signal and the third transmission signal. The ordinate of the time period 2 is a data value obtained by sampling the reflected signal corresponding to the second transmission signal in the current time period 2.
According to the rule of the above embodiment, the required time period 47 for signal holding and data acquisition of the reflection signal corresponding to the forty-seventh transmission signal is a short horizontal line between the number of sampling points 47 and the number of sampling points 48. Likewise, the time duration of the time period 47 is shorter than the time interval between the forty-seventeenth transmission signal and the forty-eighth transmission signal. Time period 47 is on the ordinate with the data value of the fourth seventeen samples.
The embodiment of the application shows the effect of collecting data once in 10ns by enumerating 47 times of sampling data and arranging the data according to the sampling sequence. It can be clearly seen that the sampling scheme adopted in the embodiments of the present application is to reduce the sampling rate of the low-speed ADC converter and the subsequent speed requirement for data processing by increasing the sampling time and the sampling times. The purpose of high-speed sampling is achieved through the low-speed ADC converter, and therefore equipment cost is reduced.
It should be noted that, when the embodiment of the present application samples the reflection signal, the number of the general sampling data is about 2000, and the transmission signal needs to be sent out for the corresponding number of times. The quantity of the sampling data and the time delay sampling time can be adjusted by matching with the corresponding test signals so as to obtain higher measurement precision.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A method for time domain reflected signal data acquisition, the method comprising:
the method comprises the following steps that a processor controls a gate array device to transmit pulse signals to a fault line to be detected, and the gate array device synchronously starts delay timing for sampling reflection signals corresponding to the transmission signals; the transmitting signal is used for detecting the position of the fault line to be detected; the delay is timing started relative to the transmitting time of the transmitting signal, and the corresponding delay time lengths are different when the reflected signal is sampled every time;
when the delay reaches a preset sampling time point, the gate array device sends a Trig trigger signal to a low-speed ADC (analog to digital converter) and a high-speed sampling holder so as to trigger the low-speed ADC to perform single-point sampling on a reflection signal output from the high-speed sampling holder at the preset sampling time point;
the number of the single-point sampling is related to the number of the emission signal.
2. A method for time domain reflectometry signal data acquisition as in claim 1 wherein prior to single point sampling of the reflectometry signal output from the high speed sample holder, the method further comprises:
the gate array device determines the Trig trigger signal generation time according to (n-1) x t;
wherein t is a first preset time value of the Trig trigger signal delayed than the emission signal, and n is the acquisition frequency.
3. A time domain reflectometry signal data acquisition method as in claim 1 wherein after said single point sampling of the reflectometry signal output from the high speed sample holder, the method comprises:
the processor receives a plurality of single-point sampling results from the low-speed ADC converter;
and determining the fault position of the to-be-detected fault line according to the plurality of single-point sampling results.
4. A method for time domain reflectometry signal data acquisition as in claim 1 wherein prior to single point sampling of the reflectometry signal output from the high speed sample holder, the method further comprises:
and the gate array device generates a Trig trigger signal at the preset sampling time point, so that the Trig trigger signal triggers the high-speed sample holder at the same time, and the high-speed sample holder outputs a sample hold signal.
5. The time-domain reflectometry signal data acquisition method of claim 1, wherein the low speed ADC converter performs a single point sampling of the output reflectometry signal from the high speed sample holder at the predetermined sampling time point, the method further comprising:
after the gate array device controls the current transmitting signal to be sent out, the time interval between the current transmitting signal and the transmitting signal to be transmitted again is larger than or equal to a second preset threshold value; the second preset threshold is a time value required by the low-speed ADC for single-point sampling.
6. The method according to claim 1, wherein the number of times of the single-point sampling is related to the number of times of the emission signal emission, specifically comprising:
the number of the single-point sampling is the same as that of the transmitting signal.
7. The time domain reflection signal data collection method according to claim 1, wherein after the processor controls the gate array device to transmit the pulse signal to the fault line to be tested, the method further comprises:
the gate array device controls the low-speed ADC to perform first single-point sampling on the head end of the reflected signal; and is
Controlling the low-speed ADC to finish the last single-point sampling at the tail end of the reflected signal;
the reflected signal is a periodic signal, the head end of the reflected signal refers to the start end point of the periodic signal, and the tail end of the reflected signal refers to the end point of the periodic signal.
8. The time domain reflection signal data acquisition method of claim 4, wherein:
the holding signal end of the high-speed sampling holder is connected with the trigger end of the low-speed ADC converter and an output end of the gate array device.
9. A method for time domain reflectometry data acquisition as in claim 1 wherein before single point sampling of the output reflectometry signal from the high speed sample holder, the method further comprises:
the processing device determines the time of the time delay according to the length of the reflected signal, and controls the maximum time of the time delay not to exceed the length of the reflected signal; wherein the maximum time of the delay is the delay time required by the last sampling.
10. A time domain reflected signal data acquisition device, comprising:
the pulse transmitting equipment is used for transmitting a pulse signal to a fault line to be detected;
the low-speed ADC is used for sampling a reflection signal corresponding to the transmission signal;
a high-speed sample holder for holding the reflected signal;
the gate array device is used for transmitting a pulse signal to a fault line to be detected after receiving the instruction of the processor, and synchronously starting delay timing for sampling a reflected signal corresponding to the transmitted signal; the transmitting signal is used for detecting the position of the fault line to be detected; the delay is timing started relative to the transmitting time of the transmitting signal, and the corresponding delay time lengths are different when the reflected signal is sampled every time; and
the device comprises a trigger signal sending unit, a sampling unit and a sampling unit, wherein the trigger signal sending unit is used for sending a Trig trigger signal to a low-speed ADC (analog to digital converter) and a high-speed sampling holder when delaying to a preset sampling time point so as to trigger the low-speed ADC to perform single-point sampling on a reflection signal output from the high-speed sampling holder at the preset sampling time point;
the number of single-point sampling is related to the number of emission times of the emission signal.
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| US8222906B2 (en) * | 2008-06-19 | 2012-07-17 | Paul Francis Wyar | Adaptive pulse width time domain reflectometer |
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