CN1114286C - High-speed data acquisition and real-time accumulation circuit for light-time domain reflectometer - Google Patents
High-speed data acquisition and real-time accumulation circuit for light-time domain reflectometer Download PDFInfo
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- CN1114286C CN1114286C CN00107855A CN00107855A CN1114286C CN 1114286 C CN1114286 C CN 1114286C CN 00107855 A CN00107855 A CN 00107855A CN 00107855 A CN00107855 A CN 00107855A CN 1114286 C CN1114286 C CN 1114286C
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Abstract
The present invention relates to a circuit for high speed data acquisition and real-time accumulation, which is used for optical time domain reflectometers in high dynamic ranges. The circuit comprises a pulse signal generating circuit, a pulse parameter and logical control unit, an analogue-digital converter, a high-speed memory, a buffer memory, a microprocessor unit, a clock signal unit and a signal processing unit, wherein the pulse signal generating circuit is used for providing driving pulses for a light transmitter; the analogue-digital converter is used for quantizing analog signals output by a light receiver; the high-speed memory with a certain capacity is used for storing the sampled and accumulated data of the ordinal positions of optical fibers to be measured; and the buffer memory is used for transferring and storing the sampled and accumulated data stored in the high-speed memory after sampling and accumulating. The circuit can realizes high resolution processing, high speed data acquisition processing and real-time accumulating processing.
Description
The present invention relates to a kind of circuit design, exactly, relate to a kind of high-speed data acquisition of high dynamic range optical time domain reflectometer and circuit of real-time accumulation process of being used for, belong to the Pulse and Digital Circuits technical field.
Optical time domain reflectometer OTDR (Optical Time-Domain Reflectometry) is the measuring instrument of a kind of measuring optical fiber link performance, positioning optical waveguides line fault point.Its operation principle is: by the back-scattering light of test pulse laser on optical fiber transmission line in time the energy distribution curve analysis of (distance) obtain the transmission characteristic such as length, decay, fault of optical fiber, promptly utilize laser to light pulse of tested optical fiber input, when light pulse when fibre circuit is propagated forward, scattering and reflect part signal; Optical time domain reflectometer is in optical fiber transmitted pulse signal, the part signal of monitoring this scattering and reflecting at its same end, and to this because the variation of Fresnel reflection, Rayleigh scattering and fiber medium and scattering and the signal that reflects carry out the continuous high speed sampling processing, thereby obtain characteristics such as the signal transmission attenuation of fibre circuit and Fault Diagnosis location.
Optical time domain reflectometer mainly is made up of two parts: light emission and receiving circuit, data acquisition and treatment circuit.Dynamic range (DR) is one of important indicator of optical time domain reflectometer, and it has directly reflected the length scale of the optical fiber of optical time domain reflectometer institute energy measurement; The length of tested optical fiber is long more, and the dynamic range of needed optical time domain reflectometer is also big more.
The method that improves the measurement dynamic range (DR) of optical time domain reflectometer mainly contains: a. increases the laser emitted energy in light emission and the receiving circuit.Because the characteristic of laser is determined by device property that mainly the raising of its emitted energy is limited.B. increase the test average time in data acquisition and the treatment circuit.Dynamic range has following relation with the test average time:
Wherein, N represents to test average time, and Δ DR represents the variable quantity of dynamic range.Will cause the prolongation of testing time owing to increase the test average time, therefore this increase also is limited.
Traditional optical time domain reflectometer adopts the laser of peak power at that time on the one hand in light emission and receiving circuit, also improve the average time of test on the other hand in data acquisition and treatment circuit as far as possible.But, because sample frequency is lower, generally be no more than 8MHz, therefore in order to improve resolution, (Interleaving) sampling that must interlock, thus to increase the testing time, reduce the average time of test.In addition, the realization of test point average algorithm, generally be after laser pulse of emission and sampling finish, read measurement data by software from the data working area by central processing unit, and the last time accumulation result of these data and cumulative data memory block added up obtain this accumulation result, deposit the cumulative data memory block then again in, when measuring distance is far, number of test points also can be a lot, and such computing unavoidably seriously takies Measuring Time.After measurement was finished, general method was, CPU is carried out read operation by software to the cumulative data memory block, and the line data of going forward side by side is handled and event analysis, will certainly postpone the follow-up test under the real-time testing pattern like this.All these all can reduce the test average time indirectly, do not reach the requirement that as far as possible improves dynamic range.
The purpose of this invention is to provide a kind of high-speed data acquisition of high dynamic range optical time domain reflectometer and circuit of real-time accumulation process of being used for, this circuit is used for beam of laser is transmitted into tested optical fiber, the back scattering in the while detection fiber and the optical time domain reflectometer (OTDR) of reflected signal, this circuit has overcome many defectives of the prior art, realizes high-resolution, high-speed data acquisition and real-time accumulation process.
The object of the present invention is achieved like this: comprise pulse signal generating circuit and a pulse parameter and a logic control element that driving pulse is provided to optical transmission circuit, the a certain A/D converter that constantly begins the analog signal that optical receiver is exported is quantized of setting before pulse laser is transmitted into this tested optical fiber, the fast storage of the sampling cumulative data of this tested optical fiber ordinal position that this A/D converter of the storage with a constant volume quantizes, one at the add up buffer memory of the sampling cumulative data unloading of storing in this fast storage after finishing of sampling, and logic control element carried out programme controlled microprocessor unit, the clock signal unit and the signal processing unit of clock signal is provided to logic control element.
Wherein A/D converter spare is to be 25MSPS to the back scattering of ordinal position in the aforementioned tested optical fiber and the frequency that reflected signal is sampled, 12 A/D converter spare.
Wherein be provided with delayer in the logic control element, the minimum delay time that this delayer can carry out was 0.15625 nanosecond, can realize promptly that also minimum resolution reaches staggered (Interleaving) Sampling techniques of 0.015625 meter.
Wherein fast storage is to adopt push-up storage FIFO realization synchronously fast.
Wherein adopt hardware circuit to realize the adding up in real time of sampled data of aforementioned tested optical fiber ordinal position in the logic control element.
Adopt static memory as buffer memory, improve data sampling speed to realize caching technology.
Adopt pipeline system to finish the pulse data sampling, read last time cumulative data, add operation, store the signal processing operations of this cumulative data.
Technical characterstic of the present invention is: reduce the number of times of interlaced sampling and improve sampling resolution by improving sample frequency, realize adding up in real time and the method that adopts fast push-up storage synchronously to store cumulative data has solved the problem of accumulating operation engaged test time by hardware circuit, and solved the occupied and problem that can't carry out follow-up test in cumulative data memory block under the real-time testing pattern by the method for introducing the buffer memory district, pass through pipeline work again, solved the problem that under the prerequisite that guarantees sample rate, reduces hardware cost, increased the test average time in the time as far as possible thereby reached at same test, improve the purpose of the test dynamic range of optical time domain reflectometer.
Specifically introduce structure, operation principle and the effect of circuit of the present invention below in conjunction with drawings and Examples:
Fig. 1 is the data acquisition of optical time domain reflectometer and the electric functional-block diagram of treatment circuit of being used for of the present invention.
Fig. 2 is the internal electrical functional-block diagram of logic control element among Fig. 1.
Fig. 3 is the sequential chart of the pipeline work of Fig. 2 logic control element.
Referring to Fig. 1, the present invention is data acquisition and the treatment circuit in the optical time domain reflectometer, and Fig. 1 has showed the operation principle of circuit of the present invention.Optical time domain reflectometer adopts an optical transmitting set 5, is connected to tested optical fiber 1 by coupler 3 and connector 2, and optical transmitting set 5 is driven by data acquisition of the present invention and treatment circuit 6.4 backscatter signal of optical receiver by coupler 3 reception tested optical fiber 1, and export corresponding analog electrical signal, this analog signal is then received by data acquisition of the present invention and treatment circuit 6 and gathers and accumulation process.
Data acquisition processing circuit 6 of the present invention comprises pulse signal generating circuit and a pulse parameter and a logic control element 14 that driving pulse can be provided to optical transmitting set 5, the A/D converter 13 that can a certain setting moment before pulse laser is transmitted into this tested optical fiber begin the analog signal that optical receiver 4 is exported is quantized, fast storage---push-up storage (FIFO) 15 synchronously fast with the sampling cumulative data that can store this tested optical fiber ordinal position that this A/D converter quantizes of a constant volume, one sampling add up finish after with this fast storage 15 in the buffer memory 16 of sampling cumulative data unloading of storage, and microprocessor unit 10, signal processing unit 11, clock signal unit 12 parts such as grade are formed.Referring to the internal electrical functional-block diagram of logic control element shown in Figure 2 14, introduce operation principle of the present invention.
Before beginning test, microprocessor unit 10 writes pulse duration register 20, pulse daley register 21, sampling number register 22 and number of repetition register 23 in the logic control element 14 respectively with set points such as pulse duration, pulse daley, sampling number, numbers of repetition, starts automatic testing process by control register 24 then.In automatic testing process, microprocessor unit 10 can read the state indicated value of " whether test is finished " from status register 25.
After starting test automatically, the laser pulse in the logic control element 14 produces circuit 35, delayer 36, sampling number counting circuit 40, repeated sampling counting circuit 39 and loads set point from pulse duration register 20, pulse daley register 21, sampling number register 22 and number of repetition register 23 automatically respectively.Laser pulse produces circuit 35 and produces the pulse signal of setting width automatically, and postpones to output to optical transmitting set 5 behind the setting-up time through delayer 36.In the laser pulse signal generation with in optical fiber emission output, sampling number counting circuit of the present invention just begins control survey, cumulative process: A/D conversion control circuit 37 control A/D converting units 13 are sampled, 38 controls of FIFO read-write control circuit are read the last time cumulative data of the same test point of storing among the fast synchronous push-up storage FIFO15 (to each test point, last time cumulative data when sampling for the first time is 0), data latching control circuit 32 control lock storage 31a, 31b latchs the data of A/D converting unit 13 outputs and the last time cumulative data of being exported by FIFO15 respectively, after adder 30 was carried out add operation, data latching control circuit 32 control lock storage 31c latched this cumulative data.This cumulative data that FIFO read-write control circuit 38 latchs latch 31c writes fast push-up storage FIFO15 synchronously.This processing procedure adopts pipeline control mode as shown in Figure 3.After sampling set point number, repeated sampling counting circuit 39 is counted, and when the not enough set point number of number of repetition, sampling number counting circuit 40 loads set point from sampling number register 22 again, and carries out next round sampling cumulative process again.After number of repetition reaches set point number, the repeated sampling counting circuit 39 reset samples counting circuit 40 of counting, and start automatic unloading control circuit 34, isolator 33 is opened.
After automatic unloading begins, automatically unloading control circuit 34 loads from sampling number register 22 automatically and sets sampling number, control FIFO read-write control circuit 38 then and read the sampling cumulative data of storage from fast synchronous push-up storage FIFO15, the cumulative data of will sampling of unloading control circuit 34 automatic generations simultaneously automatically writes buffer memory 16 required address, control signal, finishes write operation.Automatically unloading control circuit 34 is after the sampling cumulative data unloading that will set sampling number finishes, and sends the unloadings index signal that finishes to signal processing unit 11, and while status register 25 corresponding positions are changed to effectively.
Microprocessor unit 10 detects unloading and finishes behind the state, can start the cumulative process of next time sampling again.
Signal processing unit 11 detect unloading finish index signal effectively after, read the sampling cumulative data from buffer memory 16, can carry out signal processing and event analysis subsequently.
Referring to the pipeline work sequential chart of sampled signal accumulation process process of the present invention shown in Figure 3, t
wBe the width that drives the pulse signal of optical transmitting set 5, span: 10ns～20us; T
sIt is the read-write clock cycle (40ns) of A/D sampling clock cycle and FIFO; N is each sampling number; t
1It is the time difference that drives between first change over clock rising edge of the forward position of pulse signal of optical transmitting set 5 and A/D converter, in order to realize interlaced sampling, t
1Span 0～40ns; t
2Being the time difference of A/D converter change over clock rising edge and latch 31a latch clock rising edge, also is the time difference that FIFO reads rising edge clock and latch 31b latch clock rising edge, is worth to be T
s(40ns); t
3Be time difference of rising edge of the latch clock of the latch clock rising edge of latch 31a, 31b and latch 31c, be worth and be T
s(40ns); t
4Be the time difference between the rising edge clock write of the latch clock rising edge of latch 31c and FIFO, be worth and be T
s(40ns).In this pipeline work, add up total ascent time of storing process of the sampling of every bit is t
2+ t
3+ t
4(120ns), be t the blanking time of storing process but the sampling of adjacent point-to-point transmission adds up
2(40ns), guarantee the sampling rate of 25MSPS so on the one hand, also guaranteed the abundant intensity that the sampling of single test point adds up memory time on the other hand.
Circuit of the present invention mainly adopts four kinds of technical measures to improve signals sampling, storage, computing and processing speed:
(1) select for use sample frequency to carry out data sampling greater than 25MSPS, 12 A/D device, and can interlock (Interleaving) sampling and expand sample frequency to 256 times, 0.15625 nanosecond of minimum delay time (40ns/256) of the used delayer of interlaced sampling, thereby minimum sampling resolution can reach 0.015625 meter (in OTDR, consider the back and forth propagation of light in optical fiber, its propagation velocity was about for 1 meter/10 nanoseconds).
(2) utilize hardware circuit to carry out add operation, thereby improve arithmetic speed greatly, realize in real time accumulating operation automatically; And test data working area and cumulative data memory block merged, adopting access rate is that 65536 * 32 synchronous push-up storage FIFO is as the cumulative data memory block greater than 25MHz, capacity.Because push-up storage does not need address signal synchronously, and can carry out read-write operation simultaneously, not only simplifies control logic, and avoids carrying out the time delay that read-write operation caused simultaneously.
(3) proceed to when setting average time and need carry out data processing and event analysis when accumulating operation, adopt caching technology, cumulative data is dumped to the buffer memory district automatically from the cumulative data memory block, for follow-up test.Since not frequent to the buffer memory operation, therefore select for use the static memory of general read or write speed (about 70ns), 65536 * 32 bit capacities as buffer memory.
(4) since sample frequency up to 25MSPS, the hardware circuit that only has very fast speed could be finished sampling, reads last time cumulative data, add operation, store operations such as this cumulative data in 40 nanoseconds of sampling period, the present invention decomposes these operations, adopt pipeline work to realize it, can reduce requirement, thereby reduce hardware cost hardware circuit speed.
The present invention manufactures experimently out the sample circuit, and tests enforcement on light time domain test instrument, has reached designing requirement and goal of the invention, is a kind of circuit that can realize high-resolution, high-speed data acquisition and real-time accumulation process.
Claims (7)
1, a kind of high-speed data acquisition of high dynamic range optical time domain reflectometer and circuit of real-time accumulation process of being used for, it is characterized in that: comprise pulse signal generating circuit and a pulse parameter and a logic control element that driving pulse is provided to optical transmission circuit, the a certain A/D converter that constantly begins the analog signal that optical receiver is exported is quantized of setting before pulse laser is transmitted into this tested optical fiber, the fast storage of the sampling cumulative data of this tested optical fiber ordinal position that this A/D converter of the storage with a constant volume quantizes, one at the add up buffer memory of the sampling cumulative data unloading of storing in this fast storage after finishing of sampling, and logic control element carried out programme controlled microprocessor unit, the clock signal unit and the signal processing unit of clock signal is provided to logic control element.
2, the high-speed data acquisition as claimed in claim 1 and the circuit of accumulation process in real time, it is characterized in that: wherein A/D converter spare is to be 25MSPS to the back scattering of ordinal position in the aforementioned tested optical fiber and the frequency that reflected signal is sampled, 12 A/D converter spare.
3, the high-speed data acquisition as claimed in claim 1 and the circuit of accumulation process in real time, it is characterized in that: wherein be provided with delayer in the logic control element, the minimum delay time that this delayer can carry out was 0.15625 nanosecond, can realize promptly that also minimum resolution reaches staggered (Interleaving) Sampling techniques of 0.015625 meter.
4, the high-speed data acquisition as claimed in claim 1 and the circuit of accumulation process in real time is characterized in that: wherein fast storage is to adopt push-up storage FIFO realization synchronously fast.
5, high-speed data acquisition as claimed in claim 1 and the in real time circuit of accumulation process is characterized in that: wherein adopt hardware circuit to realize the adding up in real time of sampled data of aforementioned tested optical fiber ordinal position in the logic control element.
6, the high-speed data acquisition as claimed in claim 1 and the circuit of accumulation process in real time is characterized in that: adopt static memory as buffer memory, improve data sampling speed to realize caching technology.
7, high-speed data acquisition as claimed in claim 1 and the in real time circuit of accumulation process is characterized in that: adopt pipeline system to finish the pulse data sampling, read last time cumulative data, add operation, store the signal processing operations of this cumulative data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN00107855A CN1114286C (en) | 2000-06-27 | 2000-06-27 | High-speed data acquisition and real-time accumulation circuit for light-time domain reflectometer |
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| CN00107855A CN1114286C (en) | 2000-06-27 | 2000-06-27 | High-speed data acquisition and real-time accumulation circuit for light-time domain reflectometer |
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| CN1330266A CN1330266A (en) | 2002-01-09 |
| CN1114286C true CN1114286C (en) | 2003-07-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100470284C (en) * | 2006-12-13 | 2009-03-18 | 中国科学院等离子体物理研究所 | Series one divided into two optic fiber converter |
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|---|---|---|---|---|
| CN102142892B (en) | 2010-06-30 | 2014-12-17 | 华为技术有限公司 | Method for producing probe pulse and coherent light time-domain reflector |
| CN102455246B (en) * | 2011-12-12 | 2014-07-02 | 山东信通电器有限公司 | Low-noise and anti-interference optical-time-domain reflectometer with secondary shielding |
| US20130221974A1 (en) * | 2012-02-29 | 2013-08-29 | GM Global Technology Operations LLC | Time domain reflectometry system and method |
| CN103323215B (en) * | 2013-05-20 | 2015-11-25 | 中国电子科技集团公司第四十一研究所 | A kind of light time domain reflection measuring apparatus and method |
| CN103344562A (en) * | 2013-07-24 | 2013-10-09 | 中国船舶重工集团公司第七二五研究所 | Multi-point optical fiber corrosion monitoring device |
| CN106487442A (en) * | 2016-07-31 | 2017-03-08 | 苏州英克迈信息科技有限公司 | A kind of fast fibre detecting system |
| US11329663B2 (en) * | 2018-08-21 | 2022-05-10 | Commsolid Gmbh | Analog to digital converter |
| CN110736877B (en) * | 2019-09-26 | 2021-09-28 | 山东信通电子股份有限公司 | High-speed acquisition method and device for time domain reflection signals |
| CN112180220B (en) * | 2020-08-31 | 2022-09-20 | 山东信通电子股份有限公司 | Time domain reflection signal data acquisition method and device |
| CN113783607B (en) * | 2021-08-30 | 2023-04-14 | 昂纳科技(深圳)集团股份有限公司 | Double-clock wrong-phase sampling device and sampling method thereof, and optical time domain reflectometer |
-
2000
- 2000-06-27 CN CN00107855A patent/CN1114286C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100470284C (en) * | 2006-12-13 | 2009-03-18 | 中国科学院等离子体物理研究所 | Series one divided into two optic fiber converter |
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| CN1330266A (en) | 2002-01-09 |
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