CN106685416A - Oscillation circuit device - Google Patents
Oscillation circuit device Download PDFInfo
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- CN106685416A CN106685416A CN201610959068.1A CN201610959068A CN106685416A CN 106685416 A CN106685416 A CN 106685416A CN 201610959068 A CN201610959068 A CN 201610959068A CN 106685416 A CN106685416 A CN 106685416A
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- 230000010355 oscillation Effects 0.000 title abstract description 6
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 238000001514 detection method Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 230000007704 transition Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 240000002853 Nelumbo nucifera Species 0.000 description 2
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- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 238000003780 insertion Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
An oscillation circuit device capable of, suppressing a fluctuation in the frequency of an output signal (CLK) when detecting an input reference signal and making a transition from a self-running state to a PLL operation to thereby obtain a smoothly-synchronized and stable output signal (CLK) is provided. In a self-running state, a V/I conversion element to which one end of a filter circuit is connected, and a buffer circuit form a negative feedback circuit, and a capacitor in the filter circuit is charged rapidly in such a manner that an output signal (CLK) can be started from a frequency equal to that in the self-running state immediately after a transition to a PLL operation.
Description
Technical field
The present invention relates to a kind of include phase locking circuit (phase locked loop circuits, hereinafter referred to as PLL circuit)
Oscillating circuit arrangement, the phase locking circuit applies feedback control controlling phase place to the reference signal being input into.
Background technology
Existing known following oscillating circuit arrangement：It is not input into the case of the outside reference signal, internally
Generate and outputting oscillation signal, the reference signal is detected in the case of the reference signal from outside input, using PLL circuit control
Phase place processed and outputting oscillation signal.
Fig. 4 illustrates the circuit diagram of existing oscillating circuit arrangement 400.
Existing oscillating circuit arrangement 400 has power supply terminal 101, ground terminal 102, constant-current circuit 171,172, PMOS
Transistor 122, switch 150,151,154, inverter circuit 153, current control oscillator 113, frequency dividing circuit 114, phase place frequency
Rate comparator 111, charge pump circuit 112, pulse-detecting circuit 110 and filter circuit 174.Constant-current circuit 171 has PMOS
The current source 140 of transistor 120 and the 1st.Constant-current circuit 172 has PMOS transistor 121 and nmos pass transistor 131.Filter circuit
174 have capacitor 161.
Oscillating circuit arrangement as described above 400 has the work(that oscillator signal switching is carried out by following such action
Energy.
Under not externally to the 1st pattern of the input reference signal REF of REF terminals 103, pulse-detecting circuit 110 is exported
LOW, switch 150,154 is connected, and switch 151 disconnects.Because PMOS transistor 120,122 constitutes current mirror by switch 150
Circuit, therefore, respective leakage current I1 is proportional electric current to electric current I3.Additionally, the electricity of electric current I1 and the 1st current source 140
IB1 is equal for stream, as a result, current control oscillator 113 exports the output signal of the frequency proportional to electric current IB1 from CLK terminals
CLK.(determining without the state independently vibrated from outside input to reference signal REF of REF terminals 103 and relative to outside
Justice is self-operating state) under, switch 151 disconnects, therefore, constant-current circuit 172 does not affect electric current I1, electric current I3.Further, since
PMOS transistor 120,121 constitutes current mirroring circuit by switch 150, therefore, respective leakage current I1 and electric current I2 is into
The electric current of ratio.Now, switch 154 is connected, therefore, the grid of nmos pass transistor 131 is connected with drain electrode, the electricity based on electric current I2
Lotus is charged to capacitor 161.Afterwards, the grid in nmos pass transistor 131 is produced by electric current I2 and the spy of nmos pass transistor 131
Property determine grid voltage, the charging to electric capacity terminates, and electric current I2 flows through nmos pass transistor 131.
When reference signal REF is input into and becomes 2 pattern to REF terminals 103, the detection benchmark of pulse-detecting circuit 110
Signal REF simultaneously exports HIGH, disconnects switch 150,154, connects switch 151.Now, by phase frequency comparator 111,
Charge pump circuit 112, filter circuit 174, constant-current circuit 172, current control oscillator 113 and frequency dividing circuit 114 are adjusting
The PLL circuit of the phase place of reference signal REF starts action.As 131 pairs of electricity of nmos pass transistor that V/I conversion elements play a role
The output voltage VCP of lotus pump circuit 112 carries out V/I conversions, generates leakage current, there is provided to PMOS transistor 121.Due to PMOS it is brilliant
Body pipe 121,122 constitutes current mirroring circuit, and respective leakage current I2 is proportional electric current to electric current I3.Electricity under steady state
Stream I2 is controlled using the negative-feedback action of known PLL circuit so that the frequency of reference signal REF and frequency dividing circuit 114
Output be feedback signal FB_CLK frequency it is equal.Current control oscillator 113 exports proportional to electric current I2 from CLK terminals
Frequency output signal CLK.
Patent document 1 discloses that the skill that additional constant-current circuit in pll circuits and the electric capacity to filter circuit are charged
Art.
Patent document 1：No. 8174332 specifications of U.S. Patent No.
The content of the invention
But, in existing oscillating circuit arrangement 400, the charging due to carrying out capacitor 161 using constant current, so,
There is the problem of the charging interval prolongation proportional to capacitance/constant current value.Therefore, in the existing oscillating circuit arrangement of Fig. 4
In 400, when in the charging process of electric capacity as input reference signal REF and from the 1st pattern to 2 pattern switching, there is output
Signal CLK is less than the situation of desired frequency range, and the external equipment for receiving output signal CLK has the danger of misoperation
Property.
Fig. 5 be for illustrating existing oscillating circuit arrangement 400 in state change sequential chart.
Fig. 5 (a) is the time passage of the voltage VDD for putting on power supply terminal 101, and Fig. 5 (b) is charge pump circuit 112
The time passage of output voltage VCP, Fig. 5 (c) is the time passage of the frequency of reference signal REF for being input to REF terminals 103,
Fig. 5 (d) is the time passage of the frequency of output signal CLK obtained from CLK terminals.
As shown in Fig. 5 (a), in time t0 applied voltage VDD, the voltage VCP of Fig. 5 (b) due to the action of the 1st pattern,
Rise from 0V linear patterns.Afterwards, as shown in Fig. 5 (c), in time t1 input reference signal REF, oscillating circuit arrangement transfer
To the 2nd pattern.Because voltage VCP now is transition state, output signal CLK obtained from CLK terminals is with by transition state
Voltage VCP the rate-adaptive pacemaker that determines of value, as a result, as shown in Fig. 5 (d), the frequency of output signal CLK of CLK terminals is temporary transient
Drastically decline.Afterwards, by PLL actions, voltage VCP is made to increase, output signal CLK converges on the frequency with reference signal REF
Equal frequency.
The present invention in view of above-mentioned problem and complete, there is provided a kind of oscillating circuit arrangement, when the reference signal for detecting input
REF and from self-operating state be transferred to PLL actions when, the frequency variation of output signal CLK can be suppressed and successfully carried out same
Step.
In order to solve existing problem, the oscillating circuit arrangement of the present invention is constituted as follows.
Under self-operating state, negative-feedback is constituted by the V/I conversion elements and buffer circuit of one end of connection filter circuit
Circuit, can be from being that the equal frequency of frequency under self-operating state is opened with output signal CLK being just transferred to after PLL actions
Begin, the capacitor in filter circuit is hastily charged.
Invention effect
The oscillating circuit arrangement of the present invention can shorten the charging to the capacitor in the filter circuit under self-operating state
Time, therefore, it is possible to suppress the frequency variation of the output signal after just switching from self-operating state to PLL actions.
Description of the drawings
Fig. 1 is the circuit diagram of the structure of the oscillating circuit arrangement for illustrating present embodiment.
Fig. 2 is the sequential chart of the output signal in the oscillating circuit arrangement for illustrate present embodiment.
Fig. 3 is the circuit diagram of the other structures of the oscillating circuit arrangement for illustrating present embodiment.
Fig. 4 is the circuit diagram of the structure for illustrating existing oscillating circuit arrangement.
Fig. 5 is the sequential chart for illustrating the output signal in existing oscillating circuit arrangement.
Label declaration
100、300：Oscillating circuit arrangement；101：Power supply terminal；102：Ground terminal；103：REF terminals；104：CLK ends
Son；110：Pulse-detecting circuit；111：Phase frequency comparator；112：Charge pump circuit；113：Current control oscillator；114：
Frequency dividing circuit；140、141：Current source；151、152、154：Switch；153：Inverter circuit；171、172：Constant-current circuit；174：
Filter circuit；175：Buffer circuit.
Specific embodiment
Hereinafter, referring to the drawings, embodiments of the present invention are illustrated.
Fig. 1 is the circuit diagram of the oscillating circuit arrangement 100 of present embodiment.
The oscillating circuit arrangement 100 of present embodiment has power supply terminal 101, ground terminal 102, REF terminals 103, CLK
Terminal 104, constant-current circuit 171,172, PMOS transistor 122, switch 150 and 152, inverter circuit 153, current controlled oscillator
Device 113, frequency dividing circuit 114, phase frequency comparator 111, charge pump circuit 112, pulse-detecting circuit 110, filter circuit 174
And buffer circuit 175.Constant-current circuit 171 has the current source 140 of PMOS transistor 120 and the 1st.Constant-current circuit 172 has
PMOS transistor 121, switch 151 and nmos pass transistor 131.Filter circuit 174 has capacitor 161.Buffer circuit 175 has
There is the current source 141 of nmos pass transistor 130 and the 2nd.
Whether the detection of pulse detector 110 reference signal REF is input to REF terminals 103, output signal DET.Current control
Oscillator 113 exports the signal with the frequency of oscillation of the vibration current in proportion of input.Phase frequency comparator 111 is to benchmark
Signal REF is compared with feedback signal FB_CLK, exports its result.Charge pump circuit 112 is according to phase frequency comparator 111
Output signal, output voltage VCP.Buffer circuit 175 charges as soon as possible to capacitor 161, i.e., as early as possible by voltage VCP improve to
Desired value so as to stable.Phase frequency comparator 111, charge pump circuit 112, filter circuit 174, buffer circuit 175, perseverance
Current circuit 172, current control oscillator 113 and frequency dividing circuit 114 constitute the benchmark for being input to REF terminals 103 for adjustment
The PLL circuit of the phase place of signal REF.
Next, the connection to the oscillating circuit arrangement 100 of present embodiment is illustrated.
The input terminal of pulse-detecting circuit 110 is connected with REF terminals 103, the control of lead-out terminal and switch 150,152
The input terminal connection of terminal and inverter circuit 153.The lead-out terminal of inverter circuit 153 and the control end for switching 151
Son connection.Phase frequency compares back the 1st input terminal of device 111 and is connected with REF terminals 103, the 2nd input terminal and frequency dividing circuit
114 lead-out terminal connection, lead-out terminal is connected with the input terminal of charge pump circuit 112.Constitute the electric capacity of filter circuit 174
One end of device 161 is connected with the lead-out terminal of charge pump circuit 112, and the other end is connected with ground terminal 102.Nmos pass transistor
130 grid is connected with the drain electrode of nmos pass transistor 131 and the drain electrode of PMOS transistor 121, and drain electrode connects with power supply terminal 101
Connect, source electrode is connected with one end of switch 152 and one end of the 2nd current source 141.The other end and earth terminal of the 2nd current source 141
Son 102 connects.The other end of switch 152 is connected with the lead-out terminal of charge pump circuit 112.The grid of nmos pass transistor 131 with
The lead-out terminal connection of charge pump circuit 112, source electrode is connected with ground terminal 102.The source electrode and power end of PMOS transistor 120
Son 101 connects, and grid and drain electrode are connected with one end of switch 150 and one end of the 1st current source 140.1st current source 140
The other end be connected with ground terminal 102.The source electrode of PMOS transistor 121 is connected with power supply terminal 101, grid with switch 150
The other end connection.One end of switch 151 is connected with the grid of PMOS transistor 121, the leakage of the other end and PMOS transistor 121
Pole connects.The source electrode of PMOS transistor 122 is connected with power supply terminal 101, and grid is connected with the grid of PMOS transistor 121, leakage
Pole is connected with the input terminal of current control oscillator 113.The lead-out terminal of current control oscillator 113 and frequency dividing circuit 114
Input terminal connection.
Next, the action to the oscillating circuit arrangement 100 of present embodiment is illustrated.
First, reference signal REF is not input into the 1st pattern of the state of REF terminals 103 and is illustrated.
Under the 1st pattern, the output of pulse-detecting circuit 110 represents the signal DET of non-detection, and switch 150,152 is connected, opened
Close 151 to disconnect.Constant-current circuit 171 flows through the constant current IB1 of the first constant-current source 140.Due to PMOS transistor 122 and PMOS transistor
120 constitute current mirroring circuit, and respective leakage current I1 is proportional electric current to electric current I3.For example, PMOS transistor 120 with
122 size ratio is 1：In the case of 1, electric current I1 is equal with electric current I3.Current control oscillator 113 exports institute from CLK terminals
The electric current I3 of input, output signal CLK of i.e. proportional to electric current IB1 frequency.That is, the frequency of output signal CLK is by electric current
The current value of IB1 or the size ratio of PMOS transistor 120,122 are arbitrarily determined.
Further, since PMOS transistor 121 and PMOS transistor 120 constitute current mirroring circuit, respective leakage current I1 with
Electric current I2 is proportional electric current.For example, the size ratio in PMOS transistor 120 and 121 is 1：In the case of 1, electric current I1 with
Electric current I2 is equal.Due to electric current I2, the grid voltage VX of nmos pass transistor 130 rises, and nmos pass transistor 130 is connected.Also,
Capacitor 161 is charged using the source current of nmos pass transistor 130, voltage VCP rises.Thus, when grid receives electricity
When the nmos pass transistor 131 of pressure VCP is turned on, constant-current circuit 172 constitutes negative-feedback circuit with buffer circuit 175.Therefore, drastically draw
Rise the voltage VCP of the grid voltage as nmos pass transistor 131 so that the leakage current of nmos pass transistor 131 is equal with electric current I2.
Under steady state after, the constant current IB2 of the leakage current of the nmos pass transistor 130 of buffer circuit 175 and the second constant-current source 141
Equal, the second constant-current source 141 is operated as drop down element.
As described above, the oscillating circuit arrangement 100 of present embodiment has buffer circuit 175, therefore, under the 1st pattern
Capacitor 161 can be charged as soon as possible, i.e., as soon as possible voltage VCP can be improved to desired magnitude of voltage, accordingly, it is capable to
Rapidly make the frequency stable of output signal CLK.
Next, reference signal REF is input into the 2nd pattern of the state of REF terminals 103 illustrating.
When being changed into 2 pattern from the 1st pattern, the output of pulse-detecting circuit 110 represents the signal DET of detection, makes switch
150th, 152 disconnect, and by inverter circuit 153 switch 151 is connected.Due to switch 150 disconnect, therefore, constant-current circuit 171 from
Oscillating circuit arrangement 100 is separated.Because switch 151 disconnects, therefore, buffer circuit 175 is separated from filter circuit 174.Additionally, by
Connect in switch 151, therefore, PMOS transistor 121 and PMOS transistor 122 constitute current mirroring circuit, respective leakage current I2
It is proportional electric current to electric current I3.For example, the size ratio in PMOS transistor 121 and 122 is 1：In the case of 1, electric current I2
It is equal with electric current I3.
The nmos pass transistor 131 pairs played a role as V/I conversion elements is defeated according to the frequency of oscillation of reference signal REF
The output voltage VCP of the charge pump circuit 112 for going out carries out V/I conversions, generates leakage current, provides it to PMOS transistor 121.
Electric current I2 under steady state is controlled by the negative-feedback action of PLL circuit so that the frequency of reference signal REF and frequency dividing electricity
The output on road 114 is that the frequency of feedback signal FB_CLK is equal.More specifically, base is compared using phase frequency comparator 111
Calibration signal REF and feedback signal FB_CLK, from charge pump circuit 112 and the output voltage VCP of filter circuit 174, by NMOS crystal
Pipe 131 generates electric current I2.Therefore, output letter of the current control oscillator 113 from the output of CLK terminals based on the frequency of voltage VCP
Number CLK.Because switch 150 disconnects, so, constant-current circuit 171 does not affect electric current I2, electric current I3.
Fig. 2 be for illustrating the oscillating circuit arrangement 100 of present embodiment in state change sequential chart, using the figure
2 illustrating the effect of present embodiment.
Fig. 2 (a) is the time passage of the voltage VDD for putting on power supply terminal 101, and Fig. 2 (b) is charge pump circuit 112
The time passage of output voltage VCP, Fig. 2 (c) is the time passage being input into the frequency of reference signal REF of REF terminals 103,
Fig. 2 (d) is the time passage of the frequency of output signal CLK obtained from CLK terminals.
As shown in Fig. 2 (a), in time t0 applied voltage VDD, reference signal REF is not input to REF terminals 103, because
This, the action under the 1st pattern of oscillating circuit arrangement 100 is defeated by the negative-feedback action of constant-current circuit 172 and buffer circuit 175
Go out voltage VCP rapidly to rise from 0V.
Afterwards, as shown in Fig. 2 (c), in time t1 input reference signal REF, oscillating circuit arrangement 100 is transferred to the 2nd
Pattern.Now, because current control oscillator 113 carries out work by electric current corresponding with the voltage VCP for reaching steady state value
Make, so, output signal CLK of CLK terminals will not occurrence frequency drastically decline.Afterwards, by PLL actions, output signal CLK
Frequency converge on the frequency equal with reference signal REF.
As described above, the oscillating circuit arrangement 100 of present embodiment is configured to, it is negative anti-using being carried out by constant-current circuit 172
The output of the buffer circuit 175 of feedback action, improves the voltage of the capacitor 161 in filter circuit 174, therefore, shorten to electric capacity
In the charging interval of device 161, the output frequency after just switching from self-operating state to PLL actions can be suppressed to change.
Fig. 3 is the circuit diagram of the other structures of the oscillating circuit arrangement for illustrating present embodiment.
Oscillating circuit arrangement 300 is the structure with resistance 160 in filter circuit 174.
One end of resistance 160 is connected with the lead-out terminal of charge pump circuit 112, the other end and capacitor 161 and switch
152 other end connection.
So, phase compensation of the setting resistance 160 as PLL circuit in filter circuit 174 sometimes.In such filtering
In circuit 174, the lead-out terminal of buffer circuit 175 is connected between capacitor 161 and resistance 160 also by switch 152, by
This, obtains effect similar to the above.
As described above, the oscillating circuit arrangement of present embodiment compensates resistance 160 to improve frequency spy by insertion phase
Property, while the lead-out terminal of buffer circuit 175 is connected with capacitor 161, thus also can easily take into account shortening capatcitor 161
Charging interval.Thereby, it is possible to suppress the drastically decline of the output frequency after just switching from self-operating state to PLL actions, energy
Enough prevent the misoperation of external equipment being connected with CLK terminals.
In addition, for the capacitor 161, resistance is not limited to, even any circuit structure of connection other elements, also can
Obtain same effect.
Furthermore, it is to be understood that the oscillating circuit arrangement of the present invention can be applied to switch self-operating state and from outside input
Reference signal REF simultaneously makes the various electronic equipments of its work.For example, iting is desirable to be configured to make shaking for DC/DC converters from outside
Swing in the case that frequency freely changes, by the oscillating circuit arrangement using the present invention, smoothly oscillator signal can be realized
Transfer, there is provided the DC/DC converters of operating stably.
Claims (3)
1. a kind of oscillating circuit arrangement, it has：
Oscillator, it includes：The first constant-current circuit for flowing through the first constant current, the second constant-current circuit for flowing through the second constant current, flow through
The current mirroring circuit of the vibration electric current proportional to first constant current or second constant current and the oscillator signal of output
Frequency according to the current value of the vibration electric current of input the current control oscillator that changes；
PLL circuit, it includes：The phase place frequency that reference signal from outside input is compared with the phase place of the oscillator signal
Rate comparator, be input into the phase frequency comparator output charge pump circuit, be input into the output of the charge pump circuit
The frequency dividing circuit that filter circuit comprising capacitor and the output to the current control oscillator are divided, the PLL
Circuit controls second constant current using the output voltage of the charge pump circuit；And
Buffer circuit, its using the output voltage of second constant-current circuit as input voltage, via first switch to the filter
The capacitor of wave circuit is charged,
In the case where the first mode of the reference signal is not input into, the oscillating circuit arrangement output is based on the described of the oscillator
The oscillator signal of the first constant current, in the case where the second mode of the reference signal is input into, the oscillating circuit arrangement output is based on institute
The oscillator signal of second constant current of oscillator is stated,
Characterized in that,
In the first mode, the first switch is connected, thus, the capacitor by the buffer circuit output voltage
It is charged,
In the second mode, the first switch disconnects.
2. oscillating circuit arrangement according to claim 1, it is characterised in that
First constant-current circuit has the first PMOS transistor and constant flow element being connected in series,
Second constant-current circuit has the second PMOS transistor and the first nmos pass transistor being connected in series,
The grid of first PMOS transistor is connected via second switch with second PMOS transistor, a NMOS
The grid of transistor is connected with the filter circuit,
In the first mode, the second switch is connected, and thus, second constant-current circuit is generated and first constant current
The electric current of the current in proportion of circuit,
In the second mode, the second switch disconnects, and thus, generates and is shaken with described based on the frequency of the reference signal
Swing the electric current of the phase difference of the frequency of signal.
3. oscillating circuit arrangement according to claim 2, it is characterised in that
The oscillating circuit arrangement has a case that detection have input the pulse-detecting circuit of the reference signal,
The pulse-detecting circuit controls the first switch and the second switch using output signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015-221430 | 2015-11-11 | ||
| JP2015221430A JP6559548B2 (en) | 2015-11-11 | 2015-11-11 | Oscillator circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106685416A true CN106685416A (en) | 2017-05-17 |
Family
ID=58664324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610959068.1A Withdrawn CN106685416A (en) | 2015-11-11 | 2016-11-03 | Oscillation circuit device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10056910B2 (en) |
| JP (1) | JP6559548B2 (en) |
| KR (1) | KR20170055422A (en) |
| CN (1) | CN106685416A (en) |
| TW (1) | TWI678072B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101361271A (en) * | 2006-10-12 | 2009-02-04 | 松下电器产业株式会社 | Pll circuit |
| US20100026406A1 (en) * | 2008-07-31 | 2010-02-04 | Sony Corporation | Phase-locked loop circuit, recording-and-reproducing apparatus, and electronic appratus |
| US8446139B2 (en) * | 2009-10-02 | 2013-05-21 | Sony Corporation | Current source, electronic apparatus, and integrated circuit |
| CN103199857A (en) * | 2012-01-06 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Current-controlled oscillator (CCO) based PLL |
| CN103731099A (en) * | 2012-10-11 | 2014-04-16 | 联发科技（新加坡）私人有限公司 | Voltage-to-current converter and voltage controlled oscillator |
| JP2015167346A (en) * | 2014-02-17 | 2015-09-24 | 凸版印刷株式会社 | PLL circuit |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06197014A (en) * | 1992-12-25 | 1994-07-15 | Mitsubishi Electric Corp | Phase locked loop circuit |
| JPH07170178A (en) * | 1993-09-10 | 1995-07-04 | Sun Microsyst Inc | Pll damping circuit |
| JP3356136B2 (en) * | 1999-10-19 | 2002-12-09 | 日本電気株式会社 | PLL circuit |
| JP2001156759A (en) * | 1999-11-24 | 2001-06-08 | Hitachi Ltd | Serial transmission reception circuit |
| US6300838B1 (en) * | 1999-12-22 | 2001-10-09 | International Business Machines Corporation | Method and apparatus for derivative controlled phase locked loop systems |
| US7019569B2 (en) * | 2004-07-09 | 2006-03-28 | Faraday Technology Corp. | Method of implementing multi-transfer curve phase lock loop |
| US7636019B1 (en) * | 2005-06-07 | 2009-12-22 | Cypress Semiconductor Corporation | Phase lock loop pre-charging system and method |
| US8143957B2 (en) * | 2006-01-11 | 2012-03-27 | Qualcomm, Incorporated | Current-mode gain-splitting dual-path VCO |
| JP2008042339A (en) * | 2006-08-02 | 2008-02-21 | Renesas Technology Corp | Semiconductor device |
| JP2008072166A (en) * | 2006-09-12 | 2008-03-27 | Sony Corp | Phase synchronization circuit and electronic equipment |
| JP2008072272A (en) * | 2006-09-13 | 2008-03-27 | Nec Electronics Corp | Pll circuit |
| JP2008278016A (en) * | 2007-04-26 | 2008-11-13 | Nec Electronics Corp | Pll circuit and frequency setting circuit using same |
| JP4991385B2 (en) * | 2007-05-09 | 2012-08-01 | セイコーＮｐｃ株式会社 | PLL circuit |
| JP2010252094A (en) * | 2009-04-16 | 2010-11-04 | Renesas Electronics Corp | Pll circuit |
| US8169265B2 (en) * | 2009-04-29 | 2012-05-01 | Mediatek Inc. | Phase lock loop circuits |
| CN101944910B (en) * | 2009-07-07 | 2017-03-22 | 晨星软件研发(深圳)有限公司 | Double-phase-locked loop circuit and control method thereof |
| US9374099B2 (en) * | 2014-03-25 | 2016-06-21 | Mediatek Inc. | Oscillating signal generator, phase-lock loop circuit using the oscillating signal generator and control method of the oscillating signal generator |
-
2015
- 2015-11-11 JP JP2015221430A patent/JP6559548B2/en active Active
-
2016
- 2016-10-26 TW TW105134463A patent/TWI678072B/en not_active IP Right Cessation
- 2016-11-03 CN CN201610959068.1A patent/CN106685416A/en not_active Withdrawn
- 2016-11-04 KR KR1020160146507A patent/KR20170055422A/en unknown
- 2016-11-09 US US15/347,357 patent/US10056910B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101361271A (en) * | 2006-10-12 | 2009-02-04 | 松下电器产业株式会社 | Pll circuit |
| US20100026406A1 (en) * | 2008-07-31 | 2010-02-04 | Sony Corporation | Phase-locked loop circuit, recording-and-reproducing apparatus, and electronic appratus |
| US8446139B2 (en) * | 2009-10-02 | 2013-05-21 | Sony Corporation | Current source, electronic apparatus, and integrated circuit |
| CN103199857A (en) * | 2012-01-06 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Current-controlled oscillator (CCO) based PLL |
| CN103731099A (en) * | 2012-10-11 | 2014-04-16 | 联发科技（新加坡）私人有限公司 | Voltage-to-current converter and voltage controlled oscillator |
| JP2015167346A (en) * | 2014-02-17 | 2015-09-24 | 凸版印刷株式会社 | PLL circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI678072B (en) | 2019-11-21 |
| US20170134029A1 (en) | 2017-05-11 |
| JP6559548B2 (en) | 2019-08-14 |
| JP2017092738A (en) | 2017-05-25 |
| US10056910B2 (en) | 2018-08-21 |
| TW201725866A (en) | 2017-07-16 |
| KR20170055422A (en) | 2017-05-19 |
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| CB02 | Change of applicant information |
Address after: Chiba County, Japan Applicant after: EPPs Lingke Co. Ltd. Address before: Chiba County, Japan Applicant before: SEIKO INSTR INC |
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| SE01 | Entry into force of request for substantive examination | ||
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| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20170517 |