JP2015167346A - PLL circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit capable of suppressing increase in phase noise and power consumption with a low voltage power supply, and further capable of suppressing variation in the PLL loop bandwidth, in a PLL circuit where at least a phase frequency comparison circuit B, a charge pump B, a lowpass filter B, a voltage controlled oscillation circuit B, and a frequency divider B are connected in this order, and the charge pump B and voltage controlled oscillation circuit B have input terminals for controlling the reference current sources B, respectively.SOLUTION: A PLL circuit has a replica PLL for controlling a reference current source B, the replica PLL has at least a lock-up detection circuit connected with a phase frequency comparison circuit A, a charge pump A, a lowpass filter A, a voltage controlled oscillation circuit A, and a frequency divider A, in this order, and detecting lock-up of the replica PLL, and a switch for inputting an input signal of the voltage controlled oscillation circuit A to an input terminal for controlling the reference current source B, at the time of lock-up detected by the lock-up detection circuit.

Description

  The present invention relates to a low voltage PLL circuit.

Conventionally, a PLL (phase synchronization) circuit has been widely used, and its basic circuit configuration is shown in FIG.
The PLL circuit 100 generally includes a phase frequency comparison circuit (PFD) 22, a charge pump (CP) 200, a low-pass filter (LF) 30, and a voltage controlled oscillation circuit (VCO) 40. The reference signal REF from the outside and basically the feedback signal FB from the voltage controlled oscillation circuit (VCO) 40 are input to the phase frequency comparison circuit 22, and the phase difference signal is output from the phase frequency comparison circuit 22. Is connected to the low pass filter 30 via the charge pump 200. The low-pass filter 30 removes unnecessary components of the phase difference signal, converts it to a DC voltage according to its output, and drives and inputs it to the voltage controlled oscillation circuit 40. In the oscillation circuit 40, a signal whose frequency is changed by a DC voltage is output, which becomes an output of the PLL circuit 100. In the basic circuit, this output is input to the phase frequency comparison circuit 22 as a feedback signal FB. A stable signal from the reference voltage / current source circuit 60 is input to the reference signal terminal IREF. When an input signal is input to the PLL circuit 100, the voltage-controlled oscillation circuit self-runs and oscillates. At the same time, the phase correction operation is repeated and finally locked up so that the PLL circuit 100 has a stable output. The period until the output is stabilized is called a lockup time. This PLL circuit is applied in various ways such as a synthesizer, a demodulator circuit for data transmission, an FM demodulator circuit, or a motor rotation speed control. Further, there is a general usage method in which feedback between the output of the PLL circuit 100 and the feedback signal FB is fed back via the frequency divider circuit 50 and input to the phase frequency comparison circuit 22 to obtain a frequency multiplied output signal. is there.

  The charge pump (CP) 200 and the voltage controlled oscillation circuit (VCO) 40 are input to the respective reference current sources from the reference voltage / current source circuit 60 in order to obtain a stable constant current source. A band gap reference or the like is used for the reference voltage / current source circuit. The reference current source of the VCO oscillator is a current source for stable free-running oscillation, and becomes a factor for stabilizing the lock-up operation by feedback. The oscillation of the VCO is controlled by the reference current source and the output of the low pass filter.

  Known documents are shown below.

Japanese Patent Laid-Open No. 10-004350 Japanese Patent Laying-Open No. 2005-073124

  In the semiconductor integrated circuit, development of high integration is constantly advanced. However, in the deep submicron process, it is necessary to configure the circuit only with a low-voltage power supply and a low-breakdown voltage MOS device as compared with the conventional one. When a PLL circuit is configured with only a low-voltage power supply and a low-breakdown-voltage MOS device, the maximum performance is derived by optimizing circuit constants under the limitation of the power supply voltage range and device characteristics, and the performance limit is set. In addition, the reference voltage / current circuit represented by the bandgap reference as described above is difficult to control current variations due to variations in low voltage power supply and low voltage MOS devices. The oscillation frequency variation of the oscillator (VCO) makes it difficult to reduce the phase noise of the PLL circuit.

Problem 1
Designing with only a low voltage MOS device has the effect of lowering the power consumption because the power supply voltage is lowered, while the variation in oscillation circuit due to the variation in the static current characteristics and the voltage dynamic range of the low voltage MOS transistor. To compensate for the problem, it is necessary to increase the control sensitivity. For this reason, the phase modulation due to the input voltage noise increases the phase noise of the PLL circuit, which is a problem. When the required characteristics are indispensable, the problem is avoided by changing to a high voltage MOS device and increasing the voltage.

Problem 2
Regarding the charge pump circuit of the element circuit constituting the PLL circuit, when the voltage dynamic range is narrowed, the effective control voltage range is similarly narrowed. In order to compensate for the delay variable range required at this time, including environmental conditions and manufacturing variations, it is necessary to increase the variable range of the voltage range per unit by increasing the control sensitivity. It was the cause of the increase. When the control sensitivity cannot be increased, a correction circuit has been added so that the optimum element can be selected within the element variation range assumed by the trimming technique. This complicates the circuit and makes design verification complicated.

Problem 3
For the reference voltage / current circuit of the PLL circuit, the layout size increases as a trade-off by increasing the voltage / current accuracy in order to reduce phase noise, and oscillation frequency variation and phase noise characteristics under low power supply voltage conditions It was difficult to suppress.

  The present invention solves such problems, and an object of the present invention is to provide a PLL circuit that can suppress an increase in phase noise and power consumption with a low-voltage power supply and can further suppress variations in PLL loop bandwidth.

  When the frequency control current is 0 (VCO free-running oscillation state), the PLL circuit of the present invention is not a reference voltage / current circuit typified by a bandgap reference circuit (BGR), but VCO free-running oscillation. In addition, the current value generated by an independent PLL circuit (hereinafter referred to as a replica PLL) is referred to and the main PLL is oscillated to reduce oscillation range variation and phase noise, thereby solving the problem.

That is, the invention of claim 1 of the present invention is
At least the phase frequency comparison circuit B, the charge pump B, the low-pass filter B, the voltage controlled oscillation circuit B, and the frequency divider B are connected in this order, and the charge pump B and the voltage controlled oscillation circuit B In a PLL circuit having an input terminal for controlling the reference current source B,
A replica PLL for controlling the reference current source B;
In the replica PLL, at least a phase frequency comparison circuit A, a charge pump A, a low-pass filter A, a voltage control oscillation circuit A, and a frequency divider A are connected in this order. In the same configuration as the circuit B, the frequency divider A has a frequency division number different from that of the frequency divider B.
The charge pump A, the voltage controlled oscillation circuit A, and the charge pump B have their reference current source A and reference current source B controlled by the reference voltage / current source circuit,
Further, the replica PLL has a lock-up detection circuit that detects a lock-up state of the replica PLL. When the lock-up is detected by the lock-up detection circuit, an input signal of the voltage-controlled oscillation circuit A is supplied to the voltage-controlled oscillation circuit B. A PLL circuit comprising a switch for inputting to an input terminal for controlling the reference current source B.

The invention of claim 2 of the present invention
At least the phase frequency comparison circuit B, the charge pump B, the low-pass filter B, the voltage controlled oscillation circuit B, and the frequency divider B are connected in this order, and the charge pump B and the voltage controlled oscillation circuit B In a PLL circuit having an input terminal for controlling the reference current source B,
A replica PLL for controlling the reference current source B;
In the replica PLL, at least a phase frequency comparison circuit A, a charge pump A, a low-pass filter A, a voltage control oscillation circuit A, and a frequency divider A are connected in this order. In the same configuration as the circuit B, the frequency divider A has a frequency division number different from that of the frequency divider B. The charge pump A and the voltage controlled oscillation circuit A have their respective reference current sources A set by the reference voltage / current source circuit. Further, the replica PLL has a lock-up detection circuit for detecting the lock-up of the replica PLL, and the input signal of the voltage-controlled oscillation circuit A is used as a reference current source B at the time of lock-up detected by the lock-up detection circuit. This is a PLL circuit characterized by having a switch that inputs to an input terminal that controls.

  Since the present invention is configured as described above, the free-running oscillation frequency variation can be made extremely small as compared with existing circuits. Even if it is a low voltage source, by obtaining a free-running oscillation frequency with almost no variation, the VCO control sensitivity can be designed to be smaller than that of the existing circuit. Filter (CR-Filter) and charge pump current noise Can be reduced in the amount of phase modulation (phase noise) caused by the VCO.

1 is a circuit diagram showing an embodiment of a PLL circuit of the present invention. It is a specific example of the VCO of the main PLL and replica PLL of the embodiment example of the PLL circuit of the present invention. It is explanatory drawing which showed the outline of the lockup sequence of the embodiment of the PLL circuit of this invention. It is explanatory drawing which showed typically the characteristic of the input voltage and output frequency of the voltage control oscillation circuit of a PLL circuit. It is a circuit diagram of the basic structural example of the conventional PLL circuit.

  Hereinafter, modes for carrying out the present invention will be described.

FIG. 1 is a circuit diagram showing an embodiment of a PLL circuit according to the present invention. The PLL circuit 1 according to this embodiment includes a main PLL and a replica PLL. In the main PLL 101, a phase frequency comparison circuit B21, a charge pump B201, a low-pass filter B31, a voltage controlled oscillation circuit B41, and a frequency divider B51 are connected in this order. The charge pump B201 and the voltage controlled oscillation circuit B41 are An input terminal IREFB for controlling each reference current source B is provided. The replica PLL 10 controls the reference current source B. The replica PLL 10 includes at least a phase frequency comparison circuit A2, a charge pump A20, a low-pass filter A3, a voltage-controlled oscillation circuit A4, and a frequency divider. A5 is connected in this order. The voltage control circuit A4 has the same configuration as the voltage control circuit B41, the frequency divider A5 has a frequency division number different from that of the frequency divider B51, and the charge pump A20 and the voltage control oscillation circuit A4 are a reference voltage / current source circuit. Each reference current source A is controlled by 6. Further, the replica PLL 10 includes a lock-up detection circuit 7 that detects a lock-up state of the replica PLL 10, and an input signal of the voltage controlled oscillation circuit A 4 is used as a reference current source at the time of lock-up detected by the lock-up detection circuit 7. A switch 8 for inputting to an input terminal IREFA for controlling B is provided.

With such a configuration, the PLL of the present embodiment performs the following operation.
FIG. 3 is an explanatory diagram showing an outline of the lockup sequence of the present embodiment.
When the input signal CLKIN is supplied to the PLL circuit, first, the voltage controlled oscillation circuit A4 of the replica PLL 10 performs free-running oscillation with the reference current source A controlled by the reference voltage / current source circuit 6 (replica VCO). Is supplied with the offset current Ioffset 1. The range of the Replica PLL locking shown in FIGS. At the same time, the reference current source A of the charge pump A20 is also activated, and the phase correction operation is repeated toward the lock-up of the replica PLL (VCO control current Ioffset2 is supplied. FIGS. 3B and 3C, Replica. PLL locking range). When the lockup occurs, the lockup detection circuit 7 detects a lockup state (activation of the detection signal LD of the detection circuit, the rising portion in FIG. 3A), and the switch 8 is switched, and the voltage controlled oscillation circuit The input signal A4 is input to the input terminal IREFB that controls the reference current source B of the main PLL, and the control current Ioffset2 is supplied. The voltage control oscillation circuit VCO of the main PLL and the replica PLL has the same configuration, and the characteristics match. Similar to the replica PLL, the reference current controlled by the reference voltage / current source circuit 6 also controls the VCO of the main PLL.
Accordingly, since the current of the reference current source B is controlled to be the current at the time of lock-up of the replica PLL, the free-running oscillation frequency of the main PLL becomes the lock-up frequency of the replica PLL. Then, simultaneously with the self-running oscillation of the main PLL, the phase correction operation is repeatedly locked up based on this reference current source B (supply of VCO control currents Ioffset1, Ioffset2, Icont, FIGS. 3B, 3C, Main PLL locking range).

FIG. 2 is a specific example of the VCO of the main PLL and replica PLL of the present embodiment. As the VCO, both use a ring oscillation circuit, and the VCO input voltages VC (1), VC (2) and (the control current to the VCO are Icont in the main PLL and Ioffset2 in the replica PLL through the buffer. ), And the reference current source (offset currents Ioffset2 and Ioffset1 in the main PLL and Ioffset1 in the replica PLL) are connected to a current source that controls the delay time of the ring oscillator. The reference current source of the replica PLL is controlled by a reference voltage / current source circuit using a band gap reference, and supplies an offset current Ioffset1 to the ring oscillation circuit.
The voltage control oscillation circuit VCO of the main PLL and the replica PLL has the same configuration, and the reference current Ioffset1 controlled by the reference voltage / current source circuit 6 controls the VCO of the main PLL as well as the replica PLL. .

  The input voltage VC (1) of the VCO is input to the analog switch via the buffer. The analog switch is formed by connecting a P-channel MOS transistor and an N-channel MOS transistor in parallel. In addition, connection and disconnection are performed by a detection signal LD output from the lockup detection circuit. The output of the switch is connected to the reference current source of the main PLL. Therefore, after the replica PLL is locked up, the VCO input signal VC (1) of the replica PLL is input to the reference current source of the main PLL via the buffer, and free-runs based on the offset currents Ioffset2 and Ioffset1 thereby Oscillation is performed, and a control current Iton by the input signal VC (2) of the main PLL is also applied, and the phase correction operation is repeated to lock up the main PLL.

  Note that the frequency division number of the replica PLL frequency divider is different from that of the main PLL frequency divider. This is to ensure a frequency variable range (control gain) of a certain level or more for lock-up of the main PLL by setting the self-running oscillation of the main PLL to an oscillation frequency different from the lock-up frequency. In this embodiment, as shown in FIG. 1, the main PLL is N times and the replica PLL is N-1 times.

  Further, from such an operation, a design in which the reference current controlled by the reference voltage / current source circuit is omitted is also possible.

  As described above, the main PLL is an input signal of the voltage controlled oscillation circuit when the replica PLL is locked up, and the reference current source is controlled. Therefore, the free-running oscillation frequency can be made constant, and the following effects can be obtained. .

  FIG. 4 is a schematic diagram showing the characteristics of the input voltage and output frequency of the voltage controlled oscillation circuit. FIG. 4 (a) is an example of a conventional circuit, and FIG. 4 (b) is a diagram of the circuit of the present invention. It is an example.

  As shown in FIG. 4A, in the conventional ring oscillation VCO, in the free-running oscillation frequency range, the designed VCO free-running oscillation (Target freq. VCO free-running oscillation) varies due to manufacturing and other factors. Will occur. Also, in response to this variation, if the frequency is higher than the design free-running oscillation frequency (Target freq. VCO free-running oscillation shown in the figure), the VCO gain is large and the slope in the figure is large, which is smaller than the design free-running oscillation. In this case, the inclination becomes smaller. In this state, when locking up to the designed frequency, since the difference in the slope is large, the variation in the input voltage Vcont of the VCO at the designed frequency (Target freq. PLL N multiplication shown in the figure) also increases.

  The PLL of the present invention has characteristics as illustrated in FIG. Since the VPL input signal when the replica PLL is locked up is input to the reference current source, the main PLL performs a control operation so that the lock-up frequency of the replica PLL becomes the free-running oscillation frequency of the main PLL (in the figure). Target freq. Replica PLL N-1 multiplication). Therefore, variations in free-running oscillation frequency of the main PLL are reduced. As a result, the variation in the gain of the VCO is reduced, and the variation in the input voltage Vcont of the VCO at the designed frequency after the lock-up of the main PLL (Target freq. Main PLL N multiplication shown in the figure) is also reduced.

  Since such an operational effect is obtained, the free-running oscillation frequency variation can be made extremely small as compared with the existing circuit. Even if it is a low voltage source, by obtaining a free-running oscillation frequency with almost no variation, the VCO control sensitivity can be designed to be smaller than that of the existing circuit. Filter (CR-Filter) and charge pump current noise Can be reduced in the amount of phase modulation (phase noise) caused by the VCO.

  The operation and effect of controlling the reference current source of the main PLL with the input signal of the voltage controlled oscillation circuit when the replica PLL is locked up have been described above. In the present embodiment, the reference current source of the charge pump is further controlled by an input signal of the voltage controlled oscillation circuit when the replica PLL is locked up instead of a conventional band gap reference or the like.

In the PLL having such a configuration, the voltage controlled oscillation circuit and the charge pump operate as follows. As shown in FIG. 4 (b) in the voltage oscillation circuit, after the replica PLL is locked up, the control sensitivity of the ring oscillation VCO is the gm value of the element forming each delay. The control sensitivity increases when the gm value is large, and the sensitivity decreases when the gm value is small. For the same oscillation frequency, the current flowing through the element decreases when the gm value is large, and the current increases when the gm value is small. On the other hand, the charge pump output current is the same as the current flowing through each element of the VCO because the reference current source is the input current source at the time of lock-up of the replica PLL like the VCO. The output current of the charge pump is proportional to the reference current (constant current source). Therefore, when the VCO sensitivity is high, the current is small and the output current of the charge pump is small. When the VCO sensitivity is low, the current increases and the output current of the charge pump increases. At this time, in the PLL open loop transfer function, the phase comparison gain Kp when the current output type charge pump is used and the gain Kv of the voltage controlled oscillation circuit have a simple product relationship. Is canceled by the phase comparison gain Kp. For this reason, the variation width of the loop bandwidth of the PLL transfer function can be reduced. Lock-up time can also be increased.

  In this way, the variation of the PLL transfer function is suppressed by controlling the charge pump reference current source with the input signal of the voltage controlled oscillation circuit when the replica PLL is locked up instead of the conventional bandgap reference. And lock up. For this reason, the variation width of the loop bandwidth of the PLL transfer function can be reduced and the lock-up can be performed at high speed.

DESCRIPTION OF SYMBOLS 1 ... PLL circuit 10 ... Replica PLL circuit 101 ... Main PLL circuit 2 ... Phase frequency comparison circuit 20 ... Charge pump 3 ... Low pass filter 4 ... Voltage controlled oscillation Circuit 5... Frequency divider 6... Reference voltage / current source circuit 7... Lockup detection circuit 8. ··· Low-pass filter 41 ··· Voltage controlled oscillation circuit 51 ··· Frequency divider 22 ··· Phase frequency comparison circuit 200 · · · Charge pump 30 · · · Low-pass filter 40 · · · Voltage controlled oscillation circuit 50... Divider 60... Reference voltage / current source circuit

Claims (2)

At least the phase frequency comparison circuit B, the charge pump B, the low-pass filter B, the voltage controlled oscillation circuit B, and the frequency divider B are connected in this order, and the charge pump B and the voltage controlled oscillation circuit B In a PLL circuit having an input terminal for controlling the reference current source B,
A replica PLL for controlling the reference current source B;
In the replica PLL, at least a phase frequency comparison circuit A, a charge pump A, a low-pass filter A, a voltage control oscillation circuit A, and a frequency divider A are connected in this order. In the same configuration as the circuit B, the frequency divider A has a frequency division number different from that of the frequency divider B.
The charge pump A, the voltage controlled oscillation circuit A, and the charge pump B have their reference current source A and reference current source B controlled by the reference voltage / current source circuit,
Further, the replica PLL has a lock-up detection circuit that detects a lock-up state of the replica PLL. When the lock-up is detected by the lock-up detection circuit, an input signal of the voltage-controlled oscillation circuit A is supplied to the voltage-controlled oscillation circuit B. A PLL circuit comprising a switch for inputting to an input terminal for controlling the reference current source B. At least the phase frequency comparison circuit B, the charge pump B, the low-pass filter B, the voltage controlled oscillation circuit B, and the frequency divider B are connected in this order, and the charge pump B and the voltage controlled oscillation circuit B In a PLL circuit having an input terminal for controlling the reference current source B,
A replica PLL for controlling the reference current source B;
In the replica PLL, at least a phase frequency comparison circuit A, a charge pump A, a low-pass filter A, a voltage control oscillation circuit A, and a frequency divider A are connected in this order. In the same configuration as the circuit B, the frequency divider A has a frequency division number different from that of the frequency divider B. The charge pump A and the voltage controlled oscillation circuit A have their respective reference current sources A set by the reference voltage / current source circuit. Further, the replica PLL has a lock-up detection circuit that detects the lock-up state of the replica PLL. When the lock-up is detected by the lock-up detection circuit, the input signal of the voltage-controlled oscillation circuit A is used as a reference current source. A PLL circuit comprising a switch for inputting to an input terminal for controlling B.

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