TW201725866A - Oscillation circuit device - Google Patents

Abstract

To provide an oscillation circuit device capable of when detecting an input reference signal and making a transition from a self-running state to a PLL operation, suppressing a fluctuation in the frequency of an output signal CLK to thereby obtain a smoothly-synchronized and stable output signal CLK. There is provided an oscillation circuit device which is adapted to configure a negative feedback circuit by a V/I conversion element to which one end of a filter circuit is connected, and a buffer circuit in a self-running state, and has a configuration which enables a capacitance in the filter circuit to be charged rapidly in such a manner that an output signal CLK can be started from a frequency equal to that in the self-running state immediately after a transition to a PLL operation.

Description

Oscillating circuit device

The present invention relates to an oscillation circuit device including a phase synchronization circuit (phase locked loop circuit, hereinafter referred to as a PLL circuit) that performs feedback in addition to the input reference signal. In addition to control, the phase is also controlled.

Conventionally, there has been known an oscillation circuit device that generates an output oscillation signal internally when a reference signal from the outside is not input, and detects the reference signal when a reference signal is input from the outside, and The PLL circuit controls the phase to output an oscillating signal.

A circuit diagram of a conventional oscillation circuit device 400 is shown in FIG. The conventional oscillation circuit device 400 includes a power supply terminal 101, a ground terminal 102, a constant current circuit 171, a constant current circuit 172, a P channel metal oxide semiconductor (PMOS) transistor 122, and a switch. 150, switch 151, switch 154, inverter circuit 153, current control oscillator 113, frequency dividing circuit 114, phase frequency comparator 111, charge pump circuit 112, pulse detection Circuit 110 and filter circuit 174. The constant current circuit 171 includes a PMOS transistor 120 and a first current source 140. The constant current circuit 172 includes a PMOS transistor 121 and an N-channel metal oxide semiconductor (NMOS) transistor 131. The filter circuit 174 is provided with a capacitor 161.

The oscillation circuit device 400 as described above has a function of switching the oscillation signal in the following operation.

In the first mode in which the reference signal REF is not input from the outside to the REF terminal 103, the pulse wave detecting circuit 110 outputs LOW, the switch 150 and the switch 154 are turned on, and the switch 151 is turned off. The PMOS transistor 120 and the PMOS transistor 122 form a current mirror circuit via the switch 150. Therefore, each of the drain current I1 and the current I3 is a current proportional to the current. Further, the current I1 is equal to the current IB1 of the first current source 140, and as a result, the current control oscillator 113 outputs an output signal CLK of a frequency proportional to the current IB1 from the CLK terminal. In the state in which there is no reference signal REF input from the outside to the REF terminal 103 and independent of the external oscillation (defined as the free oscillation state), since the switch 151 is turned off, the constant current circuit 172 does not cause the current I1 and the current I3. influences. Further, since the PMOS transistor 120 and the PMOS transistor 121 constitute a current mirror circuit via the switch 150, each of the drain current I1 and the current I2 is a current proportional to the current. At this time, since the switch 154 is turned on, the gate of the NMOS transistor 131 is connected to the drain, and the electric charge based on the current I2 is charged to the capacitor 161. Subsequently, at the gate of the NMOS transistor 131, a gate voltage determined by the characteristics of the current I2 and the NMOS transistor 131 is generated, the charging of the capacitor is ended, and the current I2 flows to the NMOS transistor 131.

When the reference signal REF is input to the REF terminal 103 and the second mode is entered, the pulse wave detecting circuit 110 detects the reference signal REF and outputs HIGH, turns off the switch 150 and the switch 154, and turns on the switch 151. At this time, the phase frequency comparator 111, the charge pump circuit 112, the filter circuit 174, the constant current circuit 172, the current control oscillator 113, and the frequency dividing circuit 114, the PLL circuit for adjusting the phase of the reference signal REF starts operating. The NMOS transistor 131 functioning as a V/I conversion element V/I converts the output voltage VCP of the charge pump circuit 112 to generate a drain current, and supplies it to the PMOS transistor 121. Since the PMOS transistor 121 and the PMOS transistor 122 constitute a current mirror circuit, the respective drain current I2 is a current proportional to the current I3. The current I2 in the constant state is controlled by the negative feedback action of the commonly known PLL circuit to make the frequency of the reference signal REF equal to the frequency of the output of the frequency dividing circuit 114, that is, the feedback signal FB_CLK. The current control oscillator 113 outputs an output signal CLK of a frequency proportional to the current I2 from the CLK terminal.

Patent Document 1 shows a technique in which a constant current circuit is added to a PLL circuit to charge a capacitor of the filter circuit. Prior art literature

Patent Document 1: US Patent No. 8174332

[Problems to be Solved by the Invention] However, the conventional oscillation circuit device 400 has a problem that since the charging of the capacitor 161 is performed by a constant current, the charging time proportional to the capacitance value/constant current value becomes long. . Therefore, in the conventional oscillation circuit device 400 of FIG. 4, when the reference signal REF is input during the charging of the capacitor and the mode is switched from the first mode to the second mode, the output signal CLK may sometimes be lower than the desired frequency range. There is a danger that an external machine receiving the signal may malfunction.

5(a) to 5(d) are timing charts for explaining a state change in the conventional oscillation circuit device 400. 5(a) is a time transition of the voltage VDD applied to the power supply terminal 101, FIG. 5(b) is a time transition of the output voltage VCP of the charge pump circuit 112, and FIG. 5(c) is a reference signal input to the REF terminal 103. The time lapse of the frequency of REF, FIG. 5(d) is the time lapse of the frequency of the output signal CLK obtained from the CLK terminal.

As shown in FIG. 5(a), when the voltage VDD is applied at time t0, the voltage VCP of FIG. 5(b) rises linearly from 0 V due to the operation of the first mode. Subsequently, as shown in FIG. 5(c), when the reference signal REF is input at time t1, the oscillation circuit device shifts to the second mode. At this time, the voltage VCP is in a transient state, so the output signal CLK obtained from the CLK terminal is output at a frequency determined by the value of the transient state voltage VCP, and as a result, as seen in FIG. 5(d), the output signal of the CLK terminal The frequency of CLK temporarily drops sharply. Subsequently, the voltage VCP rises due to the PLL operation, and the output signal CLK converges to a frequency equal to the frequency of the reference signal REF.

The present invention has been made in view of the above problems, and provides an oscillation circuit device capable of suppressing a frequency fluctuation of an output signal CLK and smoothly synchronizing when a change from a free oscillation state to a PLL operation is detected when the input reference signal REF is detected. [Means for solving the problem]

In order to solve the conventional problems, the oscillation circuit device of the present invention has the following configuration. The present invention adopts a configuration in which, in a free-running state, a V/I conversion element connected to one end of the filter circuit and a buffer circuit form a negative feedback circuit, so that the capacitance in the filter circuit can be rapidly charged. So that after the transition to the PLL action, the output signal CLK can start from a frequency equal to the frequency in the free-running state. [Effects of the Invention]

Since the oscillation circuit device of the present invention can shorten the charging time of the capacitance in the filter circuit in the free oscillation state, it is possible to suppress the frequency variation of the output signal immediately after switching from the free oscillation state to the PLL operation.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram of an oscillation circuit device 100 of the present embodiment. The oscillation circuit device 100 of the present embodiment includes a power supply terminal 101, a ground terminal 102, a REF terminal 103, a CLK terminal 104, a constant current circuit 171, a constant current circuit 172, a PMOS transistor 122, a switch 150 and a switch 152, and an inverter circuit. 153. A current control oscillator 113, a frequency dividing circuit 114, a phase frequency comparator 111, a charge pump circuit 112, a pulse wave detecting circuit 110, a filter circuit 174, and a buffer circuit 175. The constant current circuit 171 includes a PMOS transistor 120 and a first current source 140. The constant current circuit 172 includes a PMOS transistor 121, a switch 151, and an NMOS transistor 131. The filter circuit 174 is provided with a capacitor 161. The snubber circuit 175 includes an NMOS transistor 130 and a second current source 141.

The pulse wave detector 110 detects whether or not the reference signal REF is input to the REF terminal 103, and outputs the signal DET. The current control oscillator 113 outputs a signal of an oscillation frequency proportional to the input oscillation current. The phase frequency comparator 111 compares the reference signal REF with the feedback signal FB_CLK and outputs the result. The charge pump circuit 112 outputs a voltage VCP based on an output signal of the phase frequency comparator 111. Buffer circuit 175 causes capacitor 161 to charge faster, i.e., boosts voltage VCP to a desired value and stabilizes it. The phase frequency comparator 111, the charge pump circuit 112, the filter circuit 174, the buffer circuit 175, the constant current circuit 172, the current control oscillator 113, and the frequency dividing circuit 114 constitute a PLL circuit for inputting a pair to REF The phase of the reference signal REF of the terminal 103 is adjusted.

Next, the connection of the oscillation circuit device 100 of the present embodiment will be described. The input terminal of the pulse wave detecting circuit 110 is connected to the REF terminal 103, and the output terminal is connected to the switch 150, the control terminal of the switch 152, and the input terminal of the inverter circuit 153. An output terminal of the inverter circuit 153 is connected to a control terminal of the switch 151. The first input terminal of the phase frequency comparator 111 is connected to the REF terminal 103, the second input terminal is connected to the output terminal of the frequency dividing circuit 114, and the output terminal is connected to the input terminal of the charge pump circuit 112. One end of the capacitor 161 constituting the filter circuit 174 is connected to the output terminal of the charge pump circuit 112, and the other end is connected to the ground terminal 102. The gate of the NMOS transistor 130 is connected to the drain of the NMOS transistor 131 and the drain of the PMOS transistor 121, the drain is connected to the power supply terminal 101, and the source is connected to one end of the switch 152 and one end of the second current source 141. The other end of the second current source 141 is connected to the ground terminal 102. The other end of the switch 152 is connected to the output terminal of the charge pump circuit 112. The gate of the NMOS transistor 131 is connected to the output terminal of the charge pump circuit 112, and the source is connected to the ground terminal 102. The source of the PMOS transistor 120 is connected to the power supply terminal 101, and the gate and the drain are connected to one end of the switch 150 and one end of the first current source 140. The other end of the first current source 140 is connected to the ground terminal 102. The source of the PMOS transistor 121 is connected to the power supply terminal 101, and the gate is connected to the other end of the switch 150. One end of the switch 151 is connected to the gate of the PMOS transistor 121, and the other end is connected to the drain of the PMOS transistor 121. The source of the PMOS transistor 122 is connected to the power supply terminal 101, the gate is connected to the gate of the PMOS transistor 121, and the drain is connected to the input terminal of the current controlled oscillator 113. An output terminal of the current control oscillator 113 is connected to an input terminal of the frequency dividing circuit 114.

Next, the operation of the oscillation circuit device 100 of the present embodiment will be described. First, a first mode in which the reference signal REF is not input to the REF terminal 103 will be described.

In the first mode, the pulse wave detecting circuit 110 outputs a signal DET indicating that it is not detected, the switch 150 and the switch 152 are turned on, and the switch 151 is turned off. The constant current circuit 171 causes the constant current IB1 of the first constant current source 140 to flow. Since the PMOS transistor 122 and the PMOS transistor 120 constitute a current mirror circuit, the respective drain current I1 is proportional to the current I3. For example, in the case where the size ratio of the PMOS transistor 120 to the PMOS transistor 122 is 1:1, the current I1 is equal to the current I3. The current control oscillator 113 outputs an output signal CLK of a frequency proportional to the input current I3, that is, the current IB1, from the CLK terminal. That is, the frequency of the output signal CLK is arbitrarily determined by the current value of the current IB1 or the size ratio of the PMOS transistor 120 and the PMOS transistor 122.

Moreover, since the PMOS transistor 121 and the PMOS transistor 120 constitute a current mirror circuit, the respective drain current I1 and the current I2 are proportional currents. For example, in the case where the size ratio of the PMOS transistor 120 to the PMOS transistor 121 is 1:1, the current I1 is equal to the current I2. By the current I2, the gate voltage VX of the NMOS transistor 130 rises, and the NMOS transistor 130 is turned on. Further, by the source current of the NMOS transistor 130, the capacitor 161 is charged and the voltage VCP rises. Thereby, when the NMOS transistor 131 using the gate receiving voltage VCP is turned on, the constant current circuit 172 and the buffer circuit 175 constitute a negative feedback circuit. Therefore, the voltage VCP which becomes the gate voltage of the NMOS transistor 131 is rapidly increased so that the drain current of the NMOS transistor 131 becomes equal to the current I2. In the subsequent constant state, the drain current of the NMOS transistor 130 of the buffer circuit 175 is equal to the constant current IB2 of the second constant current source 141, and the second constant current source 141 operates as a pull-down element.

As described above, since the oscillating circuit device 100 of the present embodiment includes the snubber circuit 175, the capacitor 161 can be charged faster in the first mode, that is, the voltage VCP can be quickly increased to a desired level. The voltage value can therefore quickly stabilize the frequency of the output signal CLK.

Next, a second mode in which the reference signal REF is input to the REF terminal 103 will be described. When changing from the first mode to the second mode, the pulse wave detecting circuit 110 outputs a signal DET indicating that the switch 150 and the switch 152 are turned off, and turns on the switch 151 via the inverter circuit 153. Since the switch 150 is turned off, the constant current circuit 171 is separated from the oscillation circuit device 100. Since the switch 151 is turned off, the buffer circuit 175 is separated from the filter circuit 174. Moreover, since the switch 151 is turned on, the PMOS transistor 121 and the PMOS transistor 122 constitute a current mirror circuit, and each of the drain current I2 is a current proportional to the current I3. For example, in the case where the size ratio of the PMOS transistor 121 to the PMOS transistor 122 is 1:1, the current I2 is equal to the current I3.

The NMOS transistor 131 functioning as a V/I conversion element V/I converts the output voltage VCP of the charge pump circuit 112 output based on the oscillation frequency of the reference signal REF to generate a drain current, and supplies it to the PMOS transistor 121. . The current I2 in the constant state is controlled by the negative feedback action of the PLL circuit so that the frequency of the reference signal REF and the output of the frequency dividing circuit 114, that is, the frequency of the feedback signal FB_CLK, become equal. More specifically, the phase frequency comparator 111 compares the reference signal REF with the feedback signal FB_CLK, outputs a voltage VCP from the charge pump circuit 112 and the filter circuit 174, and generates a current I2 from the NMOS transistor 131. Thus, the current control oscillator 113 outputs an output signal CLK based on the frequency of the voltage VCP from the CLK terminal. Since the switch 150 is turned off, the constant current circuit 171 does not affect the current I2 and the current I3.

2(a) to 2(d) are timing charts for explaining a state change in the oscillation circuit device 100 of the present embodiment, and the present embodiment will be described using Figs. 2(a) to 2(d). Effect. 2(a) is a time transition of the voltage VDD applied to the power supply terminal 101, FIG. 2(b) is a time transition of the output voltage VCP of the charge pump circuit 112, and FIG. 2(c) is a reference signal input to the REF terminal 103. The time lapse of the frequency of REF, Fig. 2(d) is the time lapse of the frequency of the output signal CLK obtained from the CLK terminal.

As shown in FIG. 2(a), when the voltage VDD is applied at time t0, since the reference signal REF is not input to the REF terminal 103, the oscillation circuit device 100 operates in the first mode by the constant current circuit 172 and the buffer. The negative feedback action of circuit 175 causes the output voltage VCP to rise rapidly from 0 V.

Subsequently, as shown in FIG. 2(c), when the reference signal REF is input at time t1, the oscillation circuit device 100 shifts to the second mode. At this time, since the current control oscillator 113 operates by a current corresponding to the voltage VCP that has reached a constant value, the output signal CLK of the CLK terminal does not cause a sharp frequency drop. Subsequently, by the PLL action, the frequency of the output signal CLK converges to a frequency equal to the reference signal REF.

As described above, the oscillation circuit device 100 of the present embodiment has a configuration in which the capacitance of the filter circuit 174 is increased by the output of the buffer circuit 175 that performs the negative feedback operation by the constant current circuit 172. Since the voltage of 161 is shortened, the charging period of the capacitor 161 can be shortened, and the output frequency fluctuation immediately after switching from the free oscillation state to the PLL operation can be suppressed.

Fig. 3 is a circuit diagram showing another configuration of the oscillation circuit device of the embodiment. The oscillation circuit device 300 has a configuration in which the filter circuit 174 includes a resistor 160. One end of the resistor 160 is connected to the output terminal of the charge pump circuit 112, and the other end is connected to the other end of the capacitor 161 and the switch 152.

As described above, as the phase compensation of the PLL circuit, the resistor 160 may be provided in the filter circuit 174. In the filter circuit 174, the output terminal of the buffer circuit 175 is connected between the capacitor 161 and the resistor 160 via the switch 152, and the same effect as described above can be obtained.

As described above, the oscillation circuit device of the present embodiment can improve the frequency characteristics by the insertion of the phase compensation resistor 160, and can easily balance the capacitance by connecting the output terminal of the buffer circuit 175 to the capacitor 161. The charging time of 161 is shortened. Thereby, it is possible to suppress a sudden drop in the output frequency immediately after switching from the free oscillation state to the PLL operation, and it is possible to prevent malfunction of an external device connected to the CLK terminal. Further, the capacitance 161 is not limited to the connection resistance, and the same effect can be obtained in any circuit configuration in which other elements are connected.

Further, of course, the oscillation circuit device of the present invention can be applied to various electronic devices that operate in a free-oscillation state and a reference signal REF input from the outside. For example, in a case where a configuration in which an oscillation frequency of a direct current/direct current (DC/DC) converter is freely changed from the outside is adopted, by using the oscillation circuit device of the present invention, A smooth transition of the oscillating signal provides a stable action DC/DC converter.

100,300‧‧‧Oscillation circuit device
101‧‧‧Power terminal
102‧‧‧ Grounding terminal
103‧‧‧REF terminal
104‧‧‧CLK terminal
110‧‧‧ Pulse detection circuit
111‧‧‧ phase frequency comparator
112‧‧‧Charge pump circuit
113‧‧‧ Current Controlled Oscillator
114‧‧‧dividing circuit
120, 121, 122‧‧‧ PMOS transistors
130, 131‧‧‧ NMOS transistor
140, 141‧‧‧ current source
150, 151, 152, 154‧ ‧ switch
153‧‧‧Inverter circuit
160‧‧‧resistance
161‧‧‧ Capacitance
171, 172‧‧‧ constant current circuit
174‧‧‧Filter circuit
175‧‧‧buffer circuit
CLK‧‧‧ output signal
DET‧‧ signal
FB_CLK‧‧‧ feedback signal
I1, I2, I3‧‧‧ current
IB1, IB2‧‧‧ constant current
REF‧‧‧ reference signal
T0, t1‧‧‧ time
VCP, VDD‧‧‧ voltage
VX‧‧‧ gate voltage

Fig. 1 is a circuit diagram showing a configuration of an oscillation circuit device of the embodiment. 2(a) to 2(d) are timing charts showing output signals in the oscillation circuit device of the embodiment. Fig. 3 is a circuit diagram showing another configuration of the oscillation circuit device of the embodiment. 4 is a circuit diagram showing a configuration of a conventional oscillation circuit device. 5(a) to 5(d) are timing charts showing output signals in the conventional oscillation circuit device.

100‧‧‧Oscillation circuit device

101‧‧‧Power terminal

102‧‧‧ Grounding terminal

103‧‧‧REF terminal

104‧‧‧CLK terminal

110‧‧‧ Pulse detection circuit

111‧‧‧ phase frequency comparator

112‧‧‧Charge pump circuit

113‧‧‧ Current Controlled Oscillator

114‧‧‧dividing circuit

120, 121, 122‧‧‧ PMOS transistors

130, 131‧‧‧ NMOS transistor

140, 141‧‧‧ current source

150, 151, 152‧ ‧ switch

153‧‧‧Inverter circuit

161‧‧‧ Capacitance

171, 172‧‧‧ constant current circuit

174‧‧‧Filter circuit

175‧‧‧buffer circuit

CLK‧‧‧ output signal

DET‧‧ signal

FB_CLK‧‧‧ feedback signal

I1, I2, I3‧‧‧ current

IB1, IB2‧‧‧ constant current

REF‧‧‧ reference signal

VCP, VDD‧‧‧ voltage

VX‧‧‧ gate voltage

Claims (3)

An oscillating circuit device comprising: an oscillator comprising a first constant current circuit, a second constant current circuit, a current mirror circuit and a current controlled oscillator, wherein the first constant current circuit causes a first constant current to flow, the second The constant current circuit causes a second constant current to flow, the current mirror circuit flowing an oscillating current proportional to the first constant current or the second constant current, the current controlling the oscillating signal output by the oscillator The frequency changes according to the input current value of the oscillation current; the phase locked loop circuit includes a phase frequency comparator, a charge pump circuit, a filter circuit, and a frequency dividing circuit, and the charge pump circuit An output voltage for controlling the second constant current, the phase frequency comparator comparing a reference signal input from the outside with a phase of the oscillating signal, the charge pump circuit inputting an output of the phase frequency comparator, The filter circuit includes a capacitance input to an output of the charge pump circuit, the frequency dividing circuit dividing an output of the current controlled oscillator; a buffer circuit that sets an output voltage of the second constant current circuit as an input voltage, and charges the capacitor of the filter circuit via a first switch, wherein the oscillating circuit device does not input the reference signal In the first mode, outputting an oscillating signal based on the first constant current of the oscillator, and outputting, in a second mode in which the reference signal is input, outputting the second constant current based on the oscillator An oscillating signal, wherein the oscillating circuit device turns on the first switch in the first mode, whereby the capacitor is charged by an output voltage of the snubber circuit, in the second mode Next, the first switch is turned off. The oscillating circuit device of claim 1, wherein the first constant current circuit comprises a first P-channel metal oxide semiconductor transistor and a constant current element connected in series, and the second constant current circuit comprises a series connection a second P-channel metal oxide semiconductor transistor connected to the first N-channel metal oxide semiconductor transistor, the gate of the first P-channel metal oxide semiconductor transistor being connected to the second P via a second switch a channel metal oxide semiconductor transistor, wherein a gate of the first N-channel metal oxide semiconductor transistor is connected to the filter circuit, and in the first mode, the second switch is turned on, thereby The second constant current circuit generates a current proportional to a current of the first constant current circuit, and in the second mode, the second switch is turned off, thereby generating a frequency based on the reference signal A current that is out of phase with the frequency of the oscillating signal. The oscillating circuit device according to claim 2, comprising: a pulse wave detecting circuit that detects a case where the reference signal is input, wherein the pulse wave detecting circuit controls the first switch according to an output signal The second switch.