CN106683993A - Preparation method for transistor ohmic contact electrode - Google Patents
Preparation method for transistor ohmic contact electrode Download PDFInfo
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- CN106683993A CN106683993A CN201611215467.3A CN201611215467A CN106683993A CN 106683993 A CN106683993 A CN 106683993A CN 201611215467 A CN201611215467 A CN 201611215467A CN 106683993 A CN106683993 A CN 106683993A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
The invention discloses a preparation method for a transistor ohmic contact electrode. The method comprises the steps of providing a semiconductor substrate containing a heavy doping P type GaAs layer and an InGaP layer; coating photoresist on the InGaP layer and forming at least one display area through exposure and development; depositing metal in the display area to form a metal layer; peeling off the photoresist; and at the temperature of 385-430 degrees centigrade, alloy 60-180 s, under the condition that the thickness of the P type GaAs layer is not smaller than 50 nm, the thickness of the InGaP layer is 30-50 nm, and the bottom of the metal layer at least comprises 20-50 nmPt, spreading the bottom of the metal layer to pass through the InGaP layer, thereby realizing the ohmic contact with the P type GaAs layer. The whole production process is simple, the time is saved, the controllability is greatly improved, and the yield of the products and the production efficiency are improved.
Description
Technical field
The present invention relates to semiconductor technology, more particularly to a kind of preparation method of transistor ohmic contact electrode.
Background technology
In the processing procedure of transistor, the preparation of electrode and be an important link with the connection of corresponding semiconductor layer,
It is the key factor for affecting performance of integrated circuits and stability.For example, heterojunction bipolar transistor (HBT) generally include according to
The collector layer of secondary stacking, base layer and emitter layer, prior art needs to adopt etch process when base electrode is made
Emitter layer even part base layer is gone to expose base layer to come divided by windowing, is then deposited in exposed base layer again
Metal simultaneously makes metal form low resistance, the Ohmic contact for stably contacting with base layer.
When portions of emitter semi-conducting material is removed, conventional engraving method includes dry etching and wet etching,
Dry etching is the emitter layer surface not covered by photoresistance by plasma bombardment, and wet etching is logical using chemical solution
Cross dissolving or react and remove the emitter surface not covered by photoresistance, so as to reach the purpose of part removal.
Above-mentioned no matter which kind of engraving method, technical process is all more complicated and very strict to precise requirements, slightly
Mistake will produce series of problems, and the change of such as current gain, product reliability are reduced and interfacial corrosion etc., on the one hand
The performance and yield of product are reduced, another aspect process controllability is poor.
The content of the invention
The invention provides a kind of transistor ohmic contacts the preparation method of electrode, which overcome existing for prior art
Weak point.
The technical solution adopted for the present invention to solve the technical problems is comprised the following steps：
1）Semiconductor base is provided or is formed, the semiconductor base includes heavily doped p-type GaAs layer and located at the p-type
InGaP layers on GaAs layers, wherein the thickness of the p-type GaAs layer is not less than 50 nm, the thickness of the InGaP layers is 30-
50 nm；
2）At least one aobvious open region, the aobvious open region are formed in InGaP layers top coating photoresistance and by exposure, development
The interior InGaP layer surfaces are exposed；
3）Deposited metal, then peels off photoresistance, is formed corresponding to the metal level in the aobvious open region, and the metal level is at least wrapped
The direct Pt layers contacted with the InGaP layers are included, and the thickness of a Pt layers is 20-50 nm；
4）The alloy 60-180 s at 385-430 DEG C, the metal level bottom diffuse through the InGaP layers and with the p-type
GaAs layers form Ohmic contact the electrode is obtained.
Preferably, the metal level also includes a Ti layers, is formed on a Pt layers, and thickness is 20-60
nm；2nd Pt layers, are formed on a Ti layers, and thickness is 10-50 nm；Au layers, be formed at the 2nd Pt layers it
On, thickness is 20-500 nm；2nd Ti layers, are formed on the Au layers, and thickness is 5-20 nm.
Preferably, the semiconductor base also includes the protective layer on the InGaP layers, and the photoresistance is coated on
The protective layer；Step 2）In, also including the protective layer in the etching removal aobvious open region with the exposed InGaP layers
Surface.
Preferably, the protective layer is SiN.
Preferably, the p-type GaAs layer forms at least a portion of the base stage of heterojunction bipolar transistor, the InGaP
Layer forms at least a portion of the emitter stage of heterojunction bipolar transistor, and the electrode forms the base stage of heterojunction bipolar transistor
At least a portion of electrode.
Preferably, the semiconductor base also includes GaAs layers, and the p-type GaAs layer is on the GaAs layers；It is described
GaAs layers form at least a portion of the colelctor electrode of heterojunction bipolar transistor.
Compared to prior art, the present invention makes metal have enough diffusion depths logical to spread by high temperature alloy process
Cross InGaP layers and realize Ohmic contact with p-type GaAs layer, the step for subtracted but etching InGaP layers, make whole processing procedure become letter
It is single, save time, controllability is greatly improved, it is to avoid the step for etch the various problems to be brought, improve the good of product
Rate and production efficiency；The Ohmic contact contact resistance of formation is low, heat stability is high, surface quality good, is particularly suited for HBT,
In the production procedure of the products such as BIFET, BIHEMT.
Description of the drawings
Fig. 1 is the schematic flow sheet of one embodiment of the invention；
Fig. 2 is the structural representation of metal level in Fig. 1；
Fig. 3 is the schematic flow sheet of another embodiment of the present invention.
Specific embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.Each accompanying drawing of the present invention only illustrate with
The present invention is easier to understand, its concrete ratio can be adjusted according to design requirement.Opposed member in figure described in text
Upper and lower relation, for the relative position for referring to component is will be understood that in those skilled in the art, therefore can all overturn and be in
Existing identical component, this should all belong to the scope disclosed by this specification together.Additionally, the number of the element and structure shown in figure,
The thickness of layer and the thickness contrast of interlayer, it is merely illustrative, do not limited with this, actually can be adjusted according to design requirement
It is whole.
Following examples are specifically described by taking the preparation method of HBT base electrodes as an example, provide or formed HBT first
Semiconductor base, semiconductor base includes the collector layer-GaAs layers 1, base layer-heavily doped for stacking gradually from the bottom to top
P-type GaAs layer 2 and emitter layer-InGaP layers 3, the wherein thickness of p-type GaAs layer 2 are not less than 50 nm, the thickness of InGaP layers
For 30-50 nm.InGaP/ GaAs HBT have high power density and efficient excellent specific property, are widely used in power and put
In big device.
When base stage is made, first in the surface-coated photoresistance 4 of InGaP layers 3, the conventional system such as photoresistance 4 is exposed, develop
Journey forms aobvious open region a in default base electrode position, and the InGaP for showing open region a bottoms is exposed.Then deposited metal and pass through
Peel off and remove photoresistance and the metal on photoresistance, formed corresponding to the metal level 5 in aobvious open region a.The method of deposition is general
It is physical vapour deposition (PVD).This metal deposition can provide preferable metal and tear golden effect.Metal level 5 at least includes direct
Contact with InGaP layers 3 and thickness for 20-50 nm Pt.Used as a preferred example, with reference to Fig. 2, metal level 5 is Pt/
The laminated construction of Ti/Pt/Au/Ti, is respectively from the bottom to top：First Pt layers 51, thickness is 20-50 nm；First Ti layers 52 are thick
Spend for 20-60 nm；2nd Pt layers 53, thickness is 10-50 nm；Au layers 54, thickness is 20-500 nm；2nd Ti layers 55, thickness
For 5-20 nm.
Then, alloy treatment is carried out, 60-180 s is incubated at 385-430 DEG C.Under these conditions, a Pt layers 51
Diffuse through InGaP layers 3 and be at least partially into p-type GaAs layer 2, contact interface formed heavily doped layer, so as to p-type GaAs
Layer 2 forms Ohmic contact, completes the making of base electrode.Using Pt as underlying metal, its work function is larger, is easy to reduction to connect
Tactile barrier height, diffusion is also preferable.Alloy process preferably carries out avoiding metal oxygen under the protection of inert atmosphere
Other unnecessary reactions such as change.In insulating process, by there is series of physical, chemical reaction, energy in metal and quasiconductor
Enough barrier heights for substantially reducing golden half contact area, electronics easily by golden half contact area, so as to form low resistance and high stable
The Ohmic contact of property.
In another embodiment, it is that semiconductor base is also included located at InGaP with the difference of previous embodiment with reference to Fig. 3
Protective layer 6 on layer 3.Photoresistance 4 is coated on the surface of protective layer 6.The conventional processing procedure such as photoresistance 4 is being exposed, is being developed pre-
If base electrode position is formed after aobvious open region a, the protective layer within aobvious open region a is removed by etching and InGaP is caused
Layer 3 is exposed, and then redeposited metal forms metal level 5.The specifically SiN of protective layer 6, by magnetic control sputtering plating, ion evaporation, electric arc
The methods such as ion evaporation, chemical vapor deposition are formed, and can completely cut off the impact of steam and corrosive deposit to InGaP layers 3, further
Improve the stability of transistor.
Above-described embodiment is only used for further illustrating a kind of preparation method of transistor ohmic contact electrode of the present invention, but
The invention is not limited in embodiment, what every technical spirit according to the present invention was made to above example any simply repaiies
Change, equivalent variations and modification, each fall within the protection domain of technical solution of the present invention.
Claims (6)
1. a kind of transistor ohmic contacts the preparation method of electrode, it is characterised in that comprise the following steps：
1）Semiconductor base is provided or is formed, the semiconductor base includes heavily doped p-type GaAs layer and located at the p-type
InGaP layers on GaAs layers, wherein the thickness of the p-type GaAs layer is not less than 50 nm, the thickness of the InGaP layers is 30-
50 nm；
2）At least one aobvious open region, the aobvious open region are formed in InGaP layers top coating photoresistance and by exposure, development
The interior InGaP layer surfaces are exposed；
3）Deposited metal, then peels off photoresistance, is formed corresponding to the metal level in the aobvious open region, and the metal level is at least wrapped
The direct Pt layers contacted with the InGaP layers are included, and the thickness of a Pt layers is 20-50 nm；
4）The alloy 60-180 s at 385-430 DEG C, the metal level bottom diffuse through the InGaP layers and with the p-type
GaAs layers form Ohmic contact the electrode is obtained.
2. preparation method according to claim 1, it is characterised in that：The metal level also includes
First Ti layers, are formed on a Pt layers, and thickness is 20-60 nm；
2nd Pt layers, are formed on a Ti layers, and thickness is 10-50 nm；
Au layers, are formed on the 2nd Pt layers, and thickness is 20-500 nm；
2nd Ti layers, are formed on the Au layers, and thickness is 5-20 nm.
3. preparation method according to claim 1, it is characterised in that：The semiconductor base is also included located at described
Protective layer on InGaP layers, the photoresistance is coated on the protective layer；Step 2）In, also remove including etching described
Protective layer in aobvious open region is with the exposed InGaP layer surfaces.
4. preparation method according to claim 3, it is characterised in that：The protective layer is SiN.
5. preparation method according to claim 1, it is characterised in that：The p-type GaAs layer forms heterogenous dual-pole crystal
At least a portion of the base stage of pipe, the InGaP layers form at least a portion of the emitter stage of heterojunction bipolar transistor, described
Electrode forms at least a portion of the base electrode of heterojunction bipolar transistor.
6. preparation method according to claim 5, it is characterised in that：The semiconductor base also includes GaAs layers, the p
Type GaAs layer is on the GaAs layers；The GaAs layers form at least a portion of the colelctor electrode of heterojunction bipolar transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611215467.3A CN106683993A (en) | 2016-12-26 | 2016-12-26 | Preparation method for transistor ohmic contact electrode |
| PCT/CN2017/117362 WO2018121369A1 (en) | 2016-12-26 | 2017-12-20 | Compound semiconductor transistor and power amplifier having the transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611215467.3A CN106683993A (en) | 2016-12-26 | 2016-12-26 | Preparation method for transistor ohmic contact electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106683993A true CN106683993A (en) | 2017-05-17 |
Family
ID=58870517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611215467.3A Pending CN106683993A (en) | 2016-12-26 | 2016-12-26 | Preparation method for transistor ohmic contact electrode |
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| Country | Link |
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| CN (1) | CN106683993A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018121369A1 (en) * | 2016-12-26 | 2018-07-05 | 厦门市三安集成电路有限公司 | Compound semiconductor transistor and power amplifier having the transistor |
| CN109817701A (en) * | 2018-12-25 | 2019-05-28 | 泉州三安半导体科技有限公司 | A kind of thinning method of heterojunction bipolar transistor emitter structure and emitter |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07211729A (en) * | 1994-01-26 | 1995-08-11 | Fujitsu Ltd | Hetero-junction bipolar transistor (hbt) and its manufacture |
| US5508536A (en) * | 1993-04-07 | 1996-04-16 | Sharp Kabushiki Kaisha | Heterojunction bipolar transistor having low electron and hole concentrations in the emitter-base junction region |
| EP1148554A2 (en) * | 2000-04-19 | 2001-10-24 | Sharp Kabushiki Kaisha | Heterojunction bipolar transistor and manufacturing method therefor |
| CN1577883A (en) * | 2003-06-30 | 2005-02-09 | 松下电器产业株式会社 | Hetero-junction bipolar transistor and manufacturing method thereof |
| CN1855533A (en) * | 2005-04-21 | 2006-11-01 | 松下电器产业株式会社 | Heterojunction bipolar transistor and method for fabricating the same |
| CN1956215A (en) * | 2005-07-26 | 2007-05-02 | 索尼株式会社 | Semiconductor device |
-
2016
- 2016-12-26 CN CN201611215467.3A patent/CN106683993A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508536A (en) * | 1993-04-07 | 1996-04-16 | Sharp Kabushiki Kaisha | Heterojunction bipolar transistor having low electron and hole concentrations in the emitter-base junction region |
| JPH07211729A (en) * | 1994-01-26 | 1995-08-11 | Fujitsu Ltd | Hetero-junction bipolar transistor (hbt) and its manufacture |
| EP1148554A2 (en) * | 2000-04-19 | 2001-10-24 | Sharp Kabushiki Kaisha | Heterojunction bipolar transistor and manufacturing method therefor |
| CN1577883A (en) * | 2003-06-30 | 2005-02-09 | 松下电器产业株式会社 | Hetero-junction bipolar transistor and manufacturing method thereof |
| CN1855533A (en) * | 2005-04-21 | 2006-11-01 | 松下电器产业株式会社 | Heterojunction bipolar transistor and method for fabricating the same |
| CN1956215A (en) * | 2005-07-26 | 2007-05-02 | 索尼株式会社 | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018121369A1 (en) * | 2016-12-26 | 2018-07-05 | 厦门市三安集成电路有限公司 | Compound semiconductor transistor and power amplifier having the transistor |
| CN109817701A (en) * | 2018-12-25 | 2019-05-28 | 泉州三安半导体科技有限公司 | A kind of thinning method of heterojunction bipolar transistor emitter structure and emitter |
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Application publication date: 20170517 |