WO2018121369A1

WO2018121369A1 - Compound semiconductor transistor and power amplifier having the transistor

Info

Publication number: WO2018121369A1
Application number: PCT/CN2017/117362
Authority: WO
Inventors: 颜志泓; 王江; 朱庆芳; 魏鸿基; 窦永铭; 许燕丽; 李斌
Original assignee: 厦门市三安集成电路有限公司
Priority date: 2016-12-26
Filing date: 2017-12-20
Publication date: 2018-07-05

Abstract

Provided are a compound semiconductor transistor and a power amplifier having the transistor. The transistor comprises a collector layer (4), a secondary collector layer (2), and an intermediate layer (3) provided between the collector layer (4) and the secondary collector layer (2). The collector layer (4) and the secondary collector layer (2) respectively are constituted by GaAs. The intermediate layer (3) comprises a material having an energy gap less than that of GaAs.

Description

Compound semiconductor transistor and power amplifier having the same

[0001] Related Strings

[0002] The present application claims the following priority: Chinese Invention Patent Application No. 201611216552.1, entitled "A Compound Semiconductor Heterojunction Bipolar Transistor", filed on December 26, 2016; Chinese Invention Patent Application No. 2 01611215467.3, The article entitled "Preparation of a Transistor Ohmic Contact Electrode" was submitted on December 26, 2016. The entire contents of the above application are incorporated herein by reference.

Technical field

The present invention relates to semiconductor technology, and more particularly to a compound semiconductor transistor.

Background technique

[0004] Generally, the heterojunction bipolar transistor epitaxial structure is selected in the collector layer design to form a so-called single heterojunction or double heterojunction transistor with a homogenous or heterogeneous material of the base layer. The sub-collector layer is designed to form a collector ohmic metal contact in a highly viscous concentration mode or a thicker thickness mode. Therefore, the stray resistance of the collector is determined by the high concentration and thickness of the sub-collector layer, and the metal annealing process in the subsequent process; the design of the device layout from the collector to the base is also Its stray resistance has an effect. The presence of stray resistance affects the performance of heterojunction bipolar transistors.

[0005] Common methods for reducing stray collector resistance include: (1) Optimal design of device layout from collector to base distance, but this method has a certain distance limitation, and the distance is at least 1 to 1.8 micrometers. (2) increasing the thickness of the secondary collector layer and the high concentration, but the method increases the thickness of the secondary collector layer, which increases the difficulty in the chip process stage, including the device morphology during the wet etching process. There are obvious sidewall etching problems; or the need to implant with greater energy or concentration during ion implantation to effectively isolate the device; (3) Optimization of metal annealing procedures in the process, such as annealing Inter- and temperature, but this method is not easy to control, it is prone to excessive roughening of the metal surface, or like leopard-like patchy, nodular or blister-like defects; or by transmission line measurement (TLM) Nonlinear stray resistance characteristic results, etc.

technical problem Problem solution

Technical solution

According to a first aspect of the present invention, a compound semiconductor heterojunction bipolar transistor is provided, comprising a collector layer, a sub-collector layer, and an intermediate portion between the collector layer and the sub-collector layer The collector layer and the sub-collector layer are respectively composed of GaAs, and the intermediate layer includes a material having an energy gap smaller than GaAs.

[0007] Preferably, the intermediate layer is composed of InxGaAs, where 0 < x ≤ 0.4.

[0008] Preferably, the thickness of the intermediate layer is 0.5% to 1% of the thickness of the collector layer.

[0009]

[0010] Preferably, the intermediate layer is composed of an InxGaAs/GaAs superlattice structure, where 0 < x≤0.4.

[0011] Preferably, the period of the superlattice structure ranges from 1 to 100.

[0012] Preferably, the secondary collector layer has a higher concentration than the collector layer, or the secondary collector layer has a thickness greater than the collector layer; and the secondary collector layer has a set formed thereon. Electrode electrode.

[0013] Preferably, further comprising a base layer disposed on the collector layer and composed of GaAs; an emitter layer disposed on the base layer and composed of InGaP; An emitter contact gap layer formed on the emitter layer and composed of GaAs; and an emitter contact layer formed on the emitter contact gap layer and made of InGaAs.

[0014] In the above transistor structure, a low energy gap material is introduced between the collector layer and the sub-collector layer to form an intermediate layer, and the thickness and the impurity concentration of the sub-collector are under ordinary conditions, and the stray resistance of the collector can be reduced. The value of the DC power consumption of the amplifier component based on the compound semiconductor heterojunction bipolar transistor power is improved, and the additional power efficiency of the device is improved. The power amplifier based on the above structure is applied to a handheld device such as a mobile phone, and the standby time can be increased.

[0015] According to a second aspect of the present invention, there is also provided a method of fabricating a transistor ohmic contact electrode, comprising the steps of:

[0016] 1) providing or forming a semiconductor substrate, the semiconductor substrate comprising a heavily doped p-type GaAs layer and an InGaP layer disposed on the p-type GaAs layer, wherein the p-type GaAs layer has a thickness not less than 50 nm, the thickness of the InGaP layer is 30-50 nm;

[0017] 2) coating a photoresist over the InGaP layer and forming at least one display region by exposure and development, The surface of the InGaP layer in the exposed area is bare;

3) depositing a metal, and then stripping the photoresist to form a metal layer corresponding to the germanium region, the metal layer comprising at least a first Pt layer directly in contact with the InGaP layer, and the first Pt layer Thickness is 20-50 nm;

4) alloying at 385-430 ° C for 60-180 s, the bottom of the metal layer diffusing through the InGaP layer and forming ohmic contact with the p-type GaAs layer to produce the electrode.

[0020] Preferably, the metal layer further includes a first Ti layer formed on the first Pt layer and having a thickness of 20-60 nm; and a second Pt layer formed on the first Ti layer , a thickness of 10-50 nm; an Au layer formed on the second Pt layer, having a thickness of 20-500

And a second Ti layer formed on the Au layer and having a thickness of 5-20 nm.

[0021] Preferably, the semiconductor substrate further includes a protective layer disposed on the InGaP layer, the photoresist is applied to the surface of the protective layer; and in step 2), further including etching to remove the display A protective layer in the region exposes the surface of the InGaP layer.

[0022] Preferably, the protective layer is SiN.

[0023] Preferably, the p-type GaAs layer forms at least a portion of a base of the heterojunction bipolar transistor, and the In GaP layer forms at least a portion of an emitter of the heterojunction bipolar transistor, and the electrode forms a different At least a portion of the base electrode of the bipolar transistor.

[0024] Preferably, the semiconductor substrate further comprises a GaAs layer, wherein the p-type GaAs layer is disposed on the GaAs layer; and the GaAs layer forms at least a portion of a collector of the heterojunction bipolar transistor.

Advantageous effects of the invention

Beneficial effect

[0025] Compared with the prior art, the above method uses a superalloy process to make the metal have a sufficient diffusion depth to diffuse through the InGaP layer and achieve ohmic contact with the p-type GaAs layer, thereby reducing the step of etching the InGaP layer, so that the whole The process is simple, economical, and the controllability is greatly improved, avoiding various problems that may be caused by etching at this step, improving product yield and production efficiency; forming ohmic contact contact resistance, thermal stability High surface quality, especially suitable for the production process of HBT, BIFET, BIHEMT and other products.

Brief description of the drawing DRAWINGS

1 is a schematic view showing an epitaxial structure of Embodiment 1 of the present invention.

2 is a schematic diagram showing a partial epitaxial structure of Embodiment 2 of the present invention.

3 is a schematic flow chart of Embodiment 3 of the present invention;

4 is a schematic structural view of a metal layer in FIG. 3;

5 is a schematic flow chart of Embodiment 4 of the present invention.

Embodiments of the invention

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The drawings of the present invention are merely illustrative for easier understanding of the present invention, and the specific proportions thereof can be adjusted according to design requirements. The above-described relative relationship of the elements in the drawings described herein will be understood by those skilled in the art to refer to the relative positions of the members, and therefore, the same members may be turned over and the like, which are all within the scope of the present disclosure. In addition, the number of components and structures shown in the drawings, the thickness of the layers, and the thickness comparison between the layers are merely examples, and are not limited thereto, and may be actually adjusted according to design requirements.

[0032] Referring to FIG. 1, an epitaxial structure of a compound semiconductor heterojunction bipolar transistor (HBT) according to an embodiment includes a substrate 1, a sub-collector layer 2, an intermediate layer 3, which are sequentially stacked from bottom to top. The collector layer 4, the base layer 5, the emitter layer 6, the emitter contact gap layer 7, and the emitter contact layer 8. Taking InGaP/GaAs type HB T as an example, the substrate 1 is semi-insulating GaAs; the sub-collector layer 2 and the collector layer 4 are n-type GaAs, and the sub-collector layer 2 has a higher concentration than the collector layer 4; The intermediate layer 3 is InxGaAs, where 0<x≤0.4; the base layer 5 is p-type GaAs, the emitter layer 6 is InGaP, and a heterojunction is formed therebetween; the emitter contact gap layer 7 is n-type GaAs, emission The contact layer 8 is InGaAs. The epitaxial structure is formed by crystal growth by MOCVD (Organic Metal Chemical Vapor Growth) or MBE (Molecular Beam Epitaxy), and a collector electrode and a base are formed on the sub-collector layer 2 by etching, metal deposition, or the like, respectively. A base electrode is formed on layer 5 and an emitter electrode is formed on emitter contact layer 8.

[0033] In this embodiment, the intermediate layer 3 is an InxGaAs having a smaller energy gap than GaAs, and the thickness is 0.5% to 1% of the collector layer 4. Specifically, the thickness of the intermediate layer 3 is not exceeded after the stress compensation according to the Mattews and Blakeslee model. Calculating the critical thickness, by changing the barrier layer of the energy band in the semiconductor technology, the collector stray resistance and the ohmic contact resistance of the collector metal can be reduced without increasing the thickness of the sub-collector layer 2 or Degree, only need to follow the conventional annealing conditions. For example, the thickness of the conventional sub-collector layer is 0.3 to 0.8 μηι, and the thickness of the collector layer is 0.5 to 1.2 μm. Under this premise, an InxGaAs intermediate layer having a thickness of 3 to 15 Å is formed therebetween. The purpose of lowering the barrier can be significantly reduced, and as the composition of In increases (X value becomes larger), the barrier layer becomes lower, and the effect is more remarkable.

[0034] The HBT of the present embodiment can be applied to a 3G/4G power amplifier. For power amplifiers, additional power efficiency (PAE) is an important parameter. The PAE is defined as the ratio of the difference between the output power Pout and the input power Pin to the DC input power Pdc: (P _OU t-Pin) / Pd _C . The PAE is a pointer indicating the quality of efficiency, and the larger the value, the more the power consumption of the power amplifier can be suppressed. The stray resistance value of the collector layer is lowered by the arrangement of the intermediate layer 3, that is, the DC power of the device is lowered, the PAE is improved, and the overall performance is improved. The above 3G/4G power amplifier is applied to a handheld device such as a mobile phone to increase standby time.

Referring to FIG. 2, the difference between the HBT epitaxial structure of Embodiment 2 and Embodiment 1 is that the intermediate layer 9 is composed of an InxGa As/GaAs superlattice structure, where 0<x≤0.4. Specifically, the InxGaAs/GaAs superlattice structure is a multilayer film in which an InxGaAs thin layer 91 and a GaAs thin layer 92 are alternately grown and maintained strictly periodic, each of which has a thickness ranging from several nanometers to several tens of nanometers. The thickness of the InxGaAs thin layer 91 in the superlattice structure is not more than the critical thickness calculated according to the Mattews and Blakeslee model after stress compensation. The superlattice structure of the intermediate layer 9 has a thin layer 91 of InxGaAs at both ends, and the period ranges from 1 to 100. The quantum well is formed by the InxGaAs/Ga As superlattice structure, and the carrier concentration in the quantum well is increased by the increase of the In composition, thereby reducing the collector stray resistance and the collector metal ohmic contact resistance. Specifically, in the intermediate layer 9 of the InxGaAs/GaAs superlattice structure, the x values of the respective InxGaAs thin layers 91 may be the same or different.

[0036] In the process of the transistor, the preparation of the electrodes and the connection with the corresponding semiconductor layers are an important link and are the key factors affecting the performance and stability of the integrated circuit. For example, a heterojunction bipolar transistor (HB T) generally includes a collector layer, a base layer, and an emitter layer which are sequentially stacked. In the prior art, a base electrode is formed, and an etch process is required to even the emitter layer. Part of the base layer is removed by exposing the base layer with a germanium window, and then depositing metal on the exposed base layer and forming a low resistance, stable contact ohmic contact between the metal and the base layer.

[0037] In the removal of a portion of the emitter semiconductor material, common etching methods include dry etching and wet etching. The dry etching is performed by plasma bombardment of the surface of the emitter layer that is not covered by the photoresist, and the wet etching is performed by using chemistry. The solution removes the surface of the emitter that is not covered by the photoresist by dissolution or reaction, thereby reaching a portion The purpose of removal.

[0038] Regardless of the etching method described above, the process is complicated and the accuracy is very strict. A slight error causes a series of problems, such as a change in current gain, a decrease in product reliability, and interface corrosion. The product performance and yield are reduced, and the process controllability is poor.

[0039] The following embodiment discloses a method of fabricating a transistor ohmic contact electrode that overcomes the deficiencies of the prior art described above. The following examples are specifically described by taking the preparation method of the HBT base electrode as an example.

Referring to FIG. 3, a semiconductor substrate of an HBT is first provided or formed. The semiconductor substrate includes a collector layer-GaAs layer 11 stacked in order from bottom to top, a base layer-heavy p-type GaAs layer 12, and an emitter. The layer-InG aP layer 13, wherein the p-type GaAs layer 12 has a thickness of not less than 50 nm, and the InGaP layer has a thickness of 30-50 nm. InGaP/GaAs HBTs are characterized by high power density and high efficiency and are widely used in power amplifiers.

[0041] In the fabrication of the base electrode, first, a photoresist 14 is coated on the surface of the InGaP layer 13, and a conventional process such as exposure, development, and the like is performed to form a display region a at a predetermined base electrode position, and a bottom portion of the display region a is formed. InGaP bare. The metal is then deposited and the photoresist and the metal over the photoresist are removed by lift-off to form a metal layer 15 corresponding to the exposed region a. The method of deposition is generally physical vapor deposition. This metal deposition method gives a better metal tearing effect. The metal layer 15 includes at least Pt which is in direct contact with the InGaP layer 13 and has a thickness of 20 to 50 nm. As a preferred example, referring to FIG. 4, the metal layer 15 is a stacked structure of Pt/i/Pt/Au/Ti, from bottom to top: first Pt layer 51, thickness 20-50 nm; first Ti Layer 52, having a thickness of 20-60 nm; a second Pt layer 53, having a thickness of 10-50 nm; an Au layer 54, having a thickness of 20-500 nm; and a second Ti layer 55 having a thickness of 5-20 nm.

[0042] Next, alloy treatment is carried out, and the temperature is maintained at 385-430 ° C 60-180

s. Under the above conditions, the first Pt layer 51 diffuses through the InGaP layer 13 and at least partially enters the p-type GaAs layer 12, forming a high impurity layer at the contact interface, thereby forming an ohmic contact with the p-type GaAs layer 12, completing the base electrode Production. With Pt as the underlying metal, the work function is large, which is convenient to reduce the contact barrier height, and the diffusion performance is also better. The alloying process is preferably carried out under the protection of an inert atmosphere to avoid other unnecessary reactions such as metal oxidation. During the heat preservation process, metals and semiconductors can significantly reduce the barrier height of the gold half-contact region by a series of physical and chemical reactions, and electrons easily pass through the gold half-contact region, thereby forming Low resistance and high stability ohmic contact.

In another embodiment, referring to FIG. 5, the difference from the foregoing embodiment is that the semiconductor substrate further includes a protective layer 16 disposed over the InG aP layer 13. The photoresist 14 is applied to the surface of the protective layer 16. After a conventional process such as exposure, development, or the like is performed on the photoresist 14, a germanium region a is formed at a predetermined base electrode position, the protective layer within the germanium region a is removed by etching to expose the InGaP layer 13 and then deposited with a metal. Metal layer 15. The protective layer 16 is specifically SiN, which is formed by magnetron sputtering, ion evaporation, arc ion evaporation, chemical vapor deposition, etc., to isolate the influence of water vapor and corrosive substances on the InGaP layer 13, and further improve the stability of the transistor.

The above embodiments are only used to further illustrate a compound semiconductor transistor of the present invention, but the present invention is not limited to the embodiments, and any simple modifications and equivalent changes made to the above embodiments in accordance with the technical essence of the present invention are Modifications are all within the scope of protection of the technical solutions of the present invention.

Claims

Claim

[Claim 1] A compound semiconductor transistor, comprising: a collector layer, a sub-collector layer, and an intermediate layer disposed between the collector layer and the sub-collector layer; the collector layer and the sub-collector The layers are each composed of GaAs, and the intermediate layer includes a material having a smaller energy gap than GaAs.

[Claim 2] The compound semiconductor transistor according to claim 1, wherein the intermediate layer is composed of InxGaAs, where 0 < x ≤ 0.4.

[Claim 3] The compound semiconductor transistor according to claim 2, wherein the intermediate layer has a thickness of 0.5% to 1% of the thickness of the collector layer.

[Claim 4] The compound semiconductor transistor according to claim 1, wherein the intermediate layer has a thickness of 3 to 15 nm.

[Claim 5] The compound semiconductor transistor according to claim 1, wherein the intermediate layer is composed of an InxGaAs/GaAs superlattice structure, wherein 0 < x ≤ 0.4.

[Claim 6] The compound semiconductor transistor according to claim 5, wherein the superlattice structure has a period of from 1 to 100.

[Claim 7] The compound semiconductor transistor according to claim 1, wherein: the secondary collector layer has a higher impurity concentration than the collector layer, or the sub-collector layer has a thickness greater than a collector layer; a collector electrode is formed on the sub-collector layer.

[Claim 8] The compound semiconductor transistor according to claim 1, further comprising: a base layer provided on the collector layer and composed of GaAs; and disposed in the base layer And an emitter layer composed of InGaP; an emitter contact gap layer formed on the emitter layer and composed of GaAs; and an emitter contact gap layer formed on the emitter contact gap layer and composed of InGaAs Emitter contact layer.

[Claim 9] The compound semiconductor transistor according to claim 1, further comprising: a base layer formed on the collector layer and composed of GaAs, the thickness of which is not less than 50 η m;

An emitter layer formed on the base layer and composed of InGaP; having a thickness of 30-50 nm.

The compound semiconductor transistor according to claim 9, further comprising: a semiconductor substrate and a GaAs layer thereon, the base layer being disposed on the GaAs layer, the GaAs layer forming at least a portion of a collector of the transistor.

The compound semiconductor transistor according to claim 9, further comprising: a metal layer provided on said base layer, comprising at least a first Pt layer directly in contact with said InGaP layer.

The compound semiconductor transistor according to claim 11, wherein the bottom portion of the metal layer is diffused through the InGaP layer to form an ohmic contact with the base layer.

The compound semiconductor transistor according to claim 11, wherein the first Pt layer has a thickness of 20 to 50 nm.

The compound semiconductor transistor according to claim 11, wherein the metal layer further comprises:

a first Ti layer formed on the first Pt layer and having a thickness of 20-60 nm;

a second Pt layer formed on the first Ti layer and having a thickness of 10-50

An Au layer formed on the second Pt layer and having a thickness of 20-500 nm;

A second Ti layer is formed on the Au layer and has a thickness of 5-20 nm.

The compound semiconductor transistor according to claim 11, wherein the metal layer is formed by the following method:

(1) coating a photoresist over the InGaP layer and forming at least one display region by exposure and development, wherein the surface of the InGaP layer in the display region is bare;

(2) depositing a metal, and then stripping the photoresist to form a metal layer corresponding to the germanium region, the metal layer including at least a first Pt layer directly in contact with the InGaP layer, and the first Pt layer The thickness is 20-50 nm;

(3) Alloy 60-180 at 385-430 °C

s, the bottom of the metal layer diffuses through the InGaP layer and forms an ohmic contact with the p-type GaAs layer to produce an electrode.

The compound semiconductor transistor according to claim 11, wherein the electrode forms at least a part of a base electrode of the transistor.

A power amplifier comprising the compounded semiconductor of any one of claims 1 to 16 01

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