KR101184321B1 - Field Effect Transistor and manufacturing method for the same - Google Patents

Abstract

The present invention discloses a field effect transistor and a method of manufacturing the same. The method includes forming a Schottky barrier layer on the substrate; Forming a first gate electrode comprising a first bottom metal layer on the Schottky barrier layer; Forming a second gate electrode on the Schottky barrier layer, the second gate electrode spaced apart from the first gate electrode and comprising a second bottom metal layer; And heat treating the substrate to form a first diffusion layer and a second diffusion layer in which materials of the first bottom metal layer and the second bottom metal layer are respectively diffused into the Schottky barrier layer. The first diffusion layer and the second diffusion layer have different depths spreading from the upper surface of the Schottky barrier layer to the inside.

Description

Field Effect Transistor and manufacturing method for the same

The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly to a compound semiconductor field effect transistor and a method of manufacturing the same.

High Electron Mobility Transistor (HEMT), a compound semiconductor device, is one of the field effect transistors, and has excellent speed characteristics compared to semiconductor devices using silicon. It is widely used in application devices in the 10 GHz to 100 GHz) band. In addition, the HEMT device has excellent noise characteristics, and has been applied to the fabrication of MMICs (MMICs), which are one of high-performance wireless communication components.

The HEMT is classified into a depletion-mode transistor having a negative threshold voltage and an enhancement-mode transistor having a positive value. Typically, the depletion mode HEMT is used to manufacture the MMIC, but recently, the depletion mode and the increase mode transistors are implemented in one integrated circuit, and the application range thereof is gradually expanded. In order to satisfy these technical requirements, a process technology for integrating elements of two modes (depletion mode field effect transistor and incremental mode field effect transistor) having different threshold voltages into one semiconductor substrate is required.

An object of the present invention is to provide a depletion mode field effect transistor, a field effect transistor capable of forming an incremental mode field effect transistor on a single substrate, and a method of manufacturing the same.

In order to achieve the above technical problem, the present invention provides a method for manufacturing a field effect transistor. Its method includes forming a Schottky barrier layer on a substrate; Forming a first gate electrode comprising a first bottom metal layer on the Schottky barrier layer; Forming a second gate electrode on the Schottky barrier layer, the second gate electrode spaced apart from the first gate electrode and comprising a second bottom metal layer; And heat treating the substrate to form a first diffusion layer and a second diffusion layer in which materials of the first bottom metal layer and the second bottom metal layer are respectively diffused into the Schottky barrier layer. The first diffusion layer and the second diffusion layer are different from each other in depth from the upper surface of the Schottky barrier layer. Here, the depletion mode field effect transistor and the increase mode field effect transistor having different threshold voltages according to the thicknesses of the first and second diffusion layers may be formed on one substrate.

According to one embodiment, the first and second bottom metal layers are formed to have different thicknesses.

According to one embodiment, the first and second diffusion layers are formed at respective depths proportional to the thickness and amount of the first and second bottom metal layers.

According to one embodiment, the first and second bottom metal layers comprise platinum (Pt).

According to one embodiment, the first and second bottom metal layers are formed of metal layers of different materials with different diffusion rates upon heat treatment of the substrate.

According to an embodiment, the method may further include forming a protective layer on the front surface of the substrate after forming the first and second gate electrodes, and heat treating the substrate is performed by forming the protective layer.

According to one embodiment, the method further comprises: stacking a plurality of epitaxial semiconductor layers, the Schottky barrier layer, an etch stop layer, and an ohmic layer on the substrate; Forming a first recess exposing the top surface of the Schottky barrier layer; Forming the first gate electrode including the first bottom metal layer in the first recess; Forming a second recess having the same depth as the first recess; And forming the second gate electrode including the second bottom metal layer in the second recess.

A field effect transistor according to an embodiment of the present invention, the Schottky barrier layer formed on the substrate; A first gate electrode having a first metal layer formed on the Schottky barrier layer and a first diffusion layer in which the material of the first metal layer is diffused into the Schottky barrier layer; And a second metal layer spaced apart from the first gate electrode, the second metal layer formed on the Schottky barrier layer, and a second diffusion layer in which the material of the first metal layer is diffused into the Schottky barrier layer. And a gate electrode, wherein the first diffusion layer and the second diffusion layer have different thicknesses.

According to one embodiment, the first and second metal layers are made of the same material, and the first and second metal layers are formed in different thicknesses.

According to an embodiment, the first and second metal layers include metal layers of different materials.

According to embodiments of the inventive concept, a depletion mode with different threshold voltages is formed by forming different thicknesses and amounts of bottom metal layers of gate electrodes and controlling diffusion depths of the bottom metal layers through a single heat treatment. The field effect transistor of and the field effect transistor of the increase mode can be formed on the same substrate.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention. The object (s), feature (s) and advantage (s) of the present invention will be readily understood through the following embodiments in conjunction with the accompanying drawings. The invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, like reference numerals designate like elements having the same functions.

In the present specification, when it is mentioned that a material film such as a conductive film, a semiconductor film, or an insulating film is on another material film or a substrate, any material film may be formed directly on another material film or substrate or between them. Means that another material film may be interposed therebetween. In addition, in various embodiments of the present specification, terms such as first, second, and third are used to describe various parts, materials, and the like, but these parts should not be limited by the same terms. Also, these terms are only used to distinguish one part from another part. Thus, what is referred to as the first part in one embodiment may be referred to as the second part in other embodiments. The term 'and / or' herein should be understood to refer to any or all of the configurations listed before and after this term.

1 to 7 are cross-sectional views illustrating a method of manufacturing a field effect transistor according to embodiments of the present invention.

Referring to FIG. 1, a Schottky barrier layer 106, an etch stop layer 107, and an ohmic layer 108 are sequentially formed on a substrate 100 including a plurality of epitaxial layers 105.

According to an embodiment, the substrate 100 may be an indium-phosphorus (InP) substrate. However, the substrate 100 is not limited to an indium-phosphorus (InP) substrate, and may include silicon-germanium (SiGe), silicon-carbide (SiC), gallium-arsenic (GaAs), and indium-gallium-arsenide (InGaAs). It may include using at least one of an insulating substrate such as a compound semiconductor substrate, glass, sapphire and quartz.

In addition, the materials forming the plurality of epitaxial layers 105 may be formed by combining a group III-V semiconductor material, and the number and shape may vary. For example, binary compounds may include gallium-arsenic (GaAs), indium-phosphorus (InP), aluminum-arsenic (AlAs), indium-arsenic (InAs), and indium-tin (In-Sb). Ternary compounds include aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), indium gallium phosphorus (InGaP), indium aluminum phosphorus (InAlP), and indium gallium phosphorus (InGaP). ), Indium-aluminum-arsenic (InAlAs), aluminum-gallium-nitrogen (AlGaN), indium-gallium-nitrogen (InGaN), and the like.

Hereinafter, a plurality of epitaxial layers 105 will be described. First, a buffer layer 101 is formed on the substrate 100. The buffer layer is formed of one of materials that reduces lattice mismatch between the substrate 100 and the layers formed on the substrate 100 and traps defects (eg, dislocations). Can be. Thus, the buffer layer 101 can suppress the diffusion of defects. The buffer layer 101 includes epi-grown indium-aluminum-arsenic (InAlAs), gallium-arsenic (GaAs).

A channel layer 102 is formed on the buffer layer 101. The channel layer 102 may be a semiconductor material having a uniform composition that is not doped with impurities, formed using epitaxial growth techniques. The channel layer 102 is a region in which charges (electrons) move in the field effect transistor and the HEMT device, and may include a two dimensional electron gas (2DEG) region. For example, channel layer 102 comprises epi-grown indium-gallium-arsenic (InGaAs).

Subsequently, a spacer layer 103 and a charge supply layer 104 are sequentially formed on the channel layer 102. For example, the spacer layer 103 includes indium aluminum arsenic (InAlAs) and may be formed thinner than the channel layer 102. The charge supply layer 104 may supply charge that passes through the spacer layer 103 to the channel layer 102. The charge supply layer 104 includes aluminum-gallium-arsenide (n + AlGaAs), or a silicon layer (Si pulse doping), and may be doped with n-type conductive impurities. The epitaxial layers 105 described above may be formed by a molecular beam epitaxy (MBE) method or a metal-organic chemical vapor deposition (MOCVD) method.

A Schottky Barrier layer 106 is then formed over the plurality of epitaxial layers 105. The Schottky barrier layer 106 may form a Schottky junction (junction between the semiconductor layer and the metal connecting with the semiconductor layer) needed to form transistors and semiconductor devices that require fast operating speeds. Schottky barrier layer 106 includes indium-aluminum-arsenic (InAlAs), one of the wide band gap ternary compound semiconductor materials.

An etch stop layer 107 and an ohmic layer 108 are sequentially formed on the Schottky barrier layer 106. The etch stop layer 107 includes aluminum arsenic (AlAs), and the ohmic layer 108 includes indium gallium arsenide (InGaAs) doped with n-type conductive impurities. The ohmic layer 108 may lower contact resistance by forming an ohmic contact with the source and drain electrodes.

2, the source and drain electrodes 109 may be formed on the ohmic layer 108. The source and drain electrodes 109 may be formed of a metal layer including at least one of germanium (Ge), gold (Au), and nickel (Ni) doped with conductive impurities. The source and drain electrodes 109 may be formed by depositing and patterning a metal layer by a sputtering method, an evaporation method, or a Molecular Beam Epitaxy (MBE) method. Although not shown, the source and drain electrodes 109 may be heat treated to diffuse to a depth below the Schottky barrier layer 106.

Referring to FIG. 3, a first recess having a first gate contact region 200 through which the Schottky barrier layer 106 is exposed in the first region between the source and drain electrodes 109 may be formed. The first recess may pattern the first photoresist layer 112 on the substrate 100, and may stop the ohmic layer 108 and the etch stop through an etching process using the first photoresist layer 112 as a mask. It may be formed by removing the layer 107.

The first photoresist layer 112 may be formed of a plurality of layers having high hydrophilicity and softness. For example, the first photoresist layer 112 may include a first lower photoresist layer 110 made of polymethyl methacraylate (PMMA) and a first upper photoresist layer 111 made of co-polymer. It may include a stacked structure. The first photoresist layer 112 may be patterned into a T-type resist pattern by e-beam lithography. That is, the first photoresist layer 112 may be formed of a T-type resist pattern in which the first upper photoresist layer 111 has a wider opening than the first lower photoresist layer 110.

The etching method may include a wet etching method or a dry etching method. In the wet etching method, the ohmic layer 108 and the etch stop layer 107 may be selectively etched by partially sacrificing the T-type resist layer 112 with succinic acid and hydrochloric acid (HCl) solution. Can be. Thus, the first recess may be formed in a T-shape similar to the first photoresist layer 112.

Referring to FIG. 4, a first gate electrode 130 formed of metal layers stacked from the first gate contact region 200 inside the first recess is formed.

The first gate electrode 130 sequentially stacks metal layers on the entire surface of the substrate 100, and lifts off the first photorest layer 112 to remove the first gate contact region 200. The upper portion may be formed in a T or Y shape. The first gate electrode 130 may have a fine gate length and at the same time obtain a large cross-sectional area, thereby reducing the gate resistance.

The first gate electrode 130 includes a first bottom metal layer 120a, a first bottom metal layer 121, a first middle metal layer 122, a first top metal layer 123, and a first top metal layer. A plurality of metal layers, such as 124. For example, these multiple metal layers include a structure in which platinum (Pt), molybdenum (Mo), titanium (Ti), platinum (Pt), and gold (Au) are stacked. Here, platinum, which is the first lowermost metal layer 120a, may be formed on the upper surface of the Schottky barrier layer 106 to a thickness of about 2 nm to about 5 nm. Platinum is a chemically very stable metal and has excellent electrical properties. In addition, the first lower metal layer 121 and the first middle metal layer 122 may be made of molybdenum and titanium as a barrier metal. The first top metal layer 123 and the first top metal layer 124 are made of platinum and gold.

The first gate electrode 130 has shown a plurality of metal layers having a horizontal structure for ease of explanation, but may actually appear as a structure in which a plurality of metal layers are stacked on both sides of a T or Y shape. The first gate electrode 130 may further include at least one of tungsten (W), nickel (Ni), cobalt (Co), and palladium (Pd).

The metal layers of the first gate electrode 130 may be formed by sputtering, evaporation, or molecular beam epitaxy (MBE). In addition, the first gate electrode 130 may be formed without being in electrical contact with the ohmic layer 108 in the first recess. The sputtering method can stack metal layers in a very high straightness method. Thus, the first gate electrode 130 may be formed vertically in the first gate contact region 200. In addition, the evaporation, or MBE, method uses the first lower photoresist layer 110 to flow into the first recess as the formation of the metal layers is performed at a high temperature. At the same time as coating, metal layers perpendicular to the first gate contact region 200 may be formed.

The first photoresist 112 may be lifted off by ethyl alcohol. In general, photoresists are readily soluble in highly volatile alcohol components. Therefore, the metal layers on the first photoresist 112 may be peeled off and removed on the substrate. In this case, the Schottky barrier layer 108 and the first lowermost metal layer 120a on the surface of the first gate contact region 200 are coupled with a predetermined level or more. Therefore, the first gate electrode 130 may be formed in a T shape without being removed at the lift off.

Referring to FIG. 5, a second recess is formed to expose the Schottky barrier layer 106 in the second region between the source and drain electrodes 109. Here, the second recess may be formed to the same depth as the first recess. Similarly, the second recess may be formed through the same process as the first recess.

The second recess patterns the second photoresist layer 115 on the substrate 100 and selectively removes the ohmic layer 108 and the etch stop layer 107 to form the second gate contact region 201. It can be formed by exposing.

Like the first photoresist layer 112, the second photoresist layer 115 may be formed of a plurality of layers having high hydrophilicity and softness. For example, the second photoresist layer 115 may include a structure in which the second lower photoresist layer 113 made of PMMA and the second upper photoresist layer 114 made of co-polymer are stacked. The second photoresist layer 115 is a T-type resist pattern in which the second upper photoresist layer 113 has a wider opening than the second lower photoresist layer 114 by e-beam lithography. Can be formed. Thereafter, the ohmic layer 108 and the etch stop layer 107 are removed by sacrificing the second photoresist layer 115 by a wet etching method or a dry etching method. The second recess may be formed.

Thus, the embodiment of the present invention forms the first and second recesses of the same depth using one etch stop layer 107, thereby reducing process steps compared to the prior art, resulting in process simplification and process cost. The effect of reducing the cost can also be obtained.

Referring to FIG. 6, a second gate electrode 131 is formed of a plurality of metal layers stacked from the second gate contact region 201 inside the second recess.

Like the first gate electrode 130, the second gate electrode 131 may have a T shape and be formed of the same material and the same method. The second gate electrode 131 deposits metal layers on the entire surface of the substrate 100 on which the second photoresist layer 115 is formed, and lifts off the second photoresist layer 115. Can be formed. In this case, the first and second gate electrodes 130 and 131 may be formed to have the same widths d1 and d2 and heights d3 and d4.

In this case, the second lowermost metal layer 120b of the second gate electrode 131 is made of the same material as the first lowermost metal layer 120a of the first gate electrode 130, but may be formed at different heights. . For example, the second bottom metal layer 120b is made of the same platinum as the first bottom metal layer 120a and is formed higher than the first bottom metal layer 120a. Therefore, the heights of the first and second gate electrodes 130 and 131 may be different from each other.

The second gate electrode 131 includes a second bottom metal layer 120b, a second bottom metal layer 121, a second middle metal layer 122, a second top metal layer 123, and a second top metal layer. It consists of a plurality of metal layers, including 124. In addition, although the second gate electrode 131 has a plurality of metal layers horizontally displayed only at the T- or Y-shaped bottom, a plurality of metal layers are stacked not only on the actual T- or Y-shaped bottom but also at both tops thereof. It may be formed in a shape that is. These multiple metal layers comprise at least one of platinum (Pt), molybdenum (Mo), titanium (Ti), gold (Au), tungsten (W), nickel (Ni), cobalt (Co) and palladium (Pd). Include.

As described above, the first and second lowermost metal layers 120a and 120b may be formed of the same material platinum but have different thicknesses (t1 ≠ t2). For example, the second lowermost metal layer 120b may be formed higher than the first lowermost metal layer 120a with a thickness of about 8 nm to 10 nm. According to another embodiment of the present invention, the first lowest metal layer 120a is formed to a thickness t1 of about 8 nm to 10 nm, and the second lowest metal layer 120b has a thickness of about 2 nm to 5 nm ( t2).

Referring to FIG. 7, a protective layer 116 is formed on a substrate 100 on which first and second gate electrodes 130 and 131 are formed, and the first and second lowermost metals are heated by heat treating the substrate 100. First and second diffusion layers 140 and 141 are formed under the layers 120a and 120b, respectively.

The protective layer 116 may include a silicon nitride layer (SiNx) formed by a low temperature plasma enhanced chemical vapor deposition (PECVD) method. This is to form the protective layer 116 at a low temperature, so that it is possible to control the depth of the first and second diffusion layers 140, 141 through subsequent heat treatment. In another embodiment, the heat treatment may be performed at the time of forming the protective layer 116.

The heat treatment of the substrate 100 may be performed in a temperature range of about 230 to 250 degrees Celsius in a nitrogen atmosphere. In addition, the heat treatment may be performed in-situ in the chamber forming the protective layer 116. Thus, the protective layer 116 and the first and second diffusion layers 140 and 141 are shown together in FIG. 7.

The first and second diffusion layers 140 and 141 may be formed at different depths from the top surface of the Schottky barrier layer 106 in proportion to the thicknesses of the first and second bottom metal layers 120a and 120b, respectively. . For example, when the thickness of the first lowermost metal layer 120a is smaller than the thickness of the second lowermost metal layer 120b, the thickness of the first diffusion layer 140 is smaller than the thickness of the second diffusion layer 121. Can be. First and second depths of the Schottky barrier layer 106 in proportion to the amount of platinum consisting of the first and second bottom metal layers 120a and 120b formed on the Schottky barrier layer 106. This is because the diffusion layers 140 and 141 are formed. The first and second lowermost metal layers 120a and 120b may be formed of gold (Au), tungsten (W), nickel (Ni), cobalt (Co) and palladium (Pd), for example, in addition to platinum. The first and second diffusion layers 120a and 120b may be formed to have a depth proportional to the thickness of each of the first and second lowermost metal layers 120a and 120b.

Similarly, the source / drain electrodes 109 may be formed to be more deeply diffused as they are formed in excessively large amounts compared to the first and second lowermost metal layers 120a and 120b. For example, the source / drain electrodes 109 may be formed through the Schottky barrier layer 106 up to the channel layer 102.

FIG. 8 is an enlarged view of the first and second gate electrodes and the Schottky barrier layer of FIG. 7, wherein the first and second gate electrodes 130 and 131 and the first and second diffusion layers 140 and 141 are shown. And the thickness relationship of the Schottky barrier layer 106 are disclosed in more detail.

The first and second gate electrodes 130, 131 are a plurality of metal layers 120a, 120b, 121, 122, 123, 124 stacked on the top surface of the Schottky barrier layer 106, and the Schottky barrier layer 106 includes first and second diffusion layers 140, 141 formed below the upper surface. In this case, the thickness of the Schottky barrier layer 106 formed under the first and second gate electrodes 130 and 131 is an important factor in determining the threshold voltage of the field effect transistor. In general, the threshold voltage of the field effect transistor depends on the thickness of the barrier layer connecting with the gate electrode. In other words, as the thickness of the barrier layer decreases, the threshold voltage increases toward the (+) side, and as the thickness of the barrier layer increases, the threshold voltage decreases toward the negative side. If the threshold voltage is negative The field effect transistor can be in depletion mode, and if the threshold voltage is positive The field effect transistor can be in incremental mode. Therefore, in one embodiment of the present invention, as the first and second diffusion layers 140 and 141 having different diffusion thicknesses in the depth direction from the heat treatment of the first and second lowermost metal layers 120a and 120b, the Schottky is formed. It is possible to simultaneously form transistors of depletion mode and incremental mode having different thicknesses of the barrier layer 106.

In other embodiments of the present invention, the first and second lowermost metal layers 120a and 120b may be formed of different metal layers. For example, the first lowermost metal layer 120a is formed of at least one of titanium (Ti), molybdenum (Mo), and tungsten (W) having a very slow diffusion rate during heat treatment, and the second lowermost metal layer 120b is formed. The diffusion rate may be made of at least one of platinum (Pt), gold (Au), nickel (Ni), cobalt (Co), and palladium (Pd). Therefore, the first and second diffusion layers 140 and 141 having thicknesses in different depth directions may be formed according to differences in diffusion speeds.

The thicknesses t3 and t4 of the first and second diffusion layers 140 and 141 are different from each other (t1 ≠ t2) by varying the deposition thicknesses of the first and second lowermost metal layers 120a and 120b (t1 ≠ t2). It can be formed to have t4).

According to one embodiment, when the thickness t1 of the first bottom metal layer 120a is smaller than the thickness t2 of the second bottom metal layer 120b (t1 <t2), the first diffusion layer 140 may be formed. The thickness t3 may be smaller than the thickness t4 of the second diffusion layer 141 (t3 <t4). Therefore, the thickness t5 of the Schottky barrier layer 106a under the first diffusion layer 140 may be greater than the thickness t6 of the Schottky barrier layer 106b under the second diffusion layer 141. (T5> t6). The first gate electrode 130 has a function of a depletion mode field effect transistor having a threshold voltage having a negative polarity, and the second gate electrode 131 has an increase mode field effect transistor having a positive voltage having a positive polarity. It can have a function of.

Therefore, the method of manufacturing a field effect transistor according to the embodiments of the present invention may simultaneously form the depletion mode and the increase mode field effect transistor through a single heat treatment process. Those skilled in the art will be able to easily implement these modified embodiments based on the technical spirit of the present invention described above.

1 to 7 are process cross-sectional views illustrating a method of manufacturing a field effect transistor according to embodiments of the present invention.

FIG. 8 is an enlarged view of the first and second gate electrodes and the Schottky barrier layer of FIG. 7; FIG.

Claims (10)

Forming a Schottky barrier layer on the substrate; Forming a first gate electrode comprising a first bottom metal layer on the Schottky barrier layer; Forming a second gate electrode on the Schottky barrier layer, the second gate electrode spaced apart from the first gate electrode and comprising a second bottom metal layer; And Heat-treating the substrate to form a first diffusion layer and a second diffusion layer in which materials of the first bottom metal layer and the second bottom metal layer are respectively diffused into the Schottky barrier layer; And the first diffusion layer and the second diffusion layer have different depths from the upper surface of the schottky barrier layer to the inside. The method of claim 1, And the first and second bottom metal layers have different thicknesses. The method of claim 2, Wherein the first and second diffusion layers are formed at respective depths proportional to the thickness and amount of the first and second bottom metal layers. The method of claim 3, wherein And the first and second bottom metal layers comprise platinum (Pt). The method of claim 1, The first and second bottom metal layers are formed of metal layers of different materials having different diffusion rates during heat treatment of the substrate. The method of claim 1, And forming a protective layer on the front surface of the substrate after forming the first and second gate electrodes, and heat treating the substrate is performed by forming the protective layer. Manufacturing method. The method of claim 1, Depositing a plurality of epitaxial semiconductor layers, the Schottky barrier layer, an etch stop layer, and an ohmic layer on the substrate; Forming a first recess exposing the top surface of the Schottky barrier layer; Forming the first gate electrode including the first bottom metal layer in the first recess; Forming a second recess having the same depth as the first recess; And Forming the second gate electrode comprising the second bottom metal layer in the second recess. A Schottky barrier layer formed on the substrate; A first gate electrode having a first metal layer formed on the Schottky barrier layer and a first diffusion layer in which the material of the first metal layer is diffused into the Schottky barrier layer; And A second gate spaced apart from the first gate electrode and having a second metal layer formed on the Schottky barrier layer and a second diffusion layer in which the material of the second metal layer is diffused into the Schottky barrier layer Including electrodes, And the first diffusion layer and the second diffusion layer have different thicknesses. 9. The method of claim 8, And the first and second metal layers are made of the same material, and the first and second metal layers have different thicknesses. 9. The method of claim 8, And the first and second metal layers comprise metal layers of different materials.

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