CN111477547A - Enhanced power device and manufacturing method thereof - Google Patents
Enhanced power device and manufacturing method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The application provides an enhanced power device and a manufacturing method thereof, and relates to the technical field of semiconductors. Firstly, providing a substrate, then manufacturing an epitaxial layer along one side of the substrate, wherein the epitaxial layer comprises a high-resistance P-type doped layer, activating a target region of the high-resistance P-type doped layer, removing the high-resistance P-type doped layer of a source region and a drain region, finally manufacturing a gate electrode in the target region, and manufacturing a source electrode and a drain electrode in the source region and the drain region. The enhancement type power device and the manufacturing method thereof have the advantages of simpler manufacturing process and higher manufacturability and reliability of the device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an enhanced power device and a manufacturing method thereof.
Background
Because gallium nitride (GaN) materials have a large forbidden bandwidth, power semiconductor devices based on GaN materials can have higher breakdown voltage and higher power density than traditional silicon (Si) -based power devices; and by utilizing the inherent polarization characteristic of the GaN material, a two-dimensional electron gas channel with high concentration and high electron mobility can be formed, so that the switching frequency of the silicon-based power device can be higher than that of the traditional silicon-based power device. An AlGaN/GaN high mobility transistor (HEMT) having a planar structure, which is manufactured based on high withstand voltage and high frequency characteristics of GaN, has a wide application demand in the high voltage and high frequency fields.
At present, for the manufacture of HEMT devices, the patterning of a p-type gate is usually formed by adopting an ion etching method, however, because a p-GaN or p-AlGaN layer and an AlGaN layer under a gate electrode lack selective etching, the thickness and uniformity of etching are difficult to accurately control, so that the starting voltage and the on-resistance of the device on the whole wafer are not uniform, the repeatability is poor, and the damage of the etching surface is easily caused, thereby affecting the switching performance of the device. Therefore, the manufacturing requirement for the HEMT device is higher at present.
In summary, the problem of high manufacturing requirements exists in the manufacturing process of the HEMT device at present.
Disclosure of Invention
The application aims at providing an enhancement type semiconductor device manufacturing method, which comprises the following steps:
providing a substrate;
manufacturing an epitaxial layer along one side of the substrate, wherein the epitaxial layer comprises a high-resistance P-type doped layer;
activating a target region of the high-resistance P-type doped layer;
removing the high-resistance P-type doped layer of the source region and the drain region;
and manufacturing a gate electrode in the target area, and manufacturing a source electrode and a drain electrode in the source area and the drain area.
Further, the step of fabricating an epitaxial layer along one side of the substrate comprises:
manufacturing a barrier layer along one side of the substrate;
manufacturing a heterojunction layer along one side of the barrier layer far away from the substrate;
and growing a high-resistance P-type doped layer along one side of the heterojunction layer far away from the substrate under the atmosphere containing H.
Further, the step of growing the high-resistance P-type doped layer along the side of the heterojunction layer far away from the substrate under the H-containing atmosphere comprises the following steps:
at H2And/or NH3And growing a high-resistance P-type doping layer along one side of the heterojunction layer, which is far away from the substrate, in the atmosphere.
Further, the step of activating the target region of the high-resistance P-type doped layer includes:
depositing a mask layer along one side of the high-resistance P-type doped layer far away from the substrate;
removing part of the mask layer to expose a target region of the high-resistance P-type doping layer;
and activating the target region of the high-resistance P-type doped layer.
Further, the step of activating the target region of the high-resistance P-type doped layer includes:
activating the target area by annealing, electron beam or laser.
Further, after the step of activating the target region of the high-resistance P-type doped layer, the method further includes:
and removing all the mask layer.
Further, before the step of removing the high resistance P-type doped layer of the source region and the drain region, the method further comprises:
and removing all or part of the unactivated high-resistance P-type doped layer.
In another aspect, the present application provides an enhancement mode semiconductor device, which is manufactured by the above enhancement mode semiconductor device manufacturing method, and the enhancement mode semiconductor device includes:
a substrate;
a barrier layer and a heterojunction layer connected to the substrate;
the P-type doping layer is connected with the heterojunction layer and is positioned in the target region;
and the source electrode and the drain electrode are connected with the heterojunction layer.
Furthermore, the enhancement semiconductor device further comprises a high-resistance P-type doped layer, the high-resistance P-type doped layer is connected with the heterojunction layer, and the height of the high-resistance P-type doped layer is smaller than or equal to that of the P-type doped layer in the target region.
Furthermore, the barrier layer is made of materials including GaN, AlGaN and AlN.
Compared with the prior art, the method has the following beneficial effects:
the application provides an enhanced power device and a manufacturing method thereof, and the enhanced power device comprises the steps of firstly providing a substrate, then manufacturing an epitaxial layer along one side of the substrate, wherein the epitaxial layer comprises a high-resistance P-type doped layer, activating a target region of the high-resistance P-type doped layer, removing the high-resistance P-type doped layer of a source region and a drain region, finally manufacturing a gate electrode in the target region, and manufacturing a source electrode and a drain electrode in the source region and the drain region. Because the mode that the target region is selected to be activated in the high-resistance P-type doping layer is adopted, the traditional etching process is not needed, the manufacturing process is simpler, the surface damage of the device caused by etching can not occur, and the manufacturability and the reliability of the device are improved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is an exemplary flowchart of a method for manufacturing an enhanced power device according to an embodiment of the present disclosure.
Fig. 2 is an exemplary flowchart of the sub-step of S104 in fig. 1 provided in an embodiment of the present application.
Fig. 3 is a schematic partial structural diagram of an enhancement-mode power device according to an embodiment of the present application.
Fig. 4 is an exemplary flowchart of the sub-step of S106 in fig. 1 provided in an embodiment of the present application.
Fig. 5 is a schematic structural diagram of an enhancement mode power device provided in the present application when a mask layer is fabricated.
Fig. 6 is a schematic structural diagram of patterning a mask layer according to an embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram of activating a target area according to an embodiment of the present application.
Fig. 8 is a schematic structural diagram of an enhanced power device according to an embodiment of the present application.
In the figure: 110-a substrate; 120-barrier layer; 130-a heterojunction layer; 140-high resistance P-type doped layer; 150-a mask layer; 160-gate region.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The turning on of the HEMT device relies on a high concentration of two-dimensional electron gas at the interface of adjacent nitride layers to control the turning off of the device by controlling the gate bias. A typical HEMT device is based on an AlGaN/GaN heterojunction structure, and when the gate is biased to zero, the device is turned on, and when the gate is biased negatively, the device can be turned off, which means that when the gate is powered off, the device loses control, causing leakage or short circuit, which causes serious safety problems in practical applications. Such HEMT devices, which are gate biased to turn off, are commonly referred to as normally-on or depletion mode devices. For an ideal power switch, it is desirable that the device be off at zero gate bias and the gate be positively biased to turn it on. Power devices of this structure are referred to as enhancement or normally-off devices. Realizing the normally-off state of the device is one of the core problems of the research of the GaN HEMT power device. The mainstream enhancement mode GaN HEMT device structure adopts a p-type grid (p-GaN or p-AlGaN) manufactured on an AlGaN/GaN heterojunction to exhaust two-dimensional electron gas of an AlGaN/GaN interface, so that the device is normally turned off.
However, as described in the background art, currently, for the fabrication of HEMT devices, the patterning of the p-type gate is usually formed by an ion etching method, however, because the p-GaN or p-AlGaN layer and the AlGaN layer under the gate electrode lack selective etching, it is difficult to precisely control the thickness and uniformity of etching, which results in non-uniform on-state voltage and on-state resistance of the device on the whole wafer, and also has poor repeatability, and easily causes damage to the etching surface, which affects the switching performance of the device. Therefore, the manufacturing requirement for the HEMT device is higher at present.
In view of this, in order to reduce the manufacturing requirement and improve the reliability of the manufactured HEMT device, the application provides a new method for manufacturing an enhancement power device, so that the manufacturing process is simpler, the repeatability is higher and the uniformity is higher by using a mode of selective region activation on the high-resistance P-type doped layer.
Referring to fig. 1, as an alternative implementation, a method for manufacturing an enhanced power device provided in the present application is exemplarily described below, and the method for manufacturing an enhanced power device provided in the present application includes:
s102, providing a substrate.
S104, manufacturing an epitaxial layer along one side of the substrate, wherein the epitaxial layer comprises a high-resistance P-type doped layer.
And S106, activating the target region of the high-resistance P-type doped layer.
And S108, removing the high-resistance P-type doped layers of the source region and the drain region.
S110, a gate electrode is manufactured in the target area, and a source electrode and a drain electrode are manufactured in the source area and the drain area.
The high-resistance P-type doped layer refers to a P-type doped layer with high resistance, that is, the hole activity in the high-resistance P-type doped layer is low.
Meanwhile, when the high-resistance P-type doping layer is activated, only part of the target area is activated, and then the gate electrode is manufactured on the target area, so that the manufacturing of the enhancement type HEMT device is realized. For example, only the middle region of the high-resistance P-type doped layer is activated, and the other regions are not activated, so that the target region is activated and the other regions are still high-resistance regions on the high-resistance P-type doped layer.
It should be noted that, the activation in this application refers to activating holes in the high-resistance P-type doped layer, so that the target region is activated to be of a hole conduction type.
It can be understood that, since the present application adopts steps different from those of the conventional process, the gate electrode can be directly fabricated after the target region in the P-type doped layer is activated without etching, thereby avoiding the etching damage to the surface and the accurate control of the etching rate by the dry etching in the conventional process, and making the fabrication process simpler, highly repeatable and more uniform.
Referring to fig. 2 and 3, S104 includes:
s1041, manufacturing a barrier layer along one side of the substrate.
S1042, manufacturing a heterojunction layer along one side of the barrier layer far away from the substrate.
S1043, growing a high-resistance P-type doped layer along one side of the heterojunction layer far away from the substrate in the atmosphere containing H.
Among them, the barrier layer 120 material may be GaN, AlGaN, AlN, etc. among group iii nitride semiconductor materials. On this basis, a homogeneous substrate may be used, and a heterogeneous substrate may also be employed. The homogeneous substrate, i.e., the substrate 110, is made of the same material as the barrier layer 120, for example, when the material of the barrier layer is GaN, the substrate 110 is a GaN substrate; when the material of the barrier layer is AlN, the substrate 110 is an AlN substrate.
Alternatively, the barrier layer 120 may be fabricated on the substrate 110 by using methods such as molecular beam epitaxy or metal-organic vapor phase epitaxy. Meanwhile, when the heterojunction is formed on the barrier layer 120, the heterojunction may be formed by molecular beam epitaxy or metal-organic vapor phase epitaxy. The heterojunction is a heterojunction structure with two-dimensional electron gas, and may be a heterojunction structure such as AlGaN/GaN or AlInN/GaN, for example, which is not limited in this application.
After the heterojunction layer 130 is fabricated, a high-resistance P-type doped layer may be epitaxially grown on the heterojunction layer 130, wherein the process of growing the high-resistance P-type doped layer 140 may also be a molecular beam epitaxy or a metal organic vapor phase epitaxy.
In addition, the P-type doped layer is grown along the surface of the heterojunction layer 130 in an atmosphere containing H, and since the Mg atoms and the H atoms are combined and passivated, that is, holes at the periphery of the Mg atoms are combined with electrons provided by hydrogen atoms, in the P-type doped layer, the holes are of a non-conductive type, so that the resistance of the manufactured P-type doped layer is high, and the high-resistance P-type doped layer 140 is formed.
Wherein, the H-containing atmosphere described in the present application refers to the atmosphere containing H2And/or NH3Under an atmosphere, in other words, it may be a single H2Atmosphere, may be a single NH3Atmosphere, may be H2And NH3And (4) mixing the atmosphere. Under this atmosphere, the high-resistance P-type doped layer 140 can be grown along the side of the heterojunction layer 130 away from the substrate 110.
Meanwhile, as an alternative implementation manner of the present application, please refer to fig. 4-7, where S106 includes:
and S1061, depositing a mask layer along the side of the high-resistance P-type doped layer far away from the substrate 110.
And S1062, removing partial region in the mask layer to expose the target region of the high-resistance P-type doped layer.
And S1063, activating the target region of the high-resistance P-type doped layer.
As an alternative implementation, the present application uses a mask layer 150 to achieve activation of the target region, wherein the mask layer 150 is deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition), L PCVD (L ow Pressure Chemical Vapor Deposition), and the like, the material of the mask layer 150 includes, but is not limited to SiNx、SiO2And the like.
When the high-resistance P-type doped layer 140 is grown, Mg atoms and H atoms in the P-type doped layer are substantially bonded to form Mg — H complex groups, and thus a high-resistance state is achieved. Further, the Mg — H complex group is easily decomposed at a high temperature (generally, more than 450 °), and is activated. Therefore, the deposition temperature of the present application is less than 450 ℃ when the step of depositing the mask layer 150 is performed.
After the mask layer 150 is deposited, the mask layer 150 may be patterned by photolithography, dry/wet etching, or the like. That is, the mask layer of the gate region 160 is removed to expose the surface of the high-resistance P-type doped layer 140 of the gate region 160.
After the patterning process, the high resistance P-type doped layer 140 of the gate region 160 may be activated. It will be appreciated that the activation described herein, i.e., the decomposition of the Mg-H recombination groups, causes the gate region 160 to be activated to the hole conductivity type.
As an alternative implementation, the present application activates the gate region 160 by annealing, electron beam, or laser, so as to activate the holes in the portion of the gate region 160 in the high resistance P-type doped layer 140. Since the regions other than the gate region 160 are blocked by the mask after the patterning process, the regions other than the gate region 160 cannot be activated and still maintain the high resistance state when the activation is performed.
After activating the p-type doped layer of the gate region 160, a dry or wet etching process may be used to remove all of the mask layer 150. At this time, the p-type doped layer includes two portions, one portion is a gate region 160, and holes in the region are activated. The other part is the region outside the gate region 160, and holes in the region are not activated and still present a high resistance state.
Then, the source region and the drain region in the high-resistance P-type doped layer 140 are removed until the heterojunction layer 130 is exposed, and then electrodes are respectively formed on the gate region 160, the source region and the drain region to form a gate electrode, a source electrode and a drain electrode.
As an optional implementation manner of the present application, before the step of removing the high resistance P-type doped layer 140 of the source region and the drain region, the method further includes:
and S107, removing all or part of the unactivated high-resistance P-type doped layer.
In the present application, after activating the P-type doped layer of the gate region 160, there are three processing methods for other non-activated regions:
first, the inactive high-resistance P-type doped layer 140 is not treated and remains. Since it is a high resistance region, it does not affect the normal operation of the device.
Secondly, the inactive high-resistance P-type doped layer 140 is removed, and the high-resistance P-type doped layer 140 is not completely removed, at this time, the thickness of the inactive high-resistance P-type doped layer 140 is smaller than that of the P-type doped layer of the gate region.
Third, the inactive high-resistance P-type doped layer 140 is removed, and the high-resistance P-type doped layer 140 is completely removed. Meanwhile, if the inactive high-resistance P-type doped layer 140 is completely removed, the subsequent step of removing the high-resistance P-type doped layer 140 of the source region and the drain region is not required.
Of course, the foregoing implementation manner is only one implementation manner of the present application, and the present application can also be implemented in other manners, for example, after the P-type doped layer is manufactured, a masking manner is adopted to perform passivation on other regions except the gate region 160, so that the other portions except the gate region 160 are the high-resistance P-type doped layer, and then the source region and the drain region are processed, so that the effects of the present application can also be achieved.
According to the manufacturing method of the enhanced power device, the P-type doped layer is not required to be etched, so that the manufacturing process is simple, the repeatability is high, the uniformity is high, and the enhanced power device manufactured by the method has the advantages of uniform threshold voltage and high reliability.
On the basis of the above embodiments, please refer to fig. 8, the present application further provides an enhanced semiconductor device, which is prepared by the above enhanced semiconductor device manufacturing method. The enhancement mode semiconductor device includes:
the semiconductor device includes a substrate 110, a barrier layer 120 and a heterojunction layer 130 connected to the substrate 110, a P-type doped layer connected to the heterojunction layer 130 and located in a target region, a gate electrode connected to the P-type doped layer in the target region, and source and drain electrodes connected to the heterojunction layer 130.
As an optional implementation manner, the enhancement-mode semiconductor device further includes a high-resistance P-type doped layer 140, the high-resistance P-type doped layer 140 is connected to the heterojunction layer 130, and the height of the high-resistance P-type doped layer 140 is less than or equal to the height of the P-type doped layer in the target region.
Optionally, the material for manufacturing the barrier layer 120 includes GaN, AlGaN, and AlN, and the substrate 110 may be a substrate that is the same as or different from the barrier layer 120, which is not limited in this application.
In summary, the present application provides an enhanced power device and a method for fabricating the same, which includes providing a substrate, fabricating an epitaxial layer along one side of the substrate, wherein the epitaxial layer includes a high-resistance P-type doped layer, activating a target region of the high-resistance P-type doped layer, removing the high-resistance P-type doped layer of a source region and a drain region, fabricating a gate electrode in the target region, and fabricating a source electrode and a drain electrode in the source region and the drain region. Because the mode that the target region is selected to be activated in the high-resistance P-type doping layer is adopted, the traditional etching process is not needed, the manufacturing process is simpler, the surface damage of the device caused by etching can not occur, and the manufacturability and the reliability of the device are improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A method for manufacturing an enhanced semiconductor device, the method comprising:
providing a substrate;
manufacturing an epitaxial layer along one side of the substrate, wherein the epitaxial layer comprises a high-resistance P-type doped layer;
activating a target region of the high-resistance P-type doped layer;
removing the high-resistance P-type doped layer of the source region and the drain region;
and manufacturing a gate electrode in the target area, and manufacturing a source electrode and a drain electrode in the source area and the drain area.
2. The method of fabricating an enhancement mode semiconductor device according to claim 1, wherein said step of fabricating an epitaxial layer along a side of said substrate comprises:
manufacturing a barrier layer along one side of the substrate;
manufacturing a heterojunction layer along one side of the barrier layer far away from the substrate;
and growing a high-resistance P-type doped layer along one side of the heterojunction layer far away from the substrate under the atmosphere containing H.
3. The method for manufacturing an enhancement mode semiconductor device according to claim 2, wherein the step of growing the high-resistance P-type doped layer along the side of the heterojunction layer away from the substrate in the H-containing atmosphere comprises the steps of:
at H2And/or NH3And growing a high-resistance P-type doping layer along one side of the heterojunction layer, which is far away from the substrate, in the atmosphere.
4. The method of claim 1, wherein activating the target region of the high resistance P-type doped layer comprises:
depositing a mask layer along one side of the high-resistance P-type doped layer far away from the substrate;
removing part of the mask layer to expose a target region of the high-resistance P-type doping layer;
and activating the target region of the high-resistance P-type doped layer.
5. The method for fabricating an enhancement mode semiconductor device according to claim 4, wherein the step of activating the target region of the high resistance P-type doped layer comprises:
activating the target area by annealing, electron beam or laser.
6. The method of fabricating an enhancement mode semiconductor device according to claim 4, wherein after said step of activating a target region of said high resistance P-type doped layer, said method further comprises:
and removing all the mask layer.
7. The method of fabricating an enhancement mode semiconductor device according to claim 1, wherein prior to the step of removing the high resistance P-type doped layer of the source and drain regions, the method further comprises:
and removing all or part of the unactivated high-resistance P-type doped layer.
8. An enhancement-mode semiconductor device manufactured by the enhancement-mode semiconductor device manufacturing method according to any one of claims 1 to 7, the enhancement-mode semiconductor device comprising:
a substrate;
a barrier layer and a heterojunction layer connected to the substrate;
the P-type doping layer is connected with the heterojunction layer and is positioned in the target region;
and the source electrode and the drain electrode are connected with the heterojunction layer.
9. The enhancement-mode semiconductor device according to claim 8, further comprising a high-resistance P-type doped layer connected to the heterojunction layer, wherein the height of the high-resistance P-type doped layer is less than or equal to the height of the P-type doped layer in the target region.
10. The enhancement-mode semiconductor device of claim 8, wherein the barrier layer is fabricated from a material comprising GaN, AlGaN, and AlN.
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