JP5504427B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a semiconductor field effect transistor having a Schottky junction and an ohmic junction, and more particularly to a compound semiconductor field effect transistor.

A compound semiconductor such as GaAs has a higher electron mobility than a single element semiconductor such as Si, and thus is suitable as a material for a transistor for high-speed operation. However, even if the surface of the compound semiconductor is oxidized, a gate oxide film having a high withstand voltage corresponding to SiO ₂ in the case of Si cannot be obtained. For this reason, in order to use a compound semiconductor as a field effect transistor (FET), a Schottky junction is used for the gate. In the Schottky junction, a metal such as Pt (platinum) is diffused from a gate electrode on the surface of a compound semiconductor such as GaAs, and a gate voltage is transmitted to the metal diffusion layer. Schottky junctions are used for changing the gate voltage to increase or decrease channel carriers, that is, for field effect. Therefore, the current flowing through the Schottky junction is an unnecessary gate leakage current, and it is important that no large current flows through the Schottky junction. On the other hand, an ohmic junction with as little contact resistance as possible is required between the source / drain electrodes of the FET and the semiconductor layer. For this reason, a metal such as an AuGe alloy is used for the source / drain electrodes, and an ohmic junction is formed by diffusing a part of this metal into the compound semiconductor layer. An electronic device using a metal-semiconductor Schottky junction as a gate electrode is called a MESFET (Metal Semiconductor Field Effect Transistor). In general, MESFETs are used in compound semiconductors (GaAs, InP, SiC, etc.), exhibit higher performance than silicon MOSFETs (Metal Oxide Field Effect Transistors), and are used in various RF elements.

  FIG. 1 shows a cross section of a compound semiconductor MESFET having a conventional structure. A buffer layer 12 formed on the semiconductor substrate 11, a Schottky layer 13 formed on the buffer layer 12, and an n-type contact layer 14 provided on the Schottky layer 13. An opening is provided in part, a gate electrode 15 is formed in the opening, a drain electrode 16 and a source electrode 17 are formed in part of the upper portion of the n-type contact layer 14, and at least n An insulating film 18 is formed on the type contact layer 14 and on the region where the drain electrode 16 or the source electrode 17 is not formed.

  As a transistor aiming at high-speed operation, a high electron mobility transistor (HEMT) having a structure in which an electron supply layer for supplying carriers and a channel layer are separated from each other, that is, a HEMT (High Electron Mobility Transistor) is used. For example, a non-doped GaAs layer not doped with impurities is used as a channel layer, and a semiconductor having a wider band gap than the channel layer, such as n-type AlGaAs, is provided as an electron supply layer in close contact with the channel layer. Have. Since the channel in which carriers flow is formed on the non-doped side, high mobility can be obtained because free carriers are not scattered by fixed charges existing in the electron supply layer. For this reason, there is little noise and high-speed operation of electrons is possible.

  Furthermore, as a transistor aiming at higher speed operation, a pHEMT (pseudo lattice matching HEMT) having a structure using InGaAs having a narrow band gap as a channel layer and AlGaAs having a wide band gap as an electron supply layer or a Schottky layer is also used. Further, mHEMT (metamorphic HEMT) having a structure using InGaAs as a channel layer and InAlAs as an electron supply layer or a Schottky layer is also used.

  Structural features common to compound semiconductor FETs, such as MESFET, HEMT, pHEMT, mHEMT, etc. listed above, are Schottky junctions between metal and semiconductor for gate formation, and metal and semiconductor for source / drain formation. It is the point which utilizes the ohmic junction between. Generally, an n-type contact layer made of a compound semiconductor is provided in a portion where the source / drain electrodes of these compound semiconductor FETs are formed. This is to realize a good ohmic junction with a small contact resistance between the metal electrode and the compound semiconductor. Specifically, after forming a Schottky layer using MOCVD or molecular beam epitaxy (MBE) technology, an n-type compound semiconductor layer is formed epitaxially by aligning the crystal lattice on the Schottky layer. The n-type semiconductor layer is, for example, GaAs in the case of MESFET, HEMT, and pHEMT, and is, for example, InGaAs in the case of mHEMT.

  By the way, an insulating film is formed above the gate electrode and contact layer of the compound semiconductor FET in order to insulate the metal wiring layer and gate electrode provided on the upper part, and to block air, moisture, etc. penetrating from outside the device or from the package. Is provided. Specifically, after a contact layer, source / drain electrodes, a gate electrode, and the like are formed, an insulating film such as silicon nitride (SiN) or SiO 2 is formed using a plasma CVD method.

Japanese Patent No. 3141935 JP 9-36393 A

  FIG. 2 is an enlarged view of FIG. 1 for explaining the problems of the conventional compound semiconductor FET. A buffer layer 12 formed on the semiconductor substrate 11, a Schottky layer 13 formed on the buffer layer 12, and an n-type contact layer 14 provided on the Schottky layer 13. An opening is provided in part, a gate electrode 15 is formed in the opening, a drain electrode 16 is formed in a part of the upper part of the n-type contact layer 14, and at least the n-type contact layer 14. An insulating film 18 is formed on the region above which the drain electrode 16 is not formed.

In FIG. 2, for the sake of explanation, the cross section of the region from the gate electrode 15 to the drain electrode 16 is drawn by enlarging FIG. 1, but the same applies to the source electrode side. In the conventional compound semiconductor FET, due to the interface charge 19 existing at the interface between the n-type compound semiconductor contact layer 14 provided to realize the ohmic junction of the source / drain electrodes and the insulating film provided thereon. There is a problem that the depletion layer 20 is formed in the n-type contact layer. The interface charge 19 is, for example, trapped electrons at the interface state existing at the interface between the n-type contact layer 14 made of GaAs or InAlAs and the insulating film 18 such as SiN provided thereon, and negative charges are accumulated. It has been done. The density of interface states is, for example, about 1 × 10 ¹¹ cm ⁻² per unit area of the contact layer. The upper portion of the n-type contact layer 14 is depleted due to the negative charges resulting from the interface states, and the portion that becomes a current path is narrowed to the extent indicated by d in FIG. The n-type contact layer 14 has a thickness of 10 nm, for example, but may be d = 5 nm as a result of being constricted by the interface charge. As a result, the resistance value with respect to the lateral current of the contact layer increases, and there is a disadvantage that the cutoff frequency Ft of the FET is lowered and the mutual conductance gm is lowered. Further, it is difficult to uniformly form the interface state density or the interface charge density at various locations within the wafer surface, which causes variations in FET electrical characteristics within the wafer surface. Further, the interface charge density fluctuates every day depending on the state of the plasma CVD apparatus for forming the SiN film and the subsequent manufacturing process steps, and there is a problem that the transistor characteristics cannot be made uniform among the manufacturing lots.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a field effect transistor having a large cutoff frequency Ft and mutual conductance gm and uniform electrical characteristics.

In order to achieve the above object, the present invention provides a buffer layer formed in contact with the upper surface of a semiconductor substrate, a Schottky layer formed on the buffer layer, A contact layer provided in contact with the upper surface of the Schottky layer, an opening is provided in a part of the contact layer, a gate electrode in contact with the Schottky layer in the opening, and a part of an upper part of the contact layer A field effect transistor comprising: a source electrode and a drain electrode formed on the substrate; and an insulating film formed on at least the contact layer and a region where the source electrode or the drain electrode is not formed. layers, viewed contains an upper layer of doped lower layer and a non-doped n-type impurity, is in contact with said insulating film and an upper layer of the top surface of the non-doped And wherein the door.

  According to a second aspect of the present invention, in the first aspect of the present invention, a channel layer is provided between the buffer layer and the Schottky layer.

  According to a third aspect of the present invention, in the second aspect of the present invention, the channel layer is formed of a compound semiconductor having a narrower band gap than the Schottky layer, and at least a part of the Schottky layer. Is n-doped and the channel layer is non-doped.

  The invention according to claim 4 is the invention according to claim 3, wherein the semiconductor substrate is GaAs, the channel layer is InGaAs, and the Schottky layer is InAlAs.

As described above, the contact layer of the field effect transistor according to the present invention, viewed contains an upper layer of doped lower layer and a non-doped n-type impurity, the upper layer of the top surface of the undoped and the insulating film are in contact . Thus, due to the depletion of the contact layer upper by negative charges due to the interface state between the contact layer and the insulating film, nonuniformity of the narrowing of the portion to be the path of the current proof technique, in wafer surface charge density And the influence on the electrical characteristics of the FET caused by variations between manufacturing lots can be reduced .

It is sectional drawing for demonstrating the conventional compound semiconductor FET. It is sectional drawing for demonstrating the problem of the conventional compound semiconductor FET. It is sectional drawing for demonstrating the field effect transistor by the 1st Embodiment of this invention. It is sectional drawing for demonstrating the effect of this invention. It is sectional drawing for demonstrating the field effect transistor by the 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 3 is a cross-sectional view for explaining the first embodiment of the present invention. The buffer layer 32 formed on the semiconductor substrate 31, the Schottky layer 33 formed on the buffer layer 32, the n-type contact layer 34b provided on the Schottky layer 33, and the n-type contact layer 34b The non-doped contact layer 34a is provided, an opening is provided in a part of the non-doped contact layer 34a and the n-type contact layer 34b, and a gate electrode 35 is formed in the opening, and the non-doped contact layer 34a A drain electrode 36 and a source electrode 37 are formed on part of the upper surface, and an insulating film 38 is formed at least on the non-doped contact layer 34a and on the region where the drain electrode 36 or the source electrode 37 is not formed. Has been.

In the practice of the present invention, a non-doped GaAs buffer layer 32 having a thickness of 3 μm is first provided on a semi-insulating GaAs substrate 31 by MOCVD. Next, a Schottky layer 33 having a film thickness of 0.3 μm is formed epitaxially on the buffer layer 32 by MOCVD. The Schottky layer is AlGaAs slightly doped n-type with Si, and the Si dose is 5 × 10 ¹⁶ cm ⁻³ . Further, an n-type contact layer 34b having a thickness of 10 nm is provided by MOCVD. The n-type contact layer is made of GaAs that is strongly n-type doped with Si, and the dose is preferably 1 × 10 ¹⁸ cm ⁻³ or more. Next, a non-doped contact layer 34a having a thickness of 10 nm is provided epitaxially by MOCVD. The non-doped contact layer is made of GaAs like the n-type contact layer and does not contain the dopant Si. This can be realized by adding Si during the growth of 10 nm in the first half and not adding Si during the growth of 10 nm in the second half when forming the GaAs contact layer by MOCVD. The n-type contact layer 34b and the non-doped contact layer 34a are the same compound semiconductor material, and it is important that there are no crystal defects due to lattice mismatch. There is no interface state at the interface between the n-type contact layer 34b and the non-doped contact layer 34a.

  Next, a photoresist is opened only in a region where the source and drain electrodes are to be formed using a known lithography technique. As a metal to be a source / drain electrode, a Ge / Au / Ni three-layer metal film is formed by vacuum deposition. Thereafter, an unnecessary metal film deposited on the resist is removed by using a lift-off method, thereby forming a source electrode 37 and a drain electrode 36 on a part of the non-doped contact layer.

  Next, a gate electrode 35 is formed between the source electrode 37 and the drain electrode 36. A part of the non-doped contact layer 34a and the n-type contact 34b layer is removed only in the gate formation region by using a known lithography / etching technique, and the Schottky layer 33 is exposed. Specifically, lithography is performed by applying, exposing, and developing a photoresist. The resist opening in the Schottky layer exposed region is, for example, a slit having a width of 0.7 μm. Etching is performed by wet etching using a citric acid-based etchant to expose the AlGaAs surface by utilizing the etching selectivity between GaAs as a contact layer material and AlGaAs as a Schottky layer. The metal used for the gate electrode 35 has three layers of Pt / Ti / Au and is formed by vacuum deposition and a lift-off method.

  After forming the source electrode 37, the drain electrode 36, and the gate electrode 35, Pt of the gate electrode 35 is diffused into the Schottky layer 33 by annealing at 300 ° C. for 90 seconds to form a Schottky junction, and at the same time, the source electrode 37, the drain electrode 36 Au, Ni and Ge are diffused to the non-doped contact layer 34a and the n-type contact layer 34b to form an ohmic junction of the source and drain. The non-doped contact layer 34a is insulative at the time of film formation, but has a low resistance due to diffusion of metallic Au, Ni, and Ge.

  Next, a SiN (silicon nitride) thin film having a film thickness of 0.3 μm is formed as the insulating film 38 by plasma CVD using ammonia and monosilane gas as raw materials. The plasma CVD method is performed at a pressure of 75 Pa, an RF frequency of 400 kHz, and an RF power of 200 W. The refractive index of the SiN film is 1.9. Thereafter, a wiring layer, a passivation film (SiN), and a bonding pad portion opening are sequentially performed.

  According to the above process, an interface state is generated at the interface between the SiN film 38 formed by the plasma CVD method and the non-doped contact layer 34a, but between the n-type contact layer 34b that is a current path. Since the non-doped contact layer 34a having a thickness of 10 nm exists, the interface charge can be prevented from affecting the current path.

  FIG. 4 is a cross-sectional view for explaining the effect of the present invention, and is an enlarged view of FIG. The buffer layer 32 formed on the semiconductor substrate 31, the Schottky layer 33 formed on the buffer layer 32, the n-type contact layer 34b provided on the Schottky layer 33, and the n-type contact layer 34b The non-doped contact layer 34a is provided, an opening is provided in a part of the non-doped contact layer 34a and the n-type contact layer 34b, and a gate electrode 35 is formed in the opening, and the non-doped contact layer 34a A drain electrode 36 is formed on a part of the upper surface, and an insulating film 38 is formed at least on the non-doped contact layer 34a and on the region where the drain electrode 36 is not formed.

  The field effect transistor according to the present invention includes a lower n-type contact layer 34b in which a contact layer 34 for forming a source / drain electrode is doped with an n-type impurity and an upper non-doped contact layer 34a. The non-doped layer 34 a is in contact with the interface in contact with the insulating film 38. There is a possibility that an interface charge 39 is accumulated at the interface between the insulating film 38 and the non-doped contact layer 34a. However, the interface charge 39 is located sufficiently away from the n-type contact layer 34b, which is a current path. For this reason, the influence of the interface charge on the n-type contact layer 34b is extremely small, and the problem that a part of the contact layer is depleted and the current path is narrowed like the conventional FET is solved. In addition, since the interfacial charge density non-uniformity within the wafer and the variation between manufacturing lots have little influence on the FET electrical characteristics, a uniform FET can be provided.

(Second Embodiment)
FIG. 5 is a cross-sectional view for explaining a second embodiment of the present invention. A buffer layer 52 formed on the semiconductor substrate 51, a barrier layer 53 formed on the buffer layer 52, a first delta doped layer 54 formed on the barrier layer 53, and a first delta doped layer 54 A channel layer 55 formed on the channel layer 55, a second delta doped layer 56 formed on the channel layer 55, a Schottky layer 57 formed on the second delta doped layer 56, and the Schottky layer 57 The n-type contact layer 58b provided on the n-type contact layer 58b and the non-doped contact layer 58a provided on the n-type contact layer 58b are provided, and openings are provided in part of the non-doped contact layer 58a and the n-type contact layer 58b. A gate electrode 61 is formed in the opening, and a drain electrode 59 and a source electrode 62 are formed on part of the non-doped contact layer 58a. Made are provided, on the areas not on the and drain electrode 59 or the source electrode 62 of at least the non-doped contact layer 58a is formed, an insulating film 60 is formed.

In the second embodiment of the present invention, the growth of each compound semiconductor thin film is performed by the molecular beam epitaxy (MBE) method. First, an In _X Al _1-X As buffer layer 52 having a film thickness of 1.5 μm is provided on a semi-insulating GaAs substrate 51 by MBE. The In composition X in the buffer layer 52 is formed so that the composition ratio is gradually changed so that X = 0 at the lowermost portion in contact with the GaAs substrate and X = 0.5 at the uppermost portion in contact with the barrier layer 53.

Next, an In _0.4 Al _0.6 As barrier 53 layer having a thickness of 400 nm is epitaxially grown. At this time, a part of the barrier layer 53 is provided with an n-type first delta doped layer 54 of Si so as to have a dopant concentration of 2 × 10 ¹² cm ⁻² .

Next, a non-doped In _0.4 Ga _0.6 As channel layer 55 having a thickness of 20 nm is epitaxially grown.

Next, an In _0.4 Al _0.6 As Schottky layer 57 having a thickness of 25 nm is grown epitaxially. At this time, a part of the Schottky layer 57 is provided with an n-type second delta doped layer 56 of Si so as to have a dopant concentration of 5 × 10 ¹² cm ⁻² .

Since In _0.4 Ga _0.6 As of the channel layer 55 has a narrow band gap compared to In _0.4 Al _0.6 As of the Schottky layer 57, free electrons are generated from the first and second delta doped layers. The non-doped channel layer 55 is supplied.

Next, an n-type contact layer 58b having a thickness of 10 nm and a non-doped contact layer 58a are sequentially grown epitaxially. The n-type contact layer is made of In _0.4 Ga _0.6 As that is strongly n-type doped with Si, and the dose amount is desirably 5 × 10 ¹⁸ cm ⁻³ or more. The non-doped contact layer is In _0.4 Ga _0.6 As, similar to the n-type contact layer, but does not contain the dopant Si. This can be realized by adding Si during the first 10 nm growth and not adding Si during the second 10 nm growth when depositing the In _0.4 Ga _0.6 As contact layer by MBE. . The n-type contact layer 58b and the non-doped contact layer 58a are the same compound semiconductor material, and it is important that there are no crystal defects due to lattice mismatch. There is no interface state at the interface between the n-type contact layer 58b and the non-doped contact layer 58a.

  Next, a photoresist is opened only in a region where the source and drain electrodes are to be formed using a known lithography technique. As a metal to be a source / drain electrode, a three-layered Au / Ge / Au metal film is formed by vacuum deposition. Thereafter, an unnecessary metal film deposited on the resist is removed using a lift-off method, thereby forming a source electrode 62 and a drain electrode 59 on a part of the non-doped contact layer.

Next, the gate electrode 61 is formed between the source electrode 62 and the drain electrode 59. A part of the non-doped contact layer and the n-type dopant contact layer is removed only in the gate formation region using a known lithography / etching technique, and the Schottky layer 57 is exposed. Specifically, lithography is performed by applying, exposing, and developing a photoresist. The resist opening in the exposed area of the Schottky layer is, for example, a slit having a width of 0.5 μm. Etching is performed by wet etching using a mixture of citric acid: hydrogen peroxide water: ammonia water: water, and In _0.4 Ga _0.6 As which is a material of the contact layer and In _0.4 Al _0. which is a Schottky layer _{. The} surface of In _0.4 Al _0.6 As is exposed using the etching selectivity of ₆ As. The metal used for the gate electrode 61 has three layers of Pt / Ti / Au and is formed by vacuum deposition and a lift-off method.

  After forming the source electrode 62, the drain electrode 59, and the gate electrode 61, Pt of the gate electrode 61 is diffused into the Schottky layer 57 by annealing at 290 ° C. for 90 seconds to form a Schottky junction, and at the same time, the source electrode 62, the drain electrode 59 Au and Ge are diffused to the non-doped contact layer 58a and the n-type contact layer 58b to form an ohmic junction of the source and drain. The non-doped contact layer 58a is insulative at the time of film formation, but has a low resistance due to diffusion of metallic Au and Ge.

  Next, a SiN (silicon nitride) thin film having a film thickness of 0.3 μm is formed as the insulating film 60 by plasma CVD using ammonia and monosilane gas as raw materials. The plasma CVD method is performed at a pressure of 75 Pa, an RF frequency of 400 kHz, and an RF power of 200 W. The refractive index of the SiN film is 1.9. Thereafter, a wiring layer, a passivation film (SiN), and a bonding pad portion opening are sequentially performed.

  According to the above process, an interface state is generated at the interface between the SiN film 60 formed by the plasma CVD method and the non-doped contact layer 58a, but between the n-type contact layer 58b which is a current path. Since the non-doped contact layer 58a having a thickness of 10 nm exists, the interface charge can be prevented from affecting the current path.

11, 31, 51 Semiconductor substrate 12, 32, 52 Buffer layer 13, 33, 57 Schottky layer 34a, 58a Non-doped contact layer 14, 34b, 58b N-type contact layer 15, 35, 61 Gate electrode 16, 36, 59 Drain electrode 17, 37, 62 Source electrodes 18, 38, 60 Insulating film 19, 39 Interface charge 20 Depletion layer 53 Barrier layer 54 First delta doped layer 55 Channel layer 56 Second delta doped layer

Claims (5)

A buffer layer formed in contact with the upper surface of the semiconductor substrate; a Schottky layer formed on the buffer layer; a contact layer provided in contact with the upper surface of the Schottky layer; and a part of the contact layer An opening is provided, a gate electrode in contact with the Schottky layer in the opening, a source electrode and a drain electrode formed on a part of the contact layer, and at least above the contact layer and a source electrode or drain A field effect transistor including an insulating film formed on a region where no electrode is formed,
The contact layer is viewed contains a doped lower layer and the undoped upper layer of n-type impurity, field effect transistor, characterized in that said insulating film and an upper layer of the top surface of the non-doped is in contact.   2. The field effect transistor according to claim 1, further comprising a channel layer between the buffer layer and the Schottky layer.   The channel layer is formed of a compound semiconductor having a narrow band gap compared to the Schottky layer, at least a part of the Schottky layer is doped n-type, and the channel layer is non-doped. The field effect transistor according to claim 2.   4. The field effect transistor according to claim 3, wherein the semiconductor substrate is GaAs, the channel layer is InGaAs, and the Schottky layer is InAlAs. The field effect transistor according to any one of claims 1 to 4, wherein the source electrode and the drain electrode are formed so as to penetrate through the non-doped upper layer and to contact the doped lower layer.

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