CN213716906U - Gallium nitride semiconductor device - Google Patents
Gallium nitride semiconductor device Download PDFInfo
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- CN213716906U CN213716906U CN202022638462.XU CN202022638462U CN213716906U CN 213716906 U CN213716906 U CN 213716906U CN 202022638462 U CN202022638462 U CN 202022638462U CN 213716906 U CN213716906 U CN 213716906U
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Abstract
The utility model provides a gallium nitride semiconductor device, which comprises a gallium nitride epitaxial wafer, a source electrode, a grid electrode and a drain electrode, and also comprises a first dielectric layer, an ohmic metal layer, a second dielectric layer, a third dielectric layer and a grid electrode metal contact part which are sequentially formed on the gallium nitride epitaxial wafer; the ohmic metal layer comprises a source ohmic contact part and a drain ohmic contact part, the source sequentially penetrates through the third dielectric layer and the second dielectric layer and then is connected with the source ohmic contact part, the drain sequentially penetrates through the third dielectric layer and the second dielectric layer and then is connected with the drain ohmic contact part, and the grid is connected with the grid metal contact part; the gallium nitride epitaxial wafer comprises a barrier layer and a cap layer, wherein the source electrode ohmic contact part and the drain electrode ohmic contact part both extend downwards to the barrier layer, and the grid electrode metal contact part extends downwards to the cap layer. The ohm metal of the gallium nitride semiconductor device can be protected additionally in the process of etching the grid metal, so that the difficulty of the grid metal etching process is reduced.
Description
Technical Field
The utility model belongs to the technical field of the semiconductor technology and specifically relates to a gallium nitride semiconductor device is related to.
Background
The gallium nitride semiconductor device has a very wide application prospect in the field of power amplification, and in the manufacturing process of the gallium nitride semiconductor device, the etching of grid metal can damage nearby ohmic metal, especially in the over-etching process. Over-etching is an essential step in dry etching, and can ensure that the etched film is sufficiently removed. However, in certain cases, over-etching can damage underlying structures. Generally, the risk of damage to the underlying structure is reduced by increasing the etch selectivity and reducing the amount of over-etching. However, high-selectivity etching has certain challenges and certain limitations, and reducing the amount of over-etching increases the risk of the etched film remaining.
Disclosure of Invention
The utility model aims at providing a can obtain extra protection at the ohm metal of grid metal sculpture in-process ohm metal, reduce the gallium nitride semiconductor device of the grid metal sculpture technology degree of difficulty.
In order to achieve the above object, the present invention provides a gallium nitride semiconductor device, which comprises a gallium nitride epitaxial wafer, and a source electrode, a gate electrode, and a drain electrode on the gallium nitride epitaxial wafer; the gallium nitride semiconductor device also comprises a first dielectric layer, an ohmic metal layer, a second dielectric layer, a third dielectric layer and a grid metal contact part which are sequentially formed on the gallium nitride epitaxial wafer; the ohmic metal layer comprises a source ohmic contact part and a drain ohmic contact part, the source sequentially penetrates through the third dielectric layer and the second dielectric layer and then is connected with the source ohmic contact part, the drain sequentially penetrates through the third dielectric layer and the second dielectric layer and then is connected with the drain ohmic contact part, and the grid is connected with the grid metal contact part; the gallium nitride epitaxial wafer comprises a barrier layer and a cap layer, wherein the cap layer is positioned above the barrier layer, the source electrode ohmic contact part and the drain electrode ohmic contact part both extend downwards to the barrier layer, and the gate metal contact part extends downwards to the cap layer.
In a preferred embodiment, the gallium nitride epitaxial wafer further comprises a substrate, and a transition layer and a channel layer sequentially formed on the substrate, wherein the barrier layer is formed above the channel layer.
In a preferred embodiment, the material of the first dielectric layer is one or a combination of two or more of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide.
In a preferred embodiment, the material of the second dielectric layer is one or a combination of two or more of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide.
In a preferred embodiment, the material of the third dielectric layer is one or a combination of two or more of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide.
Preferably, the thickness of the first dielectric layer is in the range of 5 microns to 500 microns.
Preferably, the ohmic metal layer is made of Ti/Al/Ti/TiN alloy, the gate metal contact is made of TiN/Al/TiN alloy, and the source electrode, the gate electrode and the drain electrode are made of Ti/Al/TiN alloy.
The beneficial effects of the utility model are that, through deposit the second dielectric layer in advance on lower floor ohm metal layer for the ohm metal layer obtains extra protection in grid metal sculpture in-process, reduces the grid metal sculpture technology degree of difficulty, will protect the top of ohm metal layer through second dielectric layer and third dielectric layer simultaneously together, makes the selection of the thickness of third dielectric layer have higher flexibility.
Drawings
Fig. 1 is a schematic structural diagram of a gallium nitride epitaxial wafer according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an embodiment of the gallium nitride semiconductor device according to the present invention after depositing a first dielectric layer on a gallium nitride epitaxial wafer.
Fig. 3 is a schematic diagram of the gallium nitride semiconductor device according to the present invention after forming the ohmic contact hole.
Fig. 4 is a schematic diagram of the gallium nitride semiconductor device according to the present invention after depositing an ohmic metal layer.
Fig. 5 is a schematic diagram of an embodiment of the gan semiconductor device according to the present invention after depositing a second dielectric layer.
Fig. 6 is a schematic diagram of the gallium nitride semiconductor device according to the present invention after etching the second dielectric layer and the ohmic metal layer.
Fig. 7 is a schematic diagram of an embodiment of a gallium nitride semiconductor device according to the present invention after deposition of a third dielectric layer.
Fig. 8 is a schematic diagram of an embodiment of a gallium nitride semiconductor device according to the present invention after a gate metal via is formed on a third dielectric layer.
Fig. 9 is a schematic diagram of the gallium nitride semiconductor device according to the present invention after depositing a gate metal layer.
Fig. 10 is a schematic diagram of the gallium nitride semiconductor device according to the present invention after etching the gate metal layer.
Fig. 11 is a schematic diagram of an embodiment of a gallium nitride semiconductor device according to the present invention after depositing a fourth dielectric layer.
Fig. 12 is a schematic view of the gallium nitride semiconductor device according to the present invention after forming contact holes for electrodes.
Fig. 13 is a schematic diagram of the gallium nitride semiconductor device according to the present invention after depositing an electrode metal layer.
Fig. 14 is a schematic diagram of a gallium nitride semiconductor device according to an embodiment of the present invention after patterning an electrode metal layer.
The present invention will be further explained with reference to the drawings and examples.
Detailed Description
Referring to fig. 1 and 14, the gallium nitride semiconductor device includes a gallium nitride epitaxial wafer 1, and a source electrode 2, a gate electrode 3, and a drain electrode 4 on the gallium nitride epitaxial wafer 1, the gate electrode 3 being located between the source electrode 2 and the drain electrode 4 in a lateral direction, the gallium nitride epitaxial wafer 1 including a substrate 11, and a transition layer 12, a channel layer 13, a barrier layer 14, and a cap layer 15 sequentially formed on the substrate 11.
The gallium nitride semiconductor device further comprises a first dielectric layer 5, an ohmic metal layer 6, a second dielectric layer 7, a third dielectric layer 8, a gate metal contact portion 31 and a fourth dielectric layer 9 which are sequentially formed on the gallium nitride epitaxial wafer 1. The ohmic metal layer 6 comprises a source ohmic contact part 21 and a drain ohmic contact part 41, the source electrode 2 sequentially penetrates through the fourth dielectric layer 9, the third dielectric layer 8 and the second dielectric layer 7 and then is connected with the source ohmic contact part 21, the drain electrode 4 sequentially penetrates through the fourth dielectric layer 9, the third dielectric layer 8 and the second dielectric layer 7 and then is connected with the drain ohmic contact part 41, and the grid electrode 3 sequentially penetrates through the fourth dielectric layer 9 and then is connected with the grid electrode metal contact part 31. The source ohmic contact 21 and the drain ohmic contact 41 each extend down to the barrier layer 14, and the gate metal contact 31 extends down to the cap layer 15.
The substrate 11 is made of silicon, silicon carbide or sapphire, the channel layer 13 is made of gallium nitride, and the barrier layer 14 is made of aluminum gallium nitride. The first dielectric layer 5, the second dielectric layer 7, the third dielectric layer 8 and the fourth dielectric layer 9 are made of one or a combination of more than two of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide. The materials of the second dielectric layer 7 and the third dielectric layer 8 may be the same or different. The thickness of the first dielectric layer 5 is in the range of 5 to 500 microns. The ohmic metal layer 6, the gate metal contact 31, the source electrode 2, the gate electrode 3 and the drain electrode 4 are all metal alloys formed by multilayer metal deposition, the material of the ohmic metal layer 6 is Ti/Al/Ti/TiN alloy, the material of the gate metal contact 31 is TiN/Al/TiN alloy, and the material of the source electrode 2, the gate electrode 3 and the drain electrode 4 is Ti/Al/TiN alloy.
Referring to fig. 1 to 14, a method of manufacturing a gallium nitride semiconductor device includes the following steps.
First, a gallium nitride epitaxial wafer 1 as shown in fig. 1 was prepared.
Next, a first dielectric layer 5 as shown in fig. 2 is deposited on the gallium nitride epitaxial wafer 1 by using a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD).
Next, an ohmic contact hole 51 as shown in fig. 3 is opened on the first dielectric layer 5 by using a semiconductor photolithography technique and an etching technique, and the ohmic contact hole 51 extends downward to the barrier layer 14. The photoetching technology comprises the steps of glue homogenizing, soft baking, exposure, development, film hardening and the like.
Next, as shown in fig. 4, an ohmic metal layer 6 is formed on the first dielectric layer 5 and in the ohmic contact hole 51 by depositing a plurality of metal layers, and the plurality of metal layers are deposited in the order of Ti, Al, Ti, and TiN to form a Ti/Al/Ti/TiN alloy.
Next, as shown in fig. 5, a second dielectric layer 7 is formed by deposition over the ohmic metal layer 6.
Next, the second dielectric layer 7 and the ohmic metal layer 6 are etched, and the ohmic metal layer 6 that is not removed forms a source ohmic contact 21 and a drain ohmic contact 41 as shown in fig. 6.
Next, as shown in fig. 7, a third dielectric layer 8 is formed by deposition over the second dielectric layer 7 and over the exposed first dielectric layer 5.
Next, as shown in fig. 8, a gate metal via 81 is formed on the third dielectric layer 8, and the gate metal via 81 penetrates through the third dielectric layer 8 and the first dielectric layer 5 and extends downward to the cap layer 15.
Next, a gate metal layer 30 as shown in FIG. 9 is formed by multilayer metal deposition, and the multilayer metal is deposited in the order of TiN, Al, TiN to form a TiN/Al/TiN alloy.
Next, the gate metal layer 30 is etched, and the portions that are not removed form gate metal contacts 31 as shown in fig. 10.
Next, as shown in fig. 11, a fourth dielectric layer 9 is formed by deposition over the gate metal layer 30 and the third dielectric layer 8.
Next, as shown in fig. 12, a source contact hole 91, a gate contact hole 92 and a drain contact hole 93 are formed in the fourth dielectric layer 9, the source contact hole 91 sequentially penetrates through the fourth dielectric layer 9, the third dielectric layer 8 and the second dielectric layer 7 and extends downward to the source ohmic contact portion 21, the gate contact hole 92 penetrates through the fourth dielectric layer 9 and extends downward to the gate metal contact portion 31, and the drain contact hole 93 sequentially penetrates through the fourth dielectric layer 9, the third dielectric layer 8 and the second dielectric layer 7 and extends downward to the drain ohmic contact portion 41.
Next, as shown in fig. 13, an electrode metal layer 90 is formed above the fourth dielectric layer 9 and in the source contact hole 91, the gate contact hole 92 and the drain contact hole 93 by multilayer metal deposition, and the multilayer metal is deposited in the order of Ti, Al and TiN to form a Ti/Al/TiN alloy.
Finally, the electrode metal layer 90 is patterned by using a semiconductor photolithography technique and an etching technique to form a source electrode 2, a gate electrode 3, and a drain electrode 4 as shown in fig. 14, the source electrode 2 being connected to the source ohmic contact 21, the gate electrode 3 being connected to the gate metal contact 31, and the drain electrode 4 being connected to the drain ohmic contact 41.
Therefore, the third dielectric layer is used for protecting the bottom material, particularly the top of the ohmic metal layer, when metal is etched, the second dielectric layer is deposited on the lower ohmic metal layer in advance, so that the ohmic metal layer is protected additionally in the etching process of the grid metal, the difficulty of the etching process of the grid metal is reduced, and meanwhile, the second dielectric layer and the third dielectric layer protect the top of the ohmic metal layer together, so that the selection of the thickness of the third dielectric layer has higher flexibility.
Finally, it should be emphasized that the above-described preferred embodiments of the present invention are merely examples of implementations, and are not intended to limit the scope of the present invention, as those skilled in the art will appreciate that various changes and modifications may be made without departing from the spirit and scope of the invention, and it is intended to cover all such modifications, equivalents, and improvements as fall within the true spirit and scope of the invention.
Claims (7)
1. The gallium nitride semiconductor device is characterized by comprising a gallium nitride epitaxial wafer, and a source electrode, a grid electrode and a drain electrode which are positioned on the gallium nitride epitaxial wafer;
the gallium nitride semiconductor device also comprises a first dielectric layer, an ohmic metal layer, a second dielectric layer, a third dielectric layer and a grid metal contact part which are sequentially formed on the gallium nitride epitaxial wafer;
the ohmic metal layer comprises a source ohmic contact part and a drain ohmic contact part, the source sequentially penetrates through the third dielectric layer and the second dielectric layer and then is connected with the source ohmic contact part, the drain sequentially penetrates through the third dielectric layer and the second dielectric layer and then is connected with the drain ohmic contact part, and the grid is connected with the grid metal contact part;
the gallium nitride epitaxial wafer comprises a barrier layer and a cap layer, wherein the cap layer is positioned above the barrier layer, the source electrode ohmic contact part and the drain electrode ohmic contact part both extend downwards to the barrier layer, and the gate metal contact part extends downwards to the cap layer.
2. The gallium nitride semiconductor device according to claim 1, wherein:
the gallium nitride epitaxial wafer further comprises a substrate, and a transition layer and a channel layer which are sequentially formed on the substrate, wherein the barrier layer is formed above the channel layer.
3. The gallium nitride semiconductor device according to claim 1, wherein:
the first dielectric layer is made of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.
4. The gallium nitride semiconductor device according to any one of claims 1 to 3, wherein:
the second dielectric layer is made of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.
5. The gallium nitride semiconductor device according to any one of claims 1 to 3, wherein:
the third dielectric layer is made of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.
6. The gallium nitride semiconductor device according to any one of claims 1 to 3, wherein:
the thickness of the first dielectric layer is in the range of 5 microns to 500 microns.
7. The gallium nitride semiconductor device according to any one of claims 1 to 3, wherein:
the ohmic metal layer is made of Ti/Al/Ti/TiN alloy, the grid metal contact part is made of TiN/Al/TiN alloy, and the source electrode, the grid electrode and the drain electrode are made of Ti/Al/TiN alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022638462.XU CN213716906U (en) | 2020-11-13 | 2020-11-13 | Gallium nitride semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022638462.XU CN213716906U (en) | 2020-11-13 | 2020-11-13 | Gallium nitride semiconductor device |
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| CN213716906U true CN213716906U (en) | 2021-07-16 |
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| CN202022638462.XU Active CN213716906U (en) | 2020-11-13 | 2020-11-13 | Gallium nitride semiconductor device |
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Denomination of utility model: Gallium nitride semiconductor device Effective date of registration: 20230504 Granted publication date: 20210716 Pledgee: Guangfa Bank Co.,Ltd. Zhuhai Yinhua Branch Pledgor: INNOSCIENCE (ZHUHAI) TECHNOLOGY Co.,Ltd. Registration number: Y2023980039776 |