CN114759089A - P-type gallium nitride device for enhancing grid control capability and manufacturing method thereof - Google Patents
P-type gallium nitride device for enhancing grid control capability and manufacturing method thereof Download PDFInfo
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- CN114759089A CN114759089A CN202210421280.8A CN202210421280A CN114759089A CN 114759089 A CN114759089 A CN 114759089A CN 202210421280 A CN202210421280 A CN 202210421280A CN 114759089 A CN114759089 A CN 114759089A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 111
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 90
- 230000002708 enhancing effect Effects 0.000 title abstract description 4
- 238000004519 manufacturing process Methods 0.000 title description 7
- 238000005530 etching Methods 0.000 claims abstract description 66
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 229910052759 nickel Inorganic materials 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
The invention discloses a p-type gallium nitride device for enhancing grid control capability, which comprises: the substrate sequentially comprises a gallium nitride layer, an aluminum gallium nitride layer and a P-type gallium nitride layer from bottom to top, the surface of the substrate comprises a source region, a drain region opposite to the source region and a gate region positioned between the source region and the drain region, the gate region comprises a first etching region and second etching regions extending outwards from two sides of the first etching region, the first etching region partially etches the P-type gallium nitride layer inwards to form a first groove, and the second etching region completely etches the P-type gallium nitride layer inwards to form a second groove; a source electrode; a drain electrode; a dielectric layer; a gate electrode; the contact electrode is positioned in the second groove, one end of the contact electrode is contacted with the surface of the gallium nitride layer, and the other end of the contact electrode is contacted with the bottom of the grid electrode; the contact electrode can be in contact with the two-dimensional electron gas on the surface of the gallium nitride layer, and the hole in the P-type gallium nitride layer is controlled by controlling the two-dimensional electron gas, so that the control capability of the grid electrode is improved.
Description
Technical Field
The invention relates to a p-type gallium nitride device for enhancing grid control capability and a manufacturing method thereof, belonging to the technical field of semiconductor devices.
Background
P-type gallium nitride devices are hole-conducting using materials in P-type gallium nitride. At present, the existing enhancement type P-type gallium nitride device is obtained by using a gate groove structure or a plasma passivation structure, holes in a channel can be controlled only through a gate, and the control capability of the gate is weak. And because the substrate of the P-type channel gallium nitride device sequentially comprises the gallium nitride layer, the aluminum gallium nitride layer and the P-type gallium nitride layer from bottom to top, when the P-type gallium nitride layer is etched above the gallium nitride layer and the aluminum gallium nitride layer, the inhibited or consumed two-dimensional electron gas can be partially recovered again, and the recovered electrons can further influence the control capability of the grid.
Disclosure of Invention
The invention aims to provide a P-type gallium nitride device with enhanced grid control capability and a manufacturing method thereof, which can solve the problem that the traditional implementation method of the enhanced P-type gallium nitride device can only control holes in a channel through a grid, so that the control capability of the grid is not high.
In order to achieve the purpose, the invention provides the following technical scheme:
a p-type gallium nitride device with enhanced gating capabilities, comprising:
the substrate sequentially comprises a gallium nitride layer, an aluminum gallium nitride layer and a P-type gallium nitride layer from bottom to top, the surface of the substrate comprises a source region, a drain region opposite to the source region and a gate region positioned between the source region and the drain region, the gate region comprises a first etching region and second etching regions extending outwards from two sides of the first etching region, the first etching region internally and partially etches the P-type gallium nitride layer to form a first groove, and the second etching region inwards and completely etches the P-type gallium nitride layer to form a second groove;
the source electrode is positioned at the source electrode area;
the drain electrode is positioned at the drain region;
the dielectric layer is positioned on the surface of the p-type gallium nitride layer between the source electrode and the drain electrode;
a gate electrode positioned in the first and second recesses and above the dielectric layer;
and the contact electrode is positioned in the second groove, one end of the contact electrode is in surface contact with the gallium nitride layer, and the other end of the contact electrode is in bottom contact with the grid.
Furthermore, the extending direction of the first etching region and the second etching region is a first direction, the extending direction of the source region and the drain region is a second direction, and the first direction is perpendicular to the second direction.
Further, the p-type gallium nitride device further comprises a two-dimensional electron gas layer, the two-dimensional electron gas layer is located between the gallium nitride layer and the aluminum gallium nitride layer, and the contact electrode is in contact with the two-dimensional electron gas layer.
Further, the thickness of the P-type gallium nitride layer below the first etching area is 15-40 nm.
Further, the dielectric layer is an aluminum oxide layer.
A method for fabricating a p-type gallium nitride device with enhanced gate control capability, the method being used for fabricating the above p-type gallium nitride device, the method comprising:
s1, carrying out mesa isolation on the substrate to form an active region; the active region comprises a source region, a drain region opposite to the source region and a gate region positioned between the source region and the drain region, the gate region comprises a first etching region and a second etching region extending outwards from two sides of the first etching region, and the substrate sequentially comprises a gallium nitride layer, an aluminum gallium nitride layer and a P-type gallium nitride layer from bottom to top;
s2, partially etching the P-type gallium nitride layer below the first etching area by using an etching method;
s3, completely etching the P-type gallium nitride layer below the second etching area by using the etching method to form a contact electrode to-be-formed area;
s4, forming a source electrode on the source region, forming a drain electrode on the drain region, and forming a contact electrode on the contact electrode to-be-formed region;
s5, forming a dielectric layer on the surface of the p-type gallium nitride layer between the surface of the contact electrode and the source electrode and the drain electrode;
s6, completely etching the dielectric layer above the contact electrode by using the etching method;
and S7, forming a gate on the gate region.
Further, the etching method comprises wet etching and/or dry etching.
Further, in step S4, a high work function metal and a non-oxidizable metal are deposited by using electron beam evaporation and/or magnetron sputtering to form the source and the drain.
Further, in step S4, a low work function metal is deposited using electron beam evaporation and/or magnetron sputtering to form the gate electrode.
Further, in step S5, a dielectric layer is formed using a chemical vapor deposition method.
The invention has the beneficial effects that: the P-type gallium nitride device with the enhanced grid control capability is provided, wherein the contact electrode is positioned in the second groove, one end of the contact electrode is in contact with the surface of the gallium nitride layer, the other end of the contact electrode is in contact with the bottom of the grid, so that the contact electrode can be in contact with two-dimensional electron gas on the surface of the gallium nitride layer, and holes in the P-type gallium nitride layer are controlled by controlling the two-dimensional electron gas, so that the control capability of the grid is enhanced.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is a front view of a p-type gallium nitride device of the present application;
FIG. 2 is a top view of a p-type gallium nitride device;
FIG. 3 is a cross-sectional view of a p-type gallium nitride device;
fig. 4 is a flow chart of a method of fabricating a p-type gallium nitride device.
100-P type gallium nitride device, 1-substrate, 11-gallium nitride layer, 12-aluminum gallium nitride layer, 13-P type gallium nitride layer, 14-source region, 15-drain region, 16-gate region, 161-first etching region, 162-second etching region, 2-source electrode, 3-drain electrode, 4-dielectric layer, 5-gate electrode, 6-contact electrode and 7-two-dimensional electronic gas layer.
Detailed Description
The following detailed description of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
The following detailed description of embodiments of the present application will be described in conjunction with the accompanying drawings and examples. The following examples are intended to illustrate the present application, but are not intended to limit the scope of the present application.
In the description of the present application, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present application and to simplify the description, but are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and thus are not to be construed as limiting the scope of the present application. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the creation of the present application, the meaning of "a plurality" is two or more unless otherwise stated.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art through specific situations.
Referring to fig. 1 to 3, a preferred embodiment of the present application provides a p-type gan device 100 with enhanced gate control capability, comprising: substrate 1, source electrode 2, drain electrode 3, dielectric layer 4, gate electrode 5 and contact electrode 6. The substrate 1 comprises a gallium nitride layer 11 (such as a GaN layer in the figure), an aluminum gallium nitride layer 12 (such as an AlGaN layer in the figure) and a P-type gallium nitride layer 13 (such as a P-GaN layer in the figure) from bottom to top in sequence. It should be noted that the structure and the manufacturing method of the substrate 1 are prior art, and are not described in detail in this application. The surface of the substrate 1 comprises a source region 14, a drain region 15 opposite to the source region 14, and a gate region 16 located between the source region 14 and the drain region 15, wherein the gate region 16 comprises a first etching region 161 and second etching regions 162 extending outwards from two sides of the first etching region 161, the first etching region 161 partially etches the P-type gallium nitride layer 13 inwards to form a first groove (not numbered), and the second etching region 162 completely etches the P-type gallium nitride layer 13 inwards to form a second groove (not numbered). The source 2 is located in the source region 14. The drain 3 is located at the drain region 15. The dielectric layer 4 is positioned on the surface of the p-type gallium nitride layer 13 between the source electrode 2 and the drain electrode 3. The gate 5 is located in the first and second recesses and over the dielectric layer 4. The contact electrode 6 is positioned in the second groove, one end of the contact electrode 6 is in contact with the surface of the gallium nitride layer 11, and the other end of the contact electrode is in contact with the bottom of the grid 5.
In this embodiment, the first groove and the second groove are formed by etching. The etching method may be wet etching or dry etching. Of course, in other embodiments, the first groove and the second groove may be implemented in other manners, and the formation manner of the first groove and the second groove is not limited in this application.
Since the first groove is formed by partially etching the P-type gallium nitride layer 13, the remaining P-type gallium nitride layer 13 is also included under the first etching region 161. In the present embodiment, the thickness of the P-type gallium nitride layer 13 under the first etched region 161 is in the range of 15-40 nm.
The extending direction of the first and second etching regions 161 and 162 is a first direction (a direction), the extending direction of the source and drain regions 14 and 15 is a second direction (b direction), and the first and second directions are perpendicular.
The p-type gallium nitride device 100 further comprises a two-dimensional electron gas layer 7, the two-dimensional electron gas layer 7 is located between the gallium nitride layer 11 and the aluminum gallium nitride layer 12, and the contact electrode 6 is in contact with the two-dimensional electron gas layer 7.
Optionally, the dielectric layer 4 is an insulating layer. In the present embodiment, the dielectric layer 4 is an aluminum oxide layer. Of course, in other embodiments, the dielectric layer 4 may also be an oxide layer or a nitride layer, and the material of the dielectric layer is not limited in this application.
When the P-type gallium nitride layer 13 above the gallium nitride layer 11 and the aluminum gallium nitride layer 12 is etched, the two-dimensional electron gas that is suppressed or consumed may partially recover again, and the recovered two-dimensional electron gas is in a floating state, which may further affect the control capability of the gate 5, so in this embodiment, the two-dimensional electron gas in the two-dimensional electron gas layer 7 is connected to the gate 5 through the two contact electrodes 6, so that the two-dimensional electron gas may also affect the hole, thereby improving the control capability of the gate 5.
Fig. 4 is a flow chart of a method for fabricating a p-type gan device with enhanced gate control capability according to the present application, which is used for fabricating the above-mentioned p-type gan device. The method specifically comprises the following steps: s1, carrying out mesa isolation on the substrate to form an active region; the active region comprises a source region, a drain region opposite to the source region and a gate region positioned between the source region and the drain region, the gate region comprises a first etching region and a second etching region extending outwards from two sides of the first etching region, and the substrate sequentially comprises a gallium nitride layer, an aluminum gallium nitride layer and a P-type gallium nitride layer from bottom to top; s2, partially etching the P-type gallium nitride layer below the first etching area by using an etching method; s3, completely etching the P-type gallium nitride layer below the second etching area by using an etching method to form a contact electrode to-be-formed area; s4, forming a source electrode in the source region, forming a drain electrode in the drain region, and forming a contact electrode in the contact electrode to-be-formed region; s5, forming a dielectric layer on the surface of the contact electrode and the surface of the p-type gallium nitride layer between the source electrode and the drain electrode; s6, completely etching the dielectric layer above the contact electrode by using an etching method; and S7, forming a gate on the gate region.
Wherein the etching method comprises wet etching and/or dry etching.
In step S4, the method for forming the source and the drain includes: and depositing high work function metal and metal which is not easy to oxidize by using an electron beam evaporation method and/or a magnetron sputtering method to form a source electrode and a drain electrode. Alternatively, the high work function metal may be nickel and the non-oxidizable metal may be gold, palladium, platinum, silver, etc., and thus the combination of the high work function metal and the non-oxidizable metal may be nickel/gold, nickel/palladium, nickel/platinum, nickel/silver, etc.
After the deposition of the high work function metal and the metal not easy to be oxidized, the metal combination is annealed in an oxygen or inert gas environment for 10-600s at 100-700 ℃ to form the final source and drain.
In step S4, the method of forming the contact electrode is specifically: and depositing a low work function metal by using an electron beam evaporation method and/or a magnetron sputtering method to form a contact electrode, wherein the contact electrode is positioned on the surface of the aluminum gallium nitride layer.
Optionally, after forming the contact electrode on the surface of the aluminum gallium nitride layer, the method further includes: annealing the low work function metal in an inert gas environment for 10-600s at 100-700 ℃ to form a final contact electrode, wherein the contact electrode extends from the surface of the aluminum gallium nitride layer to the surface of the gallium nitride layer through high-temperature annealing and is in contact with two-dimensional electron gas.
In step S5, the method for forming the dielectric layer includes: the dielectric layer is formed using a chemical vapor deposition process. Here, the chemical vapor deposition method may be performed by various apparatuses to form the dielectric layer. Such as: ALD equipment or PEALD equipment or PECVD equipment or LPCVD equipment or ICPCVD equipment or MOCVD equipment and the like.
In summary, the application provides a P-type gallium nitride device with enhanced gate control capability and a manufacturing method thereof, wherein the contact electrode is located in the second groove, one end of the contact electrode is in contact with the surface of the gallium nitride layer, and the other end of the contact electrode is in contact with the bottom of the gate, so that the contact electrode can be in contact with two-dimensional electron gas on the surface of the gallium nitride layer, and the hole in the P-type gallium nitride layer is controlled by controlling the two-dimensional electron gas, thereby increasing the control capability of the gate.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (10)
1. A p-type gallium nitride device with enhanced gating capabilities, comprising:
the substrate sequentially comprises a gallium nitride layer, an aluminum gallium nitride layer and a P-type gallium nitride layer from bottom to top, the surface of the substrate comprises a source region, a drain region opposite to the source region and a gate region positioned between the source region and the drain region, the gate region comprises a first etching region and second etching regions extending outwards from two sides of the first etching region, the first etching region internally and partially etches the P-type gallium nitride layer to form a first groove, and the second etching region inwards and completely etches the P-type gallium nitride layer to form a second groove;
the source electrode is positioned at the source electrode area;
the drain electrode is positioned at the drain electrode region;
the dielectric layer is positioned on the surface of the p-type gallium nitride layer between the source electrode and the drain electrode;
a gate electrode positioned in the first and second recesses and above the dielectric layer;
and the contact electrode is positioned in the second groove, one end of the contact electrode is in contact with the surface of the gallium nitride layer, and the other end of the contact electrode is in contact with the bottom of the grid.
2. The gated p-type GaN device of claim 1, wherein the first etched region and the second etched region extend in a first direction, the source region and the drain region extend in a second direction, and the first direction and the second direction are perpendicular.
3. The enhanced gating capability p-type gallium nitride device of claim 1, further comprising a two-dimensional electron gas layer between the gallium nitride layer and the aluminum gallium nitride layer, the contact electrode in contact with the two-dimensional electron gas layer.
4. The gated capability enhanced P-type gallium nitride device of claim 1, wherein the thickness of the P-type gallium nitride layer under the first etched region is 15-40 nm.
5. The enhanced gating capability p-type gallium nitride device of claim 1, wherein the dielectric layer is an aluminum oxide layer.
6. A method for fabricating a p-type gallium nitride device with enhanced gating capability, the method being used to fabricate the p-type gallium nitride device of any of claims 1 to 5, the method comprising:
s1, carrying out mesa isolation on the substrate to form an active region; the active region comprises a source region, a drain region opposite to the source region and a gate region positioned between the source region and the drain region, the gate region comprises a first etching region and a second etching region extending outwards from two sides of the first etching region, and the substrate sequentially comprises a gallium nitride layer, an aluminum gallium nitride layer and a P-type gallium nitride layer from bottom to top;
s2, partially etching the P-type gallium nitride layer below the first etching area by using an etching method;
s3, completely etching the P-type gallium nitride layer below the second etching area by using the etching method to form a contact electrode to-be-formed area;
s4, forming a source electrode in the source region, forming a drain electrode in the drain region, and forming a contact electrode in the contact electrode to-be-formed region;
s5, forming a dielectric layer on the surface of the p-type gallium nitride layer between the surface of the contact electrode and the source electrode and the drain electrode;
s6, completely etching the dielectric layer above the contact electrode by using the etching method;
and S7, forming a gate on the gate region.
7. The method of claim 6, wherein the etching comprises wet etching and/or dry etching.
8. The method of claim 6, wherein in step S4, a high work function metal and a non-oxidizable metal are deposited by electron beam evaporation and/or magnetron sputtering to form the source and the drain.
9. The method of claim 6, wherein in step S4, a low work function metal is deposited using electron beam evaporation and/or magnetron sputtering to form the gate electrode.
10. The method of claim 6, wherein in step S5, the dielectric layer is formed by chemical vapor deposition.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116666436A (en) * | 2023-07-24 | 2023-08-29 | 西交利物浦大学 | Fin type field effect transistor and preparation method thereof |
| CN117279402A (en) * | 2023-11-10 | 2023-12-22 | 西交利物浦大学 | Artificial synapse device |
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2022
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116666436A (en) * | 2023-07-24 | 2023-08-29 | 西交利物浦大学 | Fin type field effect transistor and preparation method thereof |
| CN116666436B (en) * | 2023-07-24 | 2023-10-17 | 西交利物浦大学 | Fin type field effect transistor and preparation method thereof |
| CN117279402A (en) * | 2023-11-10 | 2023-12-22 | 西交利物浦大学 | Artificial synapse device |
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