CN106653843A - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN106653843A
CN106653843A CN201510724668.5A CN201510724668A CN106653843A CN 106653843 A CN106653843 A CN 106653843A CN 201510724668 A CN201510724668 A CN 201510724668A CN 106653843 A CN106653843 A CN 106653843A
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semiconductor
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conducting material
fin
fin structure
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CN106653843B (zh
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杨玉如
江怀慈
林胜豪
黄世贤
陈建宏
吴俊元
蔡成宗
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United Microelectronics Corp
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Abstract

本发明公开一种半导体结构，包含有一半导体基底、一形成于该半导体基底上且其内包含有至少一凹槽的介电结构、一形成于该凹槽内的鳍片结构、以及一形成于该鳍片结构内的差排区域。该半导体基底包含有一第一半导体材料，而该鳍片结构包含有该第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数不同于该第一半导体材料的一晶格常数。该差排区域的一最高部分高于该凹槽的一开口。

Description

半导体结构
技术领域
本发明涉及一种半导体结构，尤其是涉及一种外延半导体鳍片结构。
背景技术
外延(epitaxial)结构广泛地使用于半导体制作工艺中，举例来说，现有技术常利用选择性外延成长(selective epitaxial growth，以下简称为SEG)技术于一单晶基板内形成一晶格排列与基板相同的外延结构，例如硅锗(silicongermanium，以下简称为SiGe)外延结构。利用SiGe外延结构的晶格常数(lattice constant)大于硅基板晶格的特点，SiGe外延结构可产生应力，并用于改善MOS晶体管的性能。
然而，外延结构的采用固然可有效提升元件效能，但外延结构的制作大大地增加了半导体制作工艺的复杂度以及制作工艺控制的困难度。举例来说，在SiGe外延结构中，可增加锗浓度来提升应力，然而较厚的SiGe外延结构或SiGe外延结构中较高的锗浓度会在外延结构内产生差排(dislocation)，而差排的产生会导致外延结构提供的应力变低，因此更增加了具有外延结构的半导体元件在设计与制作上的难度。
由此可知，外延结构的存在虽可有效增进元件效能，但随着半导体制作工艺与产品的复杂度不断提升，业界仍不断地面对挑战。
发明内容
因此，本发明的一目的在于提供一种半导体结构，用以避免外延结构生成时可能发生的差排缺陷影响最终半导体元件的性能。
为达上述目的，本发明提供一种半导体结构，该半导体结构包含有一半导体基底、一形成于该半导体基底上的介电结构、至少一形成于该半导体基底上的鳍片结构(fin)、以及形成于该鳍片结构内的差排(disclocation)区域。该半导体基底包含有一第一半导体材料，而该鳍片结构包含有该第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数(lattice constant)不同于该第一半导体材料的一晶格常数。该介电结构包含有一顶部表面，而该鳍片结构在该介电结构的该顶部表面以上包含有一第一高度，该差排区域在该介电结构的该顶部表面以上包含有一第二高度，且该差排区域的该第二高度小于该鳍片结构的该第一高度的四分之一。
本发明提供另提供一种半导体结构，该半导体结构包含有一半导体基底、一形成于该半导体基底上且其内包含有至少一凹槽的介电结构、一形成于该凹槽内的鳍片结构、以及一形成于该鳍片结构内的差排区域。该半导体基底包含有一第一半导体材料，而该鳍片结构包含有该第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数不同于该第一半导体材料的一晶格常数。该差排区域的一最高部分高于该凹槽的一开口。
根据本发明所提供的半导体结构，导致应力降低的差排区域在介电结构顶部表面以上的高度为鳍片结构层在介电结构顶部表面以上的高度的四分之一。也就是说，本发明所提供的半导体结构的差排区域远离鳍片结构的表面。由于在鳍式场效晶体管(fin field effect transistor，以下简称为FinFET)元件中，通道区域形成于鳍片结构的表面。因此，远离鳍片结构表面的差排区域将使得差排缺陷对通道区域的影响降至最低，甚至使差排缺陷不再对通道区域造成影响。简单地说，根据本发明所提供的半导体结构，即使差排区域形成鳍片结构之内，但仍不影响最终形成的晶体管元件的性能。
附图说明
图1至图7为本发明所提供的半导体结构的制方法的一优选实施例的示意图，其中：
图3为本发明所提供的半导体结构的制方法的一变化型的示意图；以及
图5为本发明所提供的半导体结构的制方法的另一变化型的示意图。
主要元件符号说明
100 半导体基底
102 介电结构
102S 介电结构的顶部表面
104 垫氧化层
106 硬掩模层
108、108’ 凹槽
110 外延层、第一部分
110t 外延层顶部表面、鳍片结构顶部表面
110b 外延层底部表面
112 应力松弛缓冲层、第二部分
120 差排区域
120t 差排区域最高部分
130 鳍片结构
140 栅极层
142 栅极介电层
144 栅极导电层
WF 凹槽宽度、鳍片宽度
WD 差排区域最宽部分的宽度
D 凹槽深度
H1 外延层高度
H2 应力松弛缓冲层高度
HF 鳍片高度
HD 差排区域在介电结构的顶部表面以上高度
具体实施方式
请参阅图1至图7，图1至图7为本发明所提供的半导体结构的制作方法的一优选实施例的示意图。如图1所示，本优选实施例所提供的半导体结构的制作方法首先提供一半导体基底100。半导体基底100包含有一第一半导体材料，第一半导体材料可以是硅、锗、III-V族化合物(compound)、或者是II-VI族化合物。在本优选实施例中，第一半导体材料优选为硅，然而不限于此。另外，在本优选实施例中，半导体基底100可以是一块硅(bulk)基底，且可具有(100)晶面(crystal plane)。接下来，可于半导体基底100上形成一介电结构102，介电结构102的制作方式可采用浅沟隔离(shallow trenchisolation，以下简称为STI)的制作方法。简单地说，首先于基底100上依序形成一垫氧化层104与一硬掩模层106，随后图案化垫氧化层104与硬掩模层106。如图1所示，在本优选实施例中，图案化的垫氧化层104与硬掩模层106可用以定义鳍片结构的位置与宽度，但不限于此。接下来，利用合适的蚀刻制作工艺通过此一图案化的垫氧化层104与硬掩模层106蚀刻半导体基底100，而于半导体基底100内形成多个凹槽(图未示)。随后，在该多个浅沟内填入绝缘材料。
请参阅图2。接下来，进行一平坦化制作工艺，用以移除多余的绝缘材料与图案化的硬掩模层106与垫氧化层104，而于半导体基底100上形成多个STI，而该多个STI即为本优选实施例中所述的介电结构102。接下来，利用合适的蚀刻制作工艺，例如但不限于一干蚀刻制作工艺，移除STI 102之间的半导体基底100，而于STI之间，即介电结构102内形成至少一凹槽108。在本优选实施例中，凹槽108的底部可如图2所示，与介电结构102的底部共平面。另外，如图2所示，凹槽108具有一宽度WF以及一深度D，凹槽108的宽度WF可用以定义一鳍片结构的宽度，在本优选实施例中凹槽108的宽度WF可以例如是5纳米(nanometer，nm)至15nm，而深度D可以例如是100nm至300nm。也就是说，本优选实施例的凹槽108具有一深宽比，而此深宽比介于10与60之间，但都不限于此。
另外请参阅图3，图3为本发明所提供的半导体结构的制作方法的一变化型的示意图。在本变化型中，半导体基底100上可先形成一介电结构102，随后通过合适的蚀刻制作工艺，例如一干蚀刻制作工艺，蚀刻介电结构102内的半导体基底100，而于介电结构102内形成至少一凹槽108’。值得注意的是，在本变化型中，蚀刻制作工艺可过度蚀刻(over-etching)暴露于介电结构102底部的半导体基底100，是以凹槽108’的底部如图3所示，低于介电结构102的底部。
请参阅图4。在形成凹槽108或108’之后，在凹槽108或108’内形成一外延层110。外延层110可通过SEG方法形成，但不限于此。且如图4所示，外延层110填满凹槽108。外延层110包含有前述的第一半导体材料以及一第二半导体材料，且第二半导体材料的一晶格常数(lattice constant)不同于第一半导体材料的晶格常数，且第二半导体材料的晶格常数优选为大于第一半导体材料的晶格常数。在本优选实施例中，第二半导体材料为锗，故外延层110包含SiGe。外延层110中的第二半导体材料包含有一第一浓度(即锗浓度)，且第一浓度可介于30％～70％，但不限于此。在本发明的一变化型中，外延层110的第二半导体材料的第一浓度甚至可达100％。另外需注意的是，外延层110为一未掺杂(undoped)的膜层。也就是说，外延层110内并未包含任何导电掺杂质(conductive dopant)，因此外延层110也为一本质硅锗(intrinsic SiGe)层。
如图4所示，外延层110是填满凹槽108，因此外延层110的一高度H1，即外延层110的顶部表面110t与底部表面110b所定义出的距离，或者说是外延层110的顶部表面110t与半导体基底100表面所定义出的距离，等于凹槽108的深度D，而外延层110的宽度即等于凹槽108的宽度WF。因此外延层110的高度H1与宽度WF的一高宽比与凹槽108的深宽比相同，也介于10与60之间，但不限于此。
值得注意的是，外延成长的特性，沿着半导体基底100(即硅基底)的晶格向上生长，但由于锗的晶格常数大于硅，因此外延层110在成长过程中，会因为硅与锗晶格的不匹配，自动发生差排的缺陷，且此差排缺陷会由凹槽108底部的半导体基底100的表面向上沿伸，而形成于如图4所示的差排区域120。需注意的是，在本优选实施例中，由于凹槽108的深宽比介于10与60之间，故差排区域120的高度被限制至小于10nm。
另外请参阅图5。图5为本发明所提供的半导体结构的制作方法的另一变化型的示意图。根据本变化型，在形成外延层110之前，可通过SEG制作工艺，先于凹槽108之内形成一应力松弛缓冲层(strain relax buffer，以下简称为SRB)层112，随后于SRB层112上形成外延层110。是以，外延层110与设置于外延层110与半导体基底100之间的SRB层112分别构成一鳍片结构的第一部分与第二部分。值得注意的是，鳍片结构的第二部分(即SRB层)112也包含第一半导体材料与第二半导体材料，且第二部分112中第二半导体材料具有一第二浓度。更重要的是，第一部分(即外延层)110的第一浓度大于第二部分112的第二浓度。举例来说，第二部分112中第二半导体材料的第二浓度可介于0％-50％，例如可以是由下而上由0％逐渐提升至50％。或者，第二部分112中的第二浓度可预定为30％，但此预定浓度可依据不同产品的需求于制作工艺中调整。另外需注意的是，第二部分112也为一未掺杂外延层。也就是说，第二部分112内并未包含任何导电掺杂质，故第二部分112也为本质硅锗层。另外，第二部分112具有一高度H2，且高度H2为凹槽104的深度D的三分之一至二分之一。举例来说，当凹槽108的深度D为100nm时，第二部分112的高度H2为30nm-50nm，但不限于此。另外，如图5所示，形成于第二部分112上的第一部分(即外延层)110是填满凹槽108。
请继续参阅图5。如图5所示，由于第二部分，即SRB层112的锗浓度介于外延层110的锗浓度与半导体基底的锗浓度(为0％)之间，因此SRB层112与外延层110的晶格不匹配较小，也因此差排缺陷的成长会被降低，故可更降低外延层110内差排区域的高度。另外，在形成SRB层112之后，可直接进行一热处理，用以更降低外延层110内的缺陷(defect)。值得注意的是，在此热处理中，并未有任何气体的加入。
请参阅图6。在完成所有外延层的制作后，进行一回蚀刻(etching back)制作工艺，用以移除部分介电结构102，使得部分外延层110突出于介电结构102的顶部表面102S。至此，是在半导体基底100上，以及介电材料102的凹槽108内完成至少一鳍片结构130的制作。鳍片结构130可包含外延层110，或可包含定义为第一部分的外延层110与定义为第二部分的SRB层112。如图6所示，在本优选实施例中，鳍片结构130突出于介电结构102的顶部表面102S，且鳍片结构130在介电结构102的顶部表面102S以上包含有一第一高度。换句话说，第一高度也就是外延层110的顶部表面110t以及介电结构102的顶部表面102S之间的距离。一般说来，此一第一高度定义为鳍片高度HF，在本优选实施例中，鳍片高度HF介于20nm～50nm，但不限于此。另外需注意的是，差排区域120的最高部分120t高于回蚀刻介电结构102后凹槽108的一开口。更详细地说，差排区域120在介电结构102的顶部表面102S以上包含有一第二高度HD，且差排区域120的第二高度HD小于鳍片结构130的第一高度HF的四分之一。由此可知，鳍片结构130的顶部表面110t不仅高于凹槽108的开口，其也高于差排区域120的最高部分120t。另外，鳍片结构130包含一宽度WF，其如前所述可介于5nm与15nm之间，而差排区域120最宽部分包含有一宽度WD，宽度WD可介于3nm与7nm之间。换句话说，差排区域120的宽度WD与鳍片结构130的宽度WD具有一比值，且该比值小于0.5。
请参阅图7。接下来，在半导体基底100上，尤其是介电结构102与鳍片结构130上依序形成一栅极介电层142与一栅极导电层144，并通过图案化方法图案化栅极介电层142与栅极导电层144，而于鳍片结构130上形成一栅极层140。如图7所示，栅极层140的延伸方向与鳍片结构130的延伸方向垂直，且栅极层140覆盖部分鳍片结构130的顶部与侧壁。栅极介电层142可包含现有介电材料如氧化硅(SiO)、氮化硅(SiN)、氮氧化硅(SiON)等介电材料。而在本优选实施例中，栅极介电层142还可包含高介电常数(high-K)材料，例如氧化铪(HfO)、硅酸铪(HfSiO)或、铝、锆、镧等金属的金属氧化物或金属硅酸盐(metal silicates)等，但不限于此。另外，当本优选实施例的栅极介电层142采用high-K材料时，本发明可与金属栅极(metal gate)制作工艺整合，以提供足以匹配high-K栅极介电层的控制电极。据此，栅极导电层144可配合金属栅极的前栅极(gate-first)制作工艺或后栅极(gate-last)制作工艺采用不同的材料。举例来说，当本优选实施例与前栅极制作工艺整合时，栅极导电层144可包含金属如钽(Ta)、钛(Ti)、钌(Ru)、钼(Mo)、或上述金属的合金、金属氮化物如氮化钽(TaN)、氮化钛(TiN)、氮化钼(MoN)等、金属碳化物如碳化钽(TaC)等。且该多个金属的选用是以所欲获得的多栅极晶体管元件的导电形式为原则，即以满足n型或p型晶体管所需功函数要求的金属为选用原则。另外，栅极导电层144可为单层结构或复合层(multi-layered)结构。而当本优选实施例与后栅极制作工艺整合时，栅极导电层144作为一虚置栅极(dummy gate)，其可包含半导体材料如多晶硅等。随后，可进行制作FinFET元件所需的后续步骤。
综上所述，根据本发明所提供的半导体结构，主要提供一深宽比介于10与60之间的凹槽，使得后续进行外延生长时，差排缺陷的延伸被限制在一定的高度以下。是以最终得到的鳍片结构中，差排区域的最高部分在介电结构表面以上的高度小于鳍片高度的四分之一，且差排区域的最宽部分的宽度小于鳍片宽度的一半。也就是说，通过凹槽的深宽比限制，差排区域的形成将自动远离作为通道区域的鳍片表面。甚或可通过SRB层的介入，影响差排区域的延伸，而使得差排区域更远离鳍片表面。因此，根据本发明所提供的半导体结构，最终形成的晶体管元件中，即使有差排缺陷的存在，仍然可确保外延层所提供的应力不受差排缺陷的影响，进而确保最终获得的晶体管元件的性能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种半导体结构，包含有：
半导体基底，包含有一第一半导体材料；
介电结构，形成于该半导体基底上，该介电结构包含有一顶部表面；
至少一鳍片结构(fin)，形成于该半导体基底上，且该鳍片结构包含有该第一半导体材料与一第二半导体材料，该第二半导体材料的一晶格常数(lattice constant)不同于该第一半导体材料的一晶格常数，且该鳍片结构在该介电结构的该顶部表面以上包含有一第一高度；以及
差排(disclocation)区域，形成于该鳍片结构内，该差排区域在该介电结构的该顶部表面以上包含有一第二高度，且该差排区域的该第二高度小于该鳍片结构的该第一高度的四分之一。
2.如权利要求1所述的半导体结构，其中该第二半导体材料的该晶格常数大于该第一半导体材料的该晶格常数。
3.如权利要求1所述的半导体结构，其中该鳍片结构包含有一第三高度，定义于该鳍片结构的一顶部表面与该半导体基底的表面之间。
4.如权利要求3所述的半导体结构，其中该鳍片结构包含有一第一宽度，该第三高度与该第一宽度具有一比值，且该比值介于10与60之间。
5.如权利要求3所述的半导体结构，其中该差排区域包含有一第二宽度，该第二宽度与该第一宽度具有一比值，且该比值小于0.5。
6.如权利要求1所述的半导体结构，其中该鳍片结构包含有一第一部分与一形成于该第一部分与该半导体基底之间的第二部分。
7.如权利要求6所述的半导体结构，其中该鳍片结构的该第一部分内的该第二半导体材料包含有一第一浓度，该第二部分内的该第二半导体材料包含有一第二浓度。
8.如权利要求7所述的半导体结构，其中该第一浓度大于该第二浓度。
9.如权利要求1所述的半导体结构，还包含一栅极层，形成于该鳍片结构上。
10.一种半导体结构，包含有：
半导体基底，包含有一第一半导体材料；
介电结构，形成于该半导体基底上，该介电结构内形成有至少一凹槽；
鳍片结构，形成于该凹槽内，该鳍片结构包含有该第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数不同于该第一半导体材料的一晶格常数；以及
差排区域，形成于该鳍片结构内，该差排区域的一最高部分高于该凹槽的一开口。
11.如权利要求10所述的半导体结构，其中该第二半导体材料的该晶格常数大于该第一半导体材料的该晶格常数。
12.如权利要求10所述的半导体结构，其中该鳍片结构包含有一宽度，且该鳍片结构的一顶部表面与一底部表面之间定义有一高度。
13.如权利要求12所述的半导体结构，其中该鳍片结构的该顶部表面高于该凹槽的该开口，以及高于该差排区域的该最高部分。
14.如权利要求12所述的半导体结构，其中该鳍片结构的该宽度等于该凹槽的该开口的一宽度。
15.如权利要求12所述的半导体结构，其中该鳍片结构的该高度与该宽度具有一比值，且该比值介于10与60。
16.如权利要求10所述的半导体结构，其中该鳍片结构包含有第一部分与设置于该第一部分与该半导体基底之间的第二部分，该第一部分内的该第二半导体材料包含有一第一浓度，该第二部分内的该第二半导体材料包含有一第二浓度，且该第一浓度大于该第二浓度。
17.如权利要求10所述的半导体结构，还包含一栅极层，形成于该鳍片结构上。
18.如权利要求10所述的半导体结构，其中该凹槽的底部低于该介电结构的底部。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130034943A1 (en) * 2006-09-27 2013-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-Gate Field-Effect Transistors Formed by Aspect Ration Trapping
US20140264438A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Heterostructures for Semiconductor Devices and Methods of Forming the Same
CN104299893A (zh) * 2013-07-17 2015-01-21 格罗方德半导体公司 通过执行替代生长制程形成finfet半导体装置的替代鳍片的方法
CN104798179A (zh) * 2012-12-20 2015-07-22 英特尔公司 缺陷转移和晶格失配外延膜
US20150206939A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company Ltd. Epitaxy in semiconductor structure and menufacuting method of the same
US9123627B1 (en) * 2014-05-01 2015-09-01 Globalfoundries Inc. Methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device
US20150249087A1 (en) * 2014-02-28 2015-09-03 Mirco Cantoro Semiconductor fin devices and method of faricating the semiconductor fin devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8324660B2 (en) * 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9012310B2 (en) * 2012-06-11 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation of source and drain regions
US9293534B2 (en) * 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130034943A1 (en) * 2006-09-27 2013-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-Gate Field-Effect Transistors Formed by Aspect Ration Trapping
CN104798179A (zh) * 2012-12-20 2015-07-22 英特尔公司 缺陷转移和晶格失配外延膜
US20140264438A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Heterostructures for Semiconductor Devices and Methods of Forming the Same
CN104299893A (zh) * 2013-07-17 2015-01-21 格罗方德半导体公司 通过执行替代生长制程形成finfet半导体装置的替代鳍片的方法
US20150206939A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company Ltd. Epitaxy in semiconductor structure and menufacuting method of the same
US20150249087A1 (en) * 2014-02-28 2015-09-03 Mirco Cantoro Semiconductor fin devices and method of faricating the semiconductor fin devices
US9123627B1 (en) * 2014-05-01 2015-09-01 Globalfoundries Inc. Methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device

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