CN106558551B - 一种半导体器件及其制造方法、电子装置 - Google Patents
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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Abstract
本发明提供一种半导体器件及其制造方法、电子装置,所述方法包括:提供具有NMOS区和PMOS区的半导体衬底,在半导体衬底上形成有栅极结构以及位于栅极结构两侧的源/漏区;在半导体衬底上形成掩膜层以覆盖栅极结构;蚀刻位于PMOS区的源/漏区上方的掩膜层以及半导体衬底,以在PMOS区的源/漏区中形成凹槽;通过外延生长工艺在掩膜层的表面形成牺牲物质颗粒;使凹槽转变为∑状凹槽的同时去除牺牲物质颗粒,并在∑状凹槽中形成锗硅层;去除掩膜层。根据本发明,可以有效去除形成用于外延生长锗硅的凹槽时生成的污染物,进一步改善凹槽的表面状况,提升外延生长的锗硅的质量。
Description
技术领域
本发明涉及半导体制造工艺,具体而言涉及一种半导体器件及其制造方法、电子装置。
背景技术
在先进的CMOS器件制造工艺中,嵌入式锗硅工艺经常被采用以提升CMOS器件的PMOS部分的性能。
对于CMOS而言,为了更好地控制在PMOS部分用于形成嵌入式锗硅的凹槽的深度,通常在衬底上先形成一双层牺牲层,此双层牺牲层的构成为:下层是氧化物,上层是氮化硅。形成所述凹槽之后,蚀刻残留物和诸如金属颗粒之类的污染物会附着在所述牺牲层的表面,在凹槽中外延生长锗硅时,存在上述物质的区域的成核聚集效应更为快速,锗硅更容易在这些区域生长,在这些区域生长锗硅是不被期望的。上述物质中的污染物的多数在沉积所述牺牲层时就已经生成,这些物质的存在会导致锗硅颗粒缺陷的形成。
为了消除这些锗硅颗粒缺陷,现有的方法有两种:一是外延生长掺杂硼的锗硅层时增加更多的蚀刻气体,其缺点在于产量的下降和单批次制造成本的升高;二是外延生长掺杂硼的锗硅层前优化实施的湿法清洗工艺条件,但是其对于去除效果的改善十分有限。
因此,需要提出一种方法,以解决上述问题。
发明内容
针对现有技术的不足,本发明提供一种半导体器件的制造方法,包括:提供具有NMOS区和PMOS区的半导体衬底,在所述半导体衬底上形成有栅极结构以及位于所述栅极结构两侧的源/漏区;在所述半导体衬底上形成掩膜层以覆盖所述栅极结构;蚀刻位于所述PMOS区的源/漏区上方的掩膜层以及所述半导体衬底,以在所述PMOS区的源/漏区中形成凹槽;通过外延生长工艺在所述掩膜层的表面形成牺牲物质颗粒;使所述凹槽转变为∑状凹槽的同时去除所述牺牲物质颗粒,并在所述∑状凹槽中形成锗硅层。
在一个示例中,所述外延生长的材料为未掺杂的多晶硅、单晶硅或者锗硅,所述外延为AP炉式外延、LP炉式外延或者腔室外延,温度为400℃-1000℃,压力为0.1torr-760torr,前体材料为硅烷、乙硅烷、DCS或者TCS。
在一个示例中,所述蚀刻为具有纵向蚀刻特性的干法蚀刻。
在一个示例中,采用先干法蚀刻再湿法蚀刻的工艺使所述凹槽转变为∑状凹槽。
在一个示例中,实施所述湿法蚀刻的过程中去除所述牺牲物质颗粒。
在一个示例中,形成所述锗硅层之前,还包括在所述∑状凹槽中形成籽晶层的步骤。
在一个示例中,形成所述锗硅层之后,还包括在所述锗硅层上形成帽层的步骤。
在一个示例中,形成所述锗硅层之后,还包括去除所述掩膜层的步骤。
在一个实施例中,本发明还提供一种采用上述方法制造的半导体器件。
在一个实施例中,本发明还提供一种电子装置,所述电子装置包括所述半导体器件。
根据本发明,可以有效去除形成所述用于外延生长锗硅的凹槽时生成的污染物,进一步改善所述凹槽的表面状况,提升外延生长的锗硅的质量。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述,用来解释本发明的原理。
附图中:
图1A-图1E为根据本发明示例性实施例一的方法依次实施的步骤所分别获得的器件的示意性剖面图;
图2为根据本发明示例性实施例一的方法依次实施的步骤的流程图。
具体实施方式
在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。然而,对于本领域技术人员而言显而易见的是,本发明可以无需一个或多个这些细节而得以实施。在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。
为了彻底理解本发明,将在下列的描述中提出详细的步骤,以便阐释本发明提出的半导体器件及其制造方法、电子装置。显然,本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。
应当理解的是,当在本说明书中使用术语“包含”和/或“包括”时,其指明存在所述特征、整体、步骤、操作、元件和/或组件,但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。
[示例性实施例一]
参照图1A-图1E,其中示出了根据本发明示例性实施例一的方法依次实施的步骤所分别获得的器件的示意性剖面图。
首先,如图1A所示,提供半导体衬底100,半导体衬底100的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)等。作为示例,在本实施例中,半导体衬底100选用单晶硅材料构成。在半导体衬底100中形成有隔离结构101,隔离结构101为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构。作为示例,在本实施例中,隔离结构101为浅沟槽隔离(STI)结构,其将半导体衬底100分为NMOS区和PMOS区。在半导体衬底100中还形成有各种阱(well)结构,为了简化,图示中予以省略。
在半导体衬底100上形成有栅极结构,作为一个示例,栅极结构可包括自下而上依次层叠的栅极介电层、栅极材料层和栅极硬掩蔽层。栅极介电层可包括氧化物层,如,二氧化硅(SiO2)层。栅极材料层可包括多晶硅层、金属层、导电性金属氮化物层、导电性金属氧化物层和金属硅化物层中的一种或多种,其中,金属层的构成材料可以是钨(W)、镍(Ni)或钛(Ti);导电性金属氮化物层可包括氮化钛(TiN)层;导电性金属氧化物层可包括氧化铱(IrO2)层;金属硅化物层可包括硅化钛(TiSi)层。栅极硬掩蔽层可包括氧化物层、氮化物层、氮氧化物层和无定形碳中的一种或多种,其中,氧化物层的构成材料可包括硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、正硅酸乙酯(TEOS)、未掺杂硅玻璃(USG)、旋涂玻璃(SOG)、高密度等离子体(HDP)或旋涂电介质(SOD);氮化物层可包括氮化硅(Si3N4)层;氮氧化物层可包括氮氧化硅(SiON)层。作为实例,本实施例中,栅极介电层为氧化物层,栅极材料层为多晶硅层,栅极硬掩蔽层为氮化硅层。栅极介电层、栅极材料层以及栅极硬掩蔽层的形成方法可以采用本领域技术人员所熟习的任何现有技术,优选化学气相沉积法(CVD),如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(RTCVD)、等离子体增强化学气相沉积(PECVD)等。
此外,作为示例,在半导体衬底100上还形成有位于栅极结构两侧且紧靠栅极结构的间隙壁结构。其中,间隙壁结构可以包括至少一氧化物层和/或氮化物层。
上述形成阱(well)结构、隔离结构、栅极结构以及间隙壁结构的工艺步骤已经为本领域技术人员所熟习,在此不再详细加以描述。此外,在形成所述间隙壁结构之前,还包括LDD注入以在源/漏区形成轻掺杂漏(LDD)结构及Halo注入以调节阈值电压Vt和防止源/漏耗尽层的穿通。在形成所述间隙壁结构之后,还包括源/漏区注入。
这里,需要特别说明的是,在形成栅极结构之前,可以在半导体衬底100上形成一氧化物层,以半导体衬底100和隔离结构101在后续工艺步骤中免受不必要的损耗。
接下来,在半导体衬底100上形成氧化物层102以覆盖栅极结构,作为示例,氧化物层102的厚度小于栅极结构的高度的10%,采用化学气相沉积工艺形成氧化物层102。然后,在氧化物层102上形成氮化硅层103以覆盖栅极结构,采用化学气相沉积工艺形成氮化硅层103。至此,氮化硅层103和氧化物层102构成双层掩膜层,其作用是控制后续形成的用于外延生长锗硅的凹槽的深度。然后,在氮化硅层103上形成光致抗蚀剂层104,图形化光致抗蚀剂层104以露出半导体衬底100的PMOS区。
接着,如图1B所示,采用干法蚀刻工艺纵向蚀刻位于PMOS区的源/漏区上方的双层掩膜层以及半导体衬底100,以在PMOS区的源/漏区中形成凹槽105。作为示例,所述纵向蚀刻所使用的蚀刻气体包括含氟气体(CF4、CHF3、CH2F2等)、稀释气体(He、N2等)以及氧气。然后,采用灰化工艺去除光致抗蚀剂层104。
接着,如图1C所示,通过外延生长工艺在双层掩膜层的表面形成牺牲物质颗粒106。由于前述工艺在双层掩膜层的表面形成大量的污染物,这些污染物具有更快的成核聚集效应,因此,这些污染物与外延生长的材料组合形成牺牲物质颗粒106。作为示例,外延生长的材料可以为未掺杂的多晶硅、单晶硅、锗硅以及其它硅材料。所述外延可以为AP炉式外延、LP炉式外延或者腔室外延,温度为400℃-1000℃,压力为0.1torr-760torr,前体材料可以为硅烷、乙硅烷、DCS、TCS等。
接着,如图1D所示,使凹槽105转变为∑状凹槽107。通常采用先干法蚀刻再湿法蚀刻的工艺形成∑状凹槽107,该工艺的具体步骤如下:先采用各向同性的干法蚀刻工艺蚀刻凹槽105,在凹槽105的下方形成椭圆形凹槽,即形成碗状凹槽,作为示例,采用Cl2和NF3作为主蚀刻气体,温度40℃-60℃,功率100W-500W,偏压0V-10V,蚀刻时间根据所述碗状凹槽的侧壁向半导体衬底100的沟道区凹进的深度而定;再采用湿法蚀刻工艺扩展蚀刻所述碗状凹槽,以形成∑状凹槽107,所述湿法蚀刻的温度为30℃-60℃,时间依据∑状凹槽107的期望尺寸而定,一般为100s-300s,作为示例,采用四甲基氢氧化铵(TMAH)溶液作为所述湿法蚀刻的腐蚀液。在实施所述湿法蚀刻的过程中,形成于双层掩膜层的表面的牺牲物质颗粒106被有效去除。
接下来,对∑状凹槽107进行预处理,以确保∑状凹槽107的侧壁及底部具有清洁的表面。所述预处理包括下述步骤:首先,执行湿法清洗,以去除残留于∑状凹槽107的侧壁及底部的蚀刻残留物和杂质;然后,对半导体衬底100实施烘焙处理。
作为示例,所述湿法清洗的清洗液可以是氨水、双氧水和水的混合物(SC1)以及稀释的氢氟酸(DHF)的组合,也可以是臭氧水、SC1和DHF的组合。上述组合中的各个清洗液的浓度以及进行所述湿法清洗所需要的其它条件,例如温度和处理时间等,均可以选用本领域技术人员所熟习的浓度数值和实施条件,在此不再予以例举。
作为示例,在氢气的氛围下实施所述烘焙处理,所述烘焙处理的温度为780℃-850℃,处理时间为60s-120s。
接着,如图1E所示,采用选择性外延生长工艺在∑状凹槽107中形成锗硅层108。作为示例,所述选择性外延生长工艺可以采用低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、超高真空化学气相沉积(UHVCVD)、快速热化学气相沉积(RTCVD)和分子束外延(MBE)中的一种。锗硅层108通常为掺杂硼的锗硅层,作为示例,锗含量(锗原子百分比)为5-30%。
形成锗硅层108之前,还可以采用选择性外延生长工艺在∑状凹槽107中依次形成籽晶层和未掺杂的锗硅层,所述籽晶层可以为硅层。由于需要为随后将要形成的锗硅层108留出足够的空间,所以形成的籽晶层和未掺杂的锗硅层不能太厚,以防填满整个∑状凹槽107。
接下来,在锗硅层108上形成帽层。采用原位外延生长工艺形成帽层,即形成帽层所采用的外延生长工艺与形成锗硅层108所采用的外延生长工艺在同一个反应腔室中进行。作为示例,帽层的构成材料可以是硅(Si)或者硼硅(SiB),其中,所述硼硅中硼原子的掺杂剂量为5.0×e14atom/cm3-5.0×e20atom/cm3;也可以是掺杂硼和碳的单晶硅(SiCB),其中,所述硼原子的掺杂剂量为5.0×e14atom/cm3-5.0×e20atom/cm3,所述碳原子的掺杂剂量为5.0×e14atom/cm3-5.0×e20atom/cm3。然后,采用湿法清洗工艺去除双层掩膜层中的氮化硅层103和栅极结构中的栅极硬掩蔽层,作为示例,所述湿法清洗工艺的腐蚀液为热磷酸。
至此,完成了根据本发明示例性实施例一的方法实施的工艺步骤。根据本发明,可以有效去除形成用于外延生长锗硅的凹槽时生成的污染物,进一步改善凹槽的表面状况,提升外延生长的锗硅的质量。
参照图2,其中示出了根据本发明示例性实施例一的方法依次实施的步骤的流程图,用于简要示出制造工艺的流程。
在步骤201中,提供具有NMOS区和PMOS区的半导体衬底,在半导体衬底上形成有栅极结构以及位于栅极结构两侧的源/漏区;
在步骤202中,在半导体衬底上形成掩膜层以覆盖栅极结构;
在步骤203中,蚀刻位于PMOS区的源/漏区上方的掩膜层以及半导体衬底,以在PMOS区的源/漏区中形成凹槽;
在步骤204中,通过外延生长工艺在掩膜层的表面形成牺牲物质颗粒;
在步骤205中,使凹槽转变为∑状凹槽的同时去除所述牺牲物质颗粒,并在∑状凹槽中形成锗硅层;
在步骤206中,去除掩膜层。
[示例性实施例二]
接下来,可以通过后续工艺完成整个半导体器件的制作,包括:在NMOS区的源/漏区形成碳硅层;形成金属硅化物;实施应力近临工艺以增强作用于沟道区的应力;依次形成接触孔蚀刻停止层和层间介电层,并形成贯通层间介电层和接触孔蚀刻停止层的分别连通栅极材料层和金属硅化物的接触孔;在接触孔中形成接触塞;形成多个互连金属层,通常采用双大马士革工艺来完成;形成金属焊盘,用于后续实施器件封装时的引线键合。
[示例性实施例三]
本发明还提供一种电子装置,其包括根据本发明示例性实施例二的方法制造的半导体器件。所述电子装置可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备,也可以是任何包括所述半导体器件的中间产品。所述电子装置,由于使用了所述半导体器件,因而具有更好的性能。
本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。
Claims (10)
1.一种半导体器件的制造方法,包括:
提供具有NMOS区和PMOS区的半导体衬底,在所述半导体衬底上形成有栅极结构以及位于所述栅极结构两侧的源/漏区;
在所述半导体衬底上形成掩膜层以覆盖所述栅极结构;
蚀刻位于所述PMOS区的源/漏区上方的掩膜层以及所述半导体衬底,以在所述PMOS区的源/漏区中形成凹槽;
通过外延生长工艺在所述掩膜层的表面形成牺牲物质颗粒;
使所述凹槽转变为∑状凹槽的同时去除所述牺牲物质颗粒,并在所述∑状凹槽中形成锗硅层。
2.根据权利要求1所述的方法,其特征在于,所述外延生长的材料为未掺杂的多晶硅、单晶硅或者锗硅,温度为400℃-1000℃,压力为0.1torr-760torr,前体材料为硅烷、乙硅烷、DCS或者TCS。
3.根据权利要求1所述的方法,其特征在于,所述蚀刻为具有纵向蚀刻特性的干法蚀刻。
4.根据权利要求1所述的方法,其特征在于,采用先干法蚀刻再湿法蚀刻的工艺使所述凹槽转变为∑状凹槽。
5.根据权利要求4所述的方法,其特征在于,实施所述湿法蚀刻的过程中去除所述牺牲物质颗粒。
6.根据权利要求1所述的方法,其特征在于,形成所述锗硅层之前,还包括在所述∑状凹槽中形成籽晶层的步骤。
7.根据权利要求1所述的方法,其特征在于,形成所述锗硅层之后,还包括在所述锗硅层上形成帽层的步骤。
8.根据权利要求1所述的方法,其特征在于,形成所述锗硅层之后,还包括去除所述掩膜层的步骤。
9.一种采用权利要求1-8之一所述的方法制造的半导体器件。
10.一种电子装置,所述电子装置包括权利要求9所述的半导体器件。
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