CN106548974B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN106548974B
CN106548974B CN201510860211.7A CN201510860211A CN106548974B CN 106548974 B CN106548974 B CN 106548974B CN 201510860211 A CN201510860211 A CN 201510860211A CN 106548974 B CN106548974 B CN 106548974B
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groove
barrier layer
conductive features
layer
semiconductor device
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CN106548974A (zh
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杨士亿
李明翰
眭晓林
郭子骏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开提供一半导体装置及其制造方法。该半导体装置制造方法包含在基底上方形成第一导电特征部件，在第一导电特征部件上方形成介电层，在介电层中形成沟槽，在沟槽中形成第一阻挡层，实施热处理将第一阻挡层的第一部分转换成第二阻挡层，在沟槽中暴露出第一导电特征部件，而第二阻挡层的一部分设置于介电层上方，并在沟槽中形成第二导电特征部件。

Description

半导体装置及其制造方法
技术领域
本公开涉及半导体技术，且特别涉及半导体装置的金属互连(metalinterconnection)结构及其制造方法。
背景技术
半导体集成电路(integrated circuit，IC)工业已经历了快速成长，集成电路的材料与设计上的技术演进已产生数个集成电路的世代，每一世代的集成电路较上一世代更小且更复杂。在集成电路的发展史中，功能密度(每一晶片区互连的装置数目)增加，同时几何尺寸(工艺中所制造的最小的元件(或线路))缩小。
此元件尺寸微缩化的工艺一般来说具有增加生产效率与降低相关费用的益处。元件尺寸微缩化也增加了处理与制造集成电路的复杂性。为了实现这些发展，在集成电路的加工与处理中需要相似的发展。其中，一个领域为晶体管和其他元件之间的布线或互连。虽然现存的制造集成电路元件的方法一般来说对于其预期目的都是适当的，但是这些方法并非全方面令人满意。举例来说，发展完善的工艺来形成低导通孔电阻的金属互连结构是一种挑战。
发明内容
在一些实施例中，本公开提供半导体装置的制造方法，其包含在基底上方形成第一导电特征部件；在第一导电特征部件上方形成介电层；在介电层中形成沟槽，其中沟槽在其下部具有第一宽度且在其上部具有第二宽度，其中第二宽度大于第一宽度，其中第一导电特征部件在沟槽中暴露出来；在沟槽中形成第一阻挡层，其中第一阻挡层具有设置于介电层上方的第一部分和设置于第一导电特征部件上方的第二部分；实施热处理将第一阻挡层的第一部分转换成第二阻挡层；在沟槽中暴露出第一导电特征部件，且第二阻挡层的一部分设置于介电层上方；以及在沟槽中形成第二导电特征部件。
在其他实施例中，本公开提供半导体装置的制造方法，其包含在设置于基底上的第一导电特征部件上方形成介电层；在介电层中形成沟槽，其中沟槽在其上部具有第一宽度且在其下部具有第二宽度，其中第一宽度大于第二宽度，其中第一导电特征部件在沟槽中暴露出来；在沟槽中形成第一阻挡层，其中第一阻挡层的第一部分沿着介电层定义的沟槽的侧壁表面形成，且第一阻挡层的第二部分沿着第一导电特征部件定义的沟槽的底部表面形成；将第一阻挡层的第一部分转换成第二阻挡层，其中第二阻挡层由不同于第一阻挡层的材料形成；在沟槽中暴露出第一导电特征，且第二阻挡层的一部分设置于介电层上方；以及在沟槽中形成第二导电特征部件。
在另外一些实施例中，本公开提供半导体装置，其包含第一导电特征部件，设置于基底上方；第二导电特征部件，设置于第一导电特征部件上方，其中第二导电特征部件具有第一宽度的上部和第二宽度的部分，第二宽度与第一宽度不同，其中下部物理性接触第一导电特征部件的顶部；第一阻挡层，沿着第二导电特征部件的侧壁设置；以及介电层，沿着第一阻挡层设置，其中介电层物理性接触第一阻挡层远离第二导电特征部件的一侧。
附图说明
根据以下的详细说明并配合说明书附图做完整公开。应注意的是，根据本产业的一般作业，图示中的各种特征并未必按照比例绘制。事实上，可能任意的放大或缩小各种特征的尺寸，以做清楚的说明。
图1显示依据本公开的一些实施例的制造半导体装置的例示性方法的流程图。
图2显示依据本公开的一些实施例的半导体装置的一例示性初始结构的剖面示意图。
图3、4、5A、5B、6、7、8、9、10A、10B显示依据本公开的一些实施例的例示性半导体装置的剖面示意图。
附图标记说明：
100 方法
102、104、106、108、110、112、114、116、118 步骤
200 半导体装置
205 初始结构
210 基底
214 导电特征部件
216 阻挡层
220 介电层
310 沟槽
311 底层
312 中间层
313 阻剂
315 第一侧壁
410 通孔沟槽
411 阶梯式沟槽
415 第二侧壁
416 底部
510 第一阻挡层
510D 第一部分
510M 第二部分
610 第二阻挡层
620 第三阻挡层
700 热处理
710 通孔金属
720 金属层
725 导线
W1 第一宽度
W2 第二宽度
具体实施方式
要了解的是本说明书以下的公开内容提供许多不同的实施例或范例，以实施本公开的不同特征。而本说明书以下的公开内容是叙述各个构件及其排列方式的特定范例，以求简化本公开的说明。当然，这些特定的范例并非用以限定本公开。例如，若是本说明书以下的公开内容叙述了将一第一特征形成于一第二特征之上或上方，即表示其包含了所形成的上述第一特征与上述第二特征是直接接触的实施例，亦包含了尚可将附加的特征形成于上述第一特征与上述第二特征之间，而使上述第一特征与上述第二特征可能未直接接触的实施例。另外，本公开的说明中不同范例可能使用重复的参考符号及/或用字。这些重复符号或用字是为了简化与清晰的目的，并非用以限定各种实施例及/或所述外观结构之间的关系。
再者，为了方便描述附图中一元件或特征部件与另一(多)元件或(多)特征部件的关系，可使用空间相关用语，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了附图所绘示的方位之外，空间相关用语涵盖使用或操作中的装置的不同方位。例如，若翻转附图中的装置，描述为位于其他元件或特征部件“下方”或“在...之下”的元件，将定位为位于其他元件或特征部件“上方”。因此，范例的用语“下方”可涵盖上方及下方的方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。
图1显示依据本公开的一些实施例的制造一个或多个半导体装置的方法100的流程图。方法100详述如下，参照图2所示的半导体装置的初始结构205和图3、4、5A、5B、6、7、8、9、10A、10B所示的半导体装置200。
参照图1、2，方法100从步骤102开始，提供初始结构205。初始结构205包含基底210，其可包含硅。或者，基底210可包含其他元素半导体例如锗。基底210也可包含化合物半导体例如碳化硅、砷化镓、砷化铟和磷化铟。基底210可包含合金半导体例如硅锗、碳化硅锗、磷化镓砷和磷化镓铟。在一实施例中，基底210包含磊晶层。举例来说，基底可包含覆盖块状半导体的磊晶层。此外，基底210可包含绝缘体上的半导体(semiconductor-on-insulator，SOI)结构。举例来说，基底210可包含埋置氧化(buried oxide，BOX)层，其通过植氧分离(separation by implantation of oxygen，SIMOX)工艺或其他合适的技术，例如晶圆接合(bonding)和研磨(grinding)形成。
基底210也包含各种p型掺杂区及/或n型掺杂区，其通过例如离子布植及/或扩散工艺建置。这些掺杂区包含n型阱、p型阱、轻掺杂区(light doped region，LDD)、重掺杂源极和漏极(source/drain，S/D)和各种通道掺杂轮廓，其是设置来形成各种集成电路(IC)元件，例如互补式金属氧化物半导体场效晶体管(complimentary metal-oxide-semiconductor field-effect transistor，CMOSFET)、影像感测器及/或发光二极管(light emitting diode，LED)。基底210可还包含其他功能性特征部件(feature)，例如形成于基底内或其上的电阻器或电容器。基底210可还包含横向的隔离特征部件来分离各种形成于基底210内的元件。在一实施例中，浅沟槽隔离(shallow trench isolation，STI)特征部件用作横向隔离。各种集成电路元件可还包含其他特征部件，例如设置于源极/漏极上的硅化物和覆盖通道区的栅极堆叠。
初始结构205也可包含多个介电层和导电特征部件整合来形成互连结构，其是配置来耦接各种p型和n型掺杂区和其他功能性特征部件(例如栅极电极)，以成为一功能性集成电路。在一例子中，初始结构205可包含一部分的互连结构并统称为基底210。下面将进一步描述此互连结构。
如上所述，基底210包含互连结构。此内连接结构包含多层互连(multi-layerinterconnect，MLI)结构和整合多层内连接结构的层间介电层(inter-level dielectric，ILD)，以提供电性布线来耦接基底210内的各种元件至输入/输出电源和信号。此互连结构包含各种金属线、接点(contact)和导通孔(via)特征部件(或通孔插塞(via plug))，金属线提供水平电性布线，接点提供硅基底与金属线之间的垂直连接，而导通孔特征部件提供不同金属层内的金属线之间的垂直连接。
例示性的导电特征部件214如图2所示。在一实施例中，导电特征部件214包含一部分的互连结构。举例来说，导电特征部件214包含接点、金属导通孔及/或金属线。导电特征部件214可包含铝(Al)、铜(Cu)及/或钨(W)。在另一实施例中，导电特征部件214包含电容器的电极、电阻器或一部分的电阻器。或者，导电特征部件214包含掺杂区(例如源极或漏极)或栅极电极。在另一例子中，导电特征部件214为分别的设置于源极、漏极或栅极电极上的硅化物特征部件。
在一些实施例中，导电特征部件214可由阻挡层216围绕来防止扩散及/或提供材料的附着力。阻挡层216可包含氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氮化钛硅(TiSiN)及/或氮化钽硅(TaSiN)。导电特征部件214和阻挡层216可通过包含微影、蚀刻和沉积的步骤形成。一例示性的微影工艺可包含涂布、曝光、曝光后烘烤和显影工艺。此蚀刻工艺可包含湿蚀刻、干蚀刻及/或前述的组合。此沉积工艺可包含物理气相沉积(physical vapordeposition，PVD)、化学气相沉积(chemical vapor deposition，CVD)、金属有机化学气相沉积(metal-organic chemical vapor deposition，MOCVD)和原子层沉积(atomic layerdeposition，ALD)及/或其他合适的技术。
初始结构205也包含沉积于基底210和导电特征部件214上方的介电层220。介电层220可包含氧化硅、氮化硅、具有低于热氧化硅的介电常数(k)的介电材料层(因此称为低介电常数介电材料层(low-k dielectric material layer))及/或其他合适的介电材料层。介电层220可包含单层或多层。介电层220可通过化学气相沉积、原子层沉积或旋转涂布沉积。
参照图1、3，当得到初始结构205后，方法100进行至步骤104，将一部分的介电层220移除来形成介电层220中的沟槽310。沟槽310为即将形成于其中的导电线的预留位置。沟槽310可通过第一微影和蚀刻工艺形成。第一微影工艺可包含形成光阻(或阻剂)层于介电层220上方，将此阻剂曝光成为一图案，实施曝光后烘烤工艺，并将此阻剂显影来形成包含阻剂的遮罩元件。此遮罩元件接着用来蚀刻出沟槽在介电层220中，此蚀刻工艺可包含干蚀刻、湿蚀刻及/或其他合适的工艺。
参照图1、4，方法100进行至步骤106，实施第二微影工艺来定义沟槽310上方的通孔沟槽(via trench)410。如图所示，此处显示的是使用三层材料的例示性微影工艺(三层微影(tri-layer lithography))。此三层为称为底层(bottom layer，BL)311的第一材料层、称为中间层(middle layer，ML)312的第二材料层和称为阻剂313的第三材料层。底层311在随后的蚀刻工艺保护介电层220。在一些实施例中，底层311包含不含硅的有机聚合物，中间层312可包含设计来提供与底层311具有蚀刻选择性的含硅层。在一些实施例中，也将中间层312设计来作为底部抗反射涂层，其减少微影曝光工艺期间的反射，进而增加影像对比度和提高影像分辨率。底层311填入沟槽310，中间层312形成于底层311上方，且阻剂313形成于中间层312上方。通过微影工艺将阻剂313图案化来提供在其中的通孔沟槽410。如图所示，通孔沟槽410与各自的导电特征部件214对齐。
参照图1、5A，方法100进行至步骤108，将通孔沟槽410延伸至穿透各种下方层。如图所示，通过通孔沟槽410将中间层312、底层311和介电层220蚀刻，暴露出一部分的导电特征部件214。在本实施例中，沟槽310具有第一宽度W1，其宽于通孔沟槽410的第二宽度W2。此蚀刻工艺包含湿蚀刻、干蚀刻及/或前述的组合。举例来说，此蚀刻工艺包含使用氟是化学物，例如CF4、SF6、CH2F2、CHF3及/或C2F6的等离子体干蚀刻工艺。可分别调整蚀刻工艺的各种蚀刻参数，例如使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、蚀刻剂流速及/或其他合适的参数。
形成通孔沟槽410之后，将阻剂313、中间层312和底层311的余留的部分通过另一蚀刻工艺移除，例如湿式剥离及/或等离子体灰化。如图5B所示，在移除阻剂313、中间层312和底层311的余留的部分之后，露出沟槽310且与通孔沟槽410彼此连通(或连接)。一部分的导电特征部件214在各别的通孔沟槽410中暴露出来。
沟槽310和通孔沟槽410的组合一般可称作阶梯式沟槽(stepped trench)(或深沟槽)411。因此，阶梯式沟槽411具有第一宽度W1的上部和第二宽度W2的下部。
参照图1、6，方法100进行至步骤110，将第一阻挡层510沉积于阶梯式沟槽411(即通孔沟槽410和沟槽310的组合)中，并且也沉积于介电层220的顶部。第一阻挡层510可包含锰(Mn)、氮化锰(MnN)、钛(Ti)、钽(Ta)、钴(Co)、钴钨(CoW)、钼(Mo)及/或其他合适的导电材料。第一阻挡层510可通过原子层沉积(ALD)、物理气相沉积(PVD)、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)及/或其他合适的技术沉积。在一些实施例中，第一阻挡层510通过原子层沉积(ALD)来实现有着相当薄厚度的良好阶梯覆盖。举例来说，第一阻挡层510包含通过原子层沉积(ALD)的氮化锰(MnN)层。
在本公开的实施例中，第一阻挡层510顺应性地(conformably)沿着沟槽310的第一侧壁315、通孔沟槽410的第二侧壁415和由导电特征部件214定义的通孔沟槽410的底部416沉积并与其物理性接触。因此，沿着第一侧壁315和第二侧壁415延伸的第一阻挡层510的第一部分物理性接触介电层220，而沿着底部416延伸的第一阻挡层510的第二部分物理性接触导电特征部件214。为了清楚和简明，第一部分以符号510D标示，第二部分以符号510M标示。
参照图1和7，方法100进行至步骤112，实施热处理700来将第一部分510D和第二部分510M转变(或转换)成不同的阻挡层。在一些实施例中，在热处理700期间，第一部分510D与介电层220反应而转变成第二阻挡层610，而第二部分510M与导电特征部件214反应而转变成第三阻挡层620(或底部阻挡层)。在此实施例中，第二阻挡层610由不同于第三阻挡层620的材料形成。
或者，在一些实施例中，在实施热处理700将第一部分510D转变(或转换)成第二阻挡层610的期间，第二部分510M保持不变，且第三阻挡层620由相同于第一阻挡层510的材料形成。
在本公开的实施例中，第二阻挡层610相较于第三阻挡层620在随后的蚀刻具有显著不同的蚀刻选择性。选择第一阻挡层510和介电层220，使得形成的第二阻挡层610有适当能力来增强介电层220与填入通孔沟槽410和沟槽310的金属层之间的附着力并防止介电层220与金属层之间的互相扩散和反应。在一例子中，第一阻挡层510包含氮化锰(MnN)，且介电层220包含氧化硅。在热处理700之后，第一部分510D转换成MnSixOyNz，且第二部分510M与导电特征部件214几乎没有反应，因此第三阻挡层620仍然为氮化锰层510M。此处，x代表硅成分的原子比例，y代表氧成分的原子比例，且z代表氮成分的原子比例。
用热处理700形成的第二和第三阻挡层610、620有自选择形成的本质(self-selective-formation nature)，其提供工艺简化且减轻工艺限制。特别来说，通过热处理700转换，第二阻挡层610可带有第一阻挡层510的薄膜特征，例如有薄的厚度的良好阶梯覆盖，其对将要填入通孔沟槽410的金属层提供良好的侧壁保护并避免突出部分(overhang)的形成。
热处理700可包括快速热退火(rapid thermal anneal，RTA)、激光退火、炉退火及/或闪光灯退火。举例来说，实施热退火的温度范围从100℃至400℃，并使用惰性气体例如氦(He)、氖(Ne)、氩(Ar)、氪(Kr)、氙(Xe)和氮(N2)。举另一例子来说，在真空环境中实施热处理700。
参照图1和图8，方法100进行至步骤114，将第三阻挡层620移除。在本公开的实施例中，实施选择性蚀刻使得蚀刻工艺蚀刻第三阻挡层620，而大致不蚀刻第二阻挡层610和导电特征部件214。选择性蚀刻工艺提供工艺简化且减轻工艺限制，此选择性蚀刻可包含选择性干蚀刻、选择性湿蚀刻及/或前述的组合。如上所述，在一些实施例中，第三阻挡层620由相同于第一阻挡层510的材料形成，即氮化锰(MnN)，而第二阻挡层610为MnSixOyNz，且导电特征部件214为铜。在此实施例中，在大致没有蚀刻MnSixOyNz的第二阻挡层610的情况下，氮化锰(MnN)的第三阻挡层620通过用弱酸溶液(pH值小于7)的水溶液湿式清洁工艺移除。此水溶液湿式清洁工艺增加制造过程的简化且也使得导电特征部件214的工艺引起的损伤(process-induced-damage)最小化。
在本公开的实施例中，在移除第三阻挡层620之后，在通孔沟槽410中暴露出导电特征部件214。沉积于通孔沟槽410的底部上的底部阻挡层(即第三阻挡层620)的电阻通常高于沉积在通孔沟槽410中且位在此底部阻挡层上方的金属层的电阻。因此，底部阻挡层的电阻决定了由底部阻挡层和金属层的组合形成的导电互连结构的电阻。此电阻称为导通孔电阻(via resistance)。在本公开的实施例中，方法100提供无底部阻挡层(bottom-barrier-free)的方案。
参照图1和9，方法100进行至步骤116，形成通孔金属(via metal)710于通孔沟槽410中。通孔金属710物理性接触导电特征部件214，通孔金属710可包含铜或铜合金，例如铜锰(CuMn)、铜铝(CuAl)、铜钛(CuTi)、铜钒(CuV)、铜铬(CuCr)、铜硅(CuSi)及/或铜铌(CuNb)。通孔金属710可通过物理气相沉积(PVD)、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、无电电镀沉积(electroless deposition，ELD)及/或其他合适的技术形成。在本公开的实施例中，通孔金属710通过无电电镀沉积(ELD)工艺形成，其提供低工艺温度、固有的工艺选择性和顺应性由下而上的沉积，以减少通孔沟槽填充间隙(gap-fill)的挑战。在一实施例中，通孔金属710为无电电镀沉积(ELD)工艺沉积的铜。如图所示，通孔金属710具有第二阻挡层610作为其侧壁阻挡层，因此第二阻挡层610通过限制与通孔金属扩散进入下方的介电层220有关联的电子迁移(electron migration，EM)和时间相依介电崩溃(time-dependent dielectric breakdown，TDDB)，改善了装置的可靠度。再者，通过具有侧壁阻挡层，也放宽了通孔金属710在选择上的限制。
参照图1和10A，方法100进行至步骤118，将金属层720填入沟槽310中。在本公开的实施例中，金属层720设置于通孔金属710上方并与其直接接触。在本公开的实施例中，没有阻挡层在通孔金属710与金属层720的接口上的情况下，降低了由通孔金属710与金属层720一起贡献的电阻。金属层720可包含Cu、Co、W、Ru、Ag、Au、CoW、CoF、CoSi或其他合适的金属。金属层720可通过物理气相沉积(PVD)、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)或电镀沉积。在一实施例中，金属层720包含由物理气相沉积(PVD)沉积的铜层。在一实施例中，金属层720包含由电镀沉积的铜层。在各种其他例子中，可通过其他技术实施铜沉积。可增加铜的回焊(reflow)工艺来提升铜的填充轮廓。
通过分开形成通孔金属710和金属层720，其提供使用不同沉积工艺来更佳地配合通孔沟槽410和沟槽310的不同需求的好处。此方案有时称作通孔预先填充(via pre-fill)方案。举例来说，使用无电电镀沉积(ELD)工艺形成通孔金属710，因为此工艺可在间隙填充上作适当的顺应性沉积，而使用物理气相沉积(PVD)填充具有较宽间隙的沟槽310，因为相较于无电电镀沉积(ELD)工艺，此工艺有着较快的沉积速率和较低的工艺成本。
此外，实施化学机械研磨(chemical mechanical polishing，CMP)工艺来将半导体装置200的顶表面平坦化，以移除多余的金属层720和位于介电层220上方的第二阻挡层610，如图10B所示。保留沟槽310中的第二阻挡层610和金属层720，形成导线725。由于化学机械研磨(CMP)工艺，介电层220的顶表面和导线725的顶表面大致共平面。
可在方法100之前、期间及之后提供额外的步骤，且对于方法100的其他实施例，上述的一些步骤可被取代、删除或移动。举例来说，可不在步骤116和步骤118分别地分开形成通孔金属710和沉积金属层720，取而代之的是，通孔金属710和金属层720通过一个沉积工艺形成。
半导体装置200可包含其他特征部件，其可通过随后的工艺形成。举例来说，各种导通孔/导线和多层互连特征部件(例如金属层和层间介电层)形成于基底210上方。举例来说，多层互连结构包含垂直互连结构，例如传统导通孔或接点，和水平互连结构，例如金属线。
基于上述，可见本公开实施例提供形成无底部阻挡层的金属互连结构的方法来实现低通孔接触电阻，如此一来，在通孔金属的底部和金属线的底部无底部阻挡层，金属线形成于通孔金属上方并与其物理性接触。此方法对无电电镀沉积(ELD)的通孔金属提供侧壁阻挡层，以改善时间相依介电崩溃(TDDB)和电子迁移(EM)。此方法提供完善的金属互连结构的形成工艺，且此工艺有着选择性形成和选择性蚀刻来减轻工艺限制及简化制造工艺。
本公开的实施例提供制造半导体装置的许多不同的实施例，其相较于现存的方法提供一或更多的改善。在一实施例中，半导体装置的制造方法包含在基底上方形成第一导电特征部件，在第一导电特征部件上方形成介电层，在介电层中形成沟槽。沟槽在其下部具有第一宽度且在其上部具有第二宽度，且第二宽度大于第一宽度，第一导电特征部件在沟槽中暴露出来。此方法也包含在沟槽中形成第一阻挡层，第一阻挡层具有设置于介电层上方的第一部分和设置于第一导电特征上方的第二部分。此方法也包含实施热处理将第一阻挡层的第一部分转换成第二阻挡层，在沟槽中暴露出第一导电特征部件，且第二阻挡层的一部分设置于介电层上方，并在沟槽中形成第二导电特征部件。
在另一实施例中，半导体装置的制造方法包含在设置于基底上的第一导电特征部件上方形成介电层，在介电层中形成沟槽，沟槽在其上部具有第一宽度且在其下部具有第二宽度，第一宽度大于第二宽度，第一导电特征部件在沟槽中暴露出来。此方法也包含在沟槽中形成第一阻挡层，第一阻挡层的第一部分沿着介电层定义的沟槽的侧壁表面形成，且第一阻挡层的第二部分沿着第一导电特征部件定义的沟槽的底部表面形成。此方法也包含将第一阻挡层的第一部分转换成第二阻挡层，第二阻挡层由不同于第一阻挡层的材料形成。此方法也包含在沟槽中暴露出第一导电特征部件，且第二阻挡层的一部分设置于介电层上方，并在沟槽中形成第二导电特征部件。
在另一实施例中，半导体装置包含第一导电特征部件设置于基底上方，第二导电特征部件设置于第一导电特征部件上方，第二导电特征部件具有第一宽度的上部和第二宽度的下部，第二宽度与第一宽度不同，下部物理性接触第一导电特征部件的顶部。此装置也包含第一阻挡层沿着第二导电特征部件的侧壁设置，介电层沿着第一阻挡层设置，介电层物理性接触第一阻挡层远离第二导电特征部件的一侧。
前述内容概述了许多实施例的特征，使本技术领域中技术人员可以从各个方面更佳地了解本公开。本技术领域中技术人员应可理解，且可轻易地以本公开为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本公开的发明精神与范围。在不背离本公开的发明精神与范围的前提下，可对本公开进行各种改变、置换或修改。

Claims (20)

1.一种半导体装置的制造方法，包括:
在一基底上方形成一第一导电特征部件；
在该第一导电特征部件上方形成一介电层；
在该介电层中形成一沟槽，其中该沟槽在其下部具有一第一宽度且在其上部具有一第二宽度，其中该第二宽度大于该第一宽度，其中该第一导电特征部件在该沟槽中暴露出来；
在该沟槽中形成一第一阻挡层，其中该第一阻挡层具有设置于该介电层上方的一第一部分和设置于该第一导电特征部件上方的一第二部分；
实施一热处理将该第一阻挡层的该第一部分转换成一第二阻挡层；
在该热处理之后，通过移除该第一阻挡层的该第二部分，在该沟槽中暴露出该第一导电特征部件，且该第二阻挡层的一部分设置于该介电层上方；以及
在暴露出该第一导电特征部件之后，在该沟槽中形成一第二导电特征部件。
2.如权利要求1所述的半导体装置的制造方法，其中在该介电层中形成该沟槽的步骤包含通过一第一微影工艺和一蚀刻工艺形成该沟槽的该上部。
3.如权利要求2所述的半导体装置的制造方法，其中在该介电层中形成该沟槽的步骤还包含在形成该沟槽的该上部之后，通过一第二微影工艺形成该沟槽的该下部。
4.如权利要求1所述的半导体装置的制造方法，其中在该沟槽中形成该第二导电特征部件的步骤包含通过一无电电镀沉积工艺在该沟槽的该下部中沉积一第一铜层，其中该第一铜层物理性接触该第一导电特征部件。
5.如权利要求4所述的半导体装置的制造方法，其中在该沟槽中形成该第二导电特征部件的步骤还包含通过一非无电电镀沉积工艺在该沟槽的该上部沉积一第二铜层。
6.如权利要求1所述的半导体装置的制造方法，其中在该沟槽中形成该第一阻挡层的步骤包含在该沟槽中形成一氮化锰(MnN)层。
7.如权利要求6所述的半导体装置的制造方法，其中实施该热处理将该第一阻挡层的该第一部分转换成该第二阻挡层的步骤包含将该氮化锰层转换成MnSixOyNz层，其中x代表硅成分的原子比例，y代表氧成分的原子比例，且z代表氮成分的原子比例。
8.如权利要求1所述的半导体装置的制造方法，其中暴露出的该沟槽中的该第一导电特征部件的步骤包含通过实施一包含酸的湿蚀刻工艺将该第一阻挡层的该第二部分移除。
9.如权利要求1所述的半导体装置的制造方法，其中在该沟槽中形成该第一阻挡层的步骤包含沿着该介电层定义的该沟槽的一侧壁表面形成该第一部分，并沿着该第一导电特征部件定义的该沟槽的一底部表面形成该第二部分。
10.一种半导体装置的制造方法，包括:
在设置于一基底上的一第一导电特征部件上方形成一介电层；
在该介电层中形成一沟槽，其中该沟槽在其上部具有一第一宽度且在其下部具有一第二宽度，其中该第一宽度大于该第二宽度，其中该第一导电特征部件在该沟槽中暴露出来；
在该沟槽中形成一第一阻挡层，其中该第一阻挡层的一第一部分沿着该介电层定义的该沟槽的一侧壁表面形成，且该第一阻挡层的一第二部分沿着该第一导电特征部件定义的该沟槽的一底部表面形成；
将该第一阻挡层的该第一部分转换成一第二阻挡层，其中该第二阻挡层由一不同于该第一阻挡层的材料形成；
在转换该第一阻挡层的该第一部分之后，通过实施一湿蚀刻工艺来移除该第一阻挡层的该第二部分，在该沟槽中暴露出该第一导电特征部件，且保留该第二阻挡层的一部分设置于该介电层上方；以及
在暴露出该第一导电特征部件之后，在该沟槽中形成一第二导电特征部件。
11.如权利要求10所述的半导体装置的制造方法，其中在该介电层中形成该沟槽的步骤包含通过一第一微影工艺和一蚀刻工艺形成该沟槽的该上部。
12.如权利要求11所述的半导体装置的制造方法，其中在该介电层中形成该沟槽的步骤还包含在形成该沟槽的该上部之后，通过一第二微影工艺形成该沟槽的该下部。
13.如权利要求10所述的半导体装置的制造方法，其中在该沟槽中形成该第二导电特征部件的步骤包含通过一无电电镀沉积工艺在该沟槽的该下部中沉积一第一金属层。
14.如权利要求13所述的半导体装置的制造方法，其中在该沟槽中形成该第二导电特征部件的步骤还包含通过一非无电电镀沉积工艺在该沟槽的该上部沉积一第二金属层，其中该第二金属层物理性接触该第一金属层。
15.如权利要求14所述的半导体装置的制造方法，其中该第一金属层为通过该无电电镀沉积工艺沉积的一铜层，且该第二金属层为通过该非无电电镀沉积工艺沉积的一铜层。
16.如权利要求10所述的半导体装置的制造方法，其中该第一阻挡层包含氮化锰，且其中该第二阻挡层包含MnSixOyNz，其中x代表硅成分的原子比例，y代表氧成分的原子比例，且z代表氮成分的原子比例。
17.如权利要求10所述的半导体装置的制造方法，其中在该沟槽中暴露出该第一导电特征部件的步骤包含通过实施包含一酸溶液的一湿蚀刻工艺将该第一阻挡层的该第二部分移除。
18.一种半导体装置，包括:
一第一导电特征部件，具有一顶表面；
一第二导电特征部件，设置于该第一导电特征部件上方，其中该第二导电特征部件具有一第一宽度的一上部和一第二宽度的一下部，该第二宽度与该第一宽度不同，其中该下部物理性接触该第一导电特征部件的一顶部；
一第一阻挡层，沿着该第二导电特征部件的侧壁设置，其中该第一阻挡层的一垂直部分设置于该第一导电特征部件上方并物理性接触该第一导电特征部件的该顶表面；以及
一介电层，沿着该第一阻挡层设置，其中该介电层物理性接触该第一阻挡层远离该第二导电特征部件的一侧。
19.如权利要求18所述的半导体装置，其中该第一导电特征部件包含铜，其中该第二导电特征部件包含铜，其中该第一阻挡层包含MnSixOyNz，其中x代表硅成分的原子比例，y代表氧成分的原子比例，且z代表氮成分的原子比例，其中该介电层包含氧化硅。
20.如权利要求18所述的半导体装置，其中该第二导电特征部件的该下部通过无电电镀沉积工艺形成。
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