CN106548928A - 用于射频应用的结构体和制造该结构体的方法 - Google Patents
用于射频应用的结构体和制造该结构体的方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 110
- 229920005591 polysilicon Polymers 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 47
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 45
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 40
- 229910052757 nitrogen Inorganic materials 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000013078 crystal Substances 0.000 description 11
- 238000001953 recrystallisation Methods 0.000 description 9
- 230000003313 weakening effect Effects 0.000 description 6
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 150000001721 carbon Chemical group 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910003828 SiH3 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
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- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
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Abstract
本发明涉及一种用于射频应用的结构体(100),包括:单晶衬底(1),直接位于所述单晶衬底(1)上的多晶硅层(2),在所述多晶硅层(2)上的有源层(3),其旨在容纳射频部件,所述结构体的特征在于,从所述多晶硅层(2)与所述单晶层的界面(I)延伸的所述多晶硅层(2)的至少第一部分(2a)包含浓度为2%~20%的位于所述多晶硅的晶界处的碳和/或氮原子。本发明还涉及一种制造该结构体的方法。
Description
技术领域
本发明涉及一种用于射频应用的结构体以及一种制造该结构体的方法。
背景技术
在射频(RF)应用中,不同类型的结构体可以用于制造RF部件。
在这些结构体之中,HR-SOI(“高电阻率绝缘体上硅”的首字母缩写)型衬底是令人感兴趣的。
在本文本中,“高电阻率”是指超过500欧姆·cm的电阻率。
绝缘体上硅(SOI)结构体依次包括硅基础衬底、介电(例如氧化物)层(通常称作“隐埋氧化物”(BOX)层)以及硅有源层。
为了改善射频(RE)开关所需的插入损耗、谐波畸变和隔离性能,由高电阻率基础衬底替代SOI衬底的硅基础衬底以便形成HR-SOI。
采用HR-SOI晶片用于RF应用实现了RF前端模块的单片集成。这导致更小的尺寸,更好的可靠性,改善的性能以及更低的系统成本。
尽管HR-SOI衬底很好地适用于2G和3G应用,但由于在Si/SiO2界面附近吸引自由载流子的固定氧化物电荷所致,它们受到在隐埋氧化物之下诱导的寄生表面导电(PSC)层的影响。
这使衬底有效电阻率大幅降低超过一个量级,限制了衬底在满足下一代性能需求方面的能力。
为了解决该固有局限并改善有效电阻率,在介电层和高电阻率基础衬底之间引入多晶硅层,从而在介电层下方提供富陷阱层以冻结PSC。
这些陷阱源自其中待制造RF部件的多晶硅层的晶界。
可以参见文献WO2012/127006。
图1示出了增强的HR-SOI结构体,其包括HR硅衬底1,其相继由多晶体硅(也称作“polysilicon”)层2’、氧化物层4以及形成衬底的有源层的单晶硅层3所覆盖。
该增强的HR-SOI结构体可以由Smart CutTM方法制造,所述方法包括以下步骤:
提供HR硅衬底,
在所述HR硅衬底上沉积多晶硅层,
提供单晶硅施主衬底,其包括界定待转移至HR硅衬底上的有源层的弱化区;所述弱化区可以通过将原子物种注入施主衬底中而获得,
在多晶硅衬底和单晶硅施主衬底的至少一个上形成介电层,例如通过氧化所述衬底中的至少一个,
将施主衬底和HR硅衬底键合,所述至少一个介电层位于键合界面处;所述至少一个介电层形成BOX层,
沿着弱化区分离施主衬底,由此将单晶有源层转移至HR硅衬底上。
由该方法得到的增强的HR-SOI结构体包括在BOX层和下方层之间的界面处的残留电荷,这是由于注入和氧化步骤所致。
所述电荷使稍后形成在有源层中或有源层上的部件的RF性能劣化。具体而言,所述电荷可以在相邻RF部件之间产生不希望的相互作用。
多晶硅层旨在捕获所述电荷并且因此避免它们对于RF性能的有害影响。实际上,多晶硅层的表面包括多个晶界,其实现在与BOX层的界面处捕获所述电荷。
关于该主题的其他信息可以在以下作者撰写的出版物中找到:D.Lederer、R.Lobet和J.-P.Raskin,“Enhanced high resistivity SOI wafer for RFapplications”、IEEE Intl.SOI Conf.,pp.46-47,2004、D.Lederer和J.-P.Raskin,“Newsubstrate passivation method dedicated to high resistivity SOI waferfabrication with increased substrate resistivity”,IEEE Electron DeviceLetters,vol.26,no.11,pp.805-807,2005、D.Lederer和J.-P.Raskin,“RF performanceof commercial SOI technology transferred onto a passivated HR siliconsubstrate”,IEEE Transactions on Electron Devices,vol.55,no.7,pp.1664-1671,2008以及D.C.Kerr等人的“Identification of RF harmonic distortion on Sisubstrates and its reduction using a trap-rich layer”,978-1-4244-1856-5/08,IEEE 2008IEEE。
然而,此种HR-SOI结构体的制造包括在高温下进行的一些步骤(例如在键合之后进行加热处理以便于增强键合强度)。所述高温引起多晶硅层的重结晶,下方的HR硅衬底(其是单晶的)充当该重结晶的晶种。换言之,重结晶从与HR单晶硅衬底的界面开始经多晶硅层向前传播。
当重结晶时,由于晶界数量的下降以及可能导致更大表面粗糙度和电荷捕获均匀性的较大晶粒尺寸变化,多晶硅层损失其捕获效率。
为了限制重结晶,可以将多晶硅层的厚度设置为足够高厚度,使得在高温步骤结束时,多晶硅层的至少一部分尚未重结晶。
此外,也需要大沉积厚度以便对在沉积之后必须抛光多晶硅层以便减小其粗糙度的事实进行补偿,所述抛光步骤移除了一定厚度的多晶硅层。
出于这些原因,在当前的增强HR-SOI结构体中,沉积的多晶硅层通常具有厚于2μm的厚度。
然而,增大多晶硅层的厚度具有缺点。实际上,当使用化学气相沉积(CVD)沉积多晶硅层时,多晶硅首先在HR硅衬底的表面上形成晶核,随后形成小晶粒,其随着多晶硅层厚度增长以基本上圆锥方式逐渐增大。由此,多晶硅层与HR硅衬底相反的表面包括比位于与HR硅衬底界面处的表面更小的晶界。因此,多晶硅层的厚度越大,晶界的数目越小,并且因此多晶硅层的捕获效率越小。
发明内容
本发明的目的在于克服上述问题,特别是减小多晶硅层的厚度而不使所述层的捕获效率劣化。
因此,本发明提供了一种用于射频应用的结构体,其包括:
单晶衬底,
直接位于单晶衬底上的多晶硅层,
在多晶硅层上的有源层,其旨在容纳射频部件,
所述结构体的特征在于,从多晶硅层与单晶层的界面延伸的多晶硅层的至少第一部分包含浓度为2%~20%的位于多晶硅的晶界处的碳和/或氮原子。
如以下将更详细说明的,在多晶硅的晶界处捕获碳和/或氮原子,这减缓了重结晶动力学。
这允许减小多晶硅层的厚度,同时仍然避免了所述层在加热处理结束时的完全重结晶。
这种厚度减小的多晶硅层在与单晶衬底相反的表面处包括更大量的晶界,并且因此比更厚的层更高效地捕获存在于所述表面处的电荷。此外,多晶硅的更小厚度引起有限的表面粗糙度,并因此使抛光步骤减至最少,并且使晶片上和晶片间的晶粒尺寸更均匀。
根据一个实施方式,整个多晶硅层含有碳和/或氮原子。
在该情形中,多晶硅层的厚度为200nm~1000nm。
根据另一实施方式,多晶硅层还包括在含有碳和/或氮原子的第一部分上的不含碳和/或氮原子的第二部分。
“不含”指的是碳和/或氮原子的浓度小于0.5%。
在该情形中,多晶硅层的第一部分的厚度有利地为10nm~200nm。多晶硅层的整个厚度因此优选为20nm~500nm。
根据一个实施方式,单晶衬底包括电阻率大于500欧姆·cm的单晶硅、碳化硅和/或锗中的至少一种。
根据实施方式,有源层包括半导体材料、介电材料、铁电材料和子结构体中的至少一种,所述子结构体包括至少一个腔和在所述腔上的至少一个悬挂元件。
根据另一实施方式,所述结构体还包括在多晶硅层上的介电层,有源层位于所述介电层上。
本发明的另一目的涉及一种制造此种结构体的方法。
所述方法包括:
提供单晶衬底,
在所述单晶衬底上沉积多晶硅层,
提供施主衬底,其包括旨在容纳射频部件的有源层,
将单晶衬底与施主衬底键合以使得多晶硅层和有源层位于键合界面处,
将有源层转移至单晶衬底和多晶硅层上,
所述方法的特征在于,在位于与单晶衬底的界面处的多晶硅层的至少第一部分的沉积过程中,在所述第一部分中沉积碳和/或氮原子。
有利地,在反应器中通过低压化学气相沉积(LPCVD)沉积多晶硅层。
将含有碳和/或氮原子的气体引入LPCVD反应器中以形成至少第一部分。
根据实施方式,在整个多晶硅层的沉积过程中将所述气体引入LPCVD反应器。
多晶硅层的厚度因此优选为200nm~1000nm。
根据另一实施方式,在沉积第一部分之后,所述方法包括停止将含有碳和/或氮原子的气体引入LPCVD反应器中,并且进一步沉积多晶硅层的不含碳和/或氮的第二部分,第二部分中的碳和/或氮的浓度小于0.5%。
多晶硅层的第一区域的厚度因此优选为10nm~200nm。
根据另一实施方式,所述方法还包括在多晶硅层上和/或在施主衬底的有源层上形成介电层。
附图说明
基于附图,本发明的其他特征和优点通过以下详述将变得显而易见,其中:
图1示出了包含多晶硅层的已知绝缘体上半导体结构体的剖视图;
图2示出了本发明实施方式的结构体的剖视图;
图3示出了本发明另一实施方式的结构体的剖视图;
图4A至图4D示出了本发明的结构体的制造方法的数个步骤。
应该注意的是附图可以不按照比例。
具体实施方式
图2示出了本发明第一实施方式的结构体100。
结构体100包括单晶衬底1。
单晶衬底可以是由一种材料制成的块状衬底,或者是由不同材料的堆叠制成的复合材料衬底,至少一种单晶材料位于衬底的主表面处。
有利地,单晶衬底由电阻率大于500欧姆·cm的单晶硅制成,尽管也可以选择其他材料。
例如,以下材料可以用于形成单晶衬底:硅、碳化硅、锗或者至少两种所述材料的组合。
多晶硅层2直接在单晶衬底1上延伸。“直接”意味着多晶硅与单晶衬底的材料在界面I处接触;具体而言,在单晶衬底1和多晶硅层2之间没有插入多晶或非晶层。
多晶硅层2包含碳和/或氮,意味着碳和/或氮原子位于多晶硅的晶界处。如下面将更详细说明的,所述碳和/或氮原子通常在多晶硅生长期间引入。
多晶硅层2中碳原子的浓度为2%~20%,这可以使用诸如俄歇电子能谱法或者二次离子质谱法等化学沉积表征技术来测定。
所述碳和/或氮浓度可以在层2的整个厚度上均匀,或者可以沿着层2的厚度改变。
多晶硅层2的厚度通常为200nm~1000nm,这比如图1所示的现有技术结构体薄得多。
诸如氧化物层等介电层4可以存在于多晶硅层2上。然而,该层4是可选的。
结构体100随后包括在多晶硅层2上(或者如果存在的话,在介电层4上)的旨在容纳射频部件的有源层。所述射频部件(未示出)可以因此形成在所述有源层3上或有源层3中。
有源层3可以包括半导体材料、介电材料、铁电材料和/或子结构体(包括至少一个腔和在所述腔上的至少一个悬挂元件)。
图3示出了本发明第二实施方式的结构体100。
由与图2中相同附图标记指代的元件是相同的并且因此无需再次详述。
与图2的结构体相比,图3的结构体包括由两个部分制成的多晶硅层2:从界面I延伸的第一部分2a,以及在第一部分2a上延伸的第二部分2b。
第一部分2a包含碳和/或氮。
多晶硅层的第一部分2a中的碳和/或氮的浓度为2%~20%。
所述第一部分2a的厚度为10nm~200nm。
相比之下,第二部分2b基本上不含碳和/或氮原子。假设相同的碳和/或氮原子可能已经污染了所述第二部分(例如在制造过程中),所述第二部分的碳和/或氮原子的浓度小于0.5%。
参照图4A至图4D描述图2和图3中所示的结构体的制造方法。
一方面,如图4A中所示,提供单晶衬底1。
将所述衬底引入反应器中以便进行多晶硅层的沉积。沉积技术有利地是低压化学气相沉积(LPCVD)或等离子体增强LPCVD。
为此,将硅烷(SiH4)、乙硅烷(Si2H6)或丙硅烷(Si3H8)以及甲烷(CH4)或甲基硅烷(SiH3CH3)引入反应器中。反应器中的温度通常为500℃~900℃。
与引入甲基硅烷或甲烷同时,将含有碳和/或氮的气体引入反应器中,以便将所述碳和/或氮原子引入正在生长的多晶硅层中。所述含有碳和/或氮气体的浓度为50sccm~300sccm。
由此,在单晶衬底1上获得包含碳和/或氮的多晶硅的第一部分2a。第一部分2a的厚度为10nm~200nm。
根据一个实施方式,多晶硅的生长与含有碳和/或氮的气体的引入一起可以继续,直至获得厚度为200nm~1000nm的最终多晶硅层。在该情形中,整个多晶硅层包含碳和/或氮(图4B,左侧)。
根据另选实施方式,在形成了第一部分2a之后停止引入含有碳和/或氮的气体,继续不含碳和/或氮的多晶硅的第二部分2b的生长直至获得总厚度为20nm~500nm的多晶硅层2(图4B,右侧)。该实施方式的优点在于,限制了引入反应器中碳的数量,并且因此使碳对反应器壁的污染减至最小。因此,相比于前述实施方式,反应器需要的清洁较少。
随后,从反应器中取出覆盖有多晶硅层的单晶衬底。
另一方面,如图4C中所示,提供包括旨在形成结构体的有源层的层3的施主衬底30。层3可以例如通过弱化区31而限制在施主衬底3中。弱化区可以通过注入物种或任何其他合适的工艺而形成。这些技术本质上是已知的并且无需在此更详细地描述。
介电层可以形成在多晶硅层和/或施主衬底的有源层上。例如,所述介电层可以通过多晶硅层和/或施主衬底的氧化而获得。举例来说,该介电层4在图4C中示出在施主衬底30的有源层3上。当多晶硅层和施主衬底上都形成介电层时,在键合之后,两个介电层一起形成隐埋介电层。
随后,如图4D中所示,将单晶衬底1和施主衬底30键合以使得多晶硅层2和有源层3(或者在适当的情况下,存在于层2和/或3上的介电层)位于键合界面处。
进行热处理以增强键合强度。该热处理的温度通常为100℃~1250℃并且其持续时间通常为10秒~2小时。
该处理的热预算应该足以引起多晶硅层从与形成重结晶的晶种的单晶衬底的界面开始的重结晶。然而,由于在与单晶衬底1接触的多晶硅层的至少一部分2a中存在碳原子,故重结晶动力学大幅减缓,原因在于碳原子阻挡了多晶硅的晶界。因此,即便含有碳和/或氮的多晶硅区域的厚度小至约100nm,多晶硅层2在热处理结束时也不会完全重结晶。
接着,通过移除施主衬底30的剩余部分32而将有源层3转移至单晶衬底1和多晶硅层2上。所述移除可通过以下方式进行:沿着弱化区31使施主衬底断裂(Smart CutTM方法),或者刻蚀和/或研磨施主衬底以便仅留下有源层3。
所得结构体示出在图2中(在多晶硅层在整个厚度上含有碳和/或氮的情形中)或者在图3中(在仅多晶硅层的第一部分包含碳和/或氮的情形中)。
在此种结构体中,多晶硅层2的厚度为200nm~1000nm(或者在参照图3所示的情形中甚至为10nm~500nm),其在与单晶衬底相反的表面处提供了比图1中的更厚层2’更大数目的晶界。结果,与更厚层相比,所述多晶硅层更高效地捕获了存在于所述表面处的电荷。
此外,因为多晶硅层2比图1中的层2’更薄,故其更不粗糙并且因此在与施主衬底键合之前需要更少抛光。由此,当形成多晶硅层时,应考虑到因抛光造成的材料损耗较小。
参考文献
WO2012/127006
D.Lederer,R.Lobet and J.-P.Raskin,“Enhanced high resistivity SOIwafers for RF applications,”IEEE Intl.SOI Conf.,pp.46-47,2004
D.Lederer and J.-P.Raskin,“New substrate passivation method dedicatedto high resistivity SOI wafer fabrication with increased substrateresistivity,”IEEE Electron Device Letters,vol.26,no.11,pp.805-807,2005
D.Lederer and J.-P.Raskin,“RF performance of a commercial SOItechnology transferred onto a passivated HR silicon substrate”,IEEETransactions on Electron Devices,vol.55,no.7,pp.1664-1671,2008
D.C.Kerr et al.,“Identification of RF harmonic distortion on Sisubstrates and its reduction using a trap-rich layer”,978-1-4244-1856-5/08,IEEE 2008IEEE.
Claims (17)
1.一种用于射频应用的结构体(100),其包括:
单晶衬底(1),
直接位于所述单晶衬底(1)上的多晶硅层(2),
在所述多晶硅层(2)上的有源层(3),其旨在容纳射频部件,
所述结构体的特征在于,从所述多晶硅层(2)与所述单晶层的界面(I)延伸的所述多晶硅层(2)的至少第一部分(2a)包含浓度为2%~20%的位于所述多晶硅的晶界处的碳和/或氮原子。
2.如权利要求1所述的结构体,其中,整个所述多晶硅层(2)含有碳和/或氮原子。
3.如权利要求2所述的结构体,其中,所述多晶硅层(2)的厚度为200nm~1000nm。
4.如权利要求1至3任一项所述的结构体,其中,所述多晶硅层(2)还包括在含有碳和/或氮原子的所述第一部分(2a)上的不含碳和/或氮原子的第二部分(2b),其中所述第二部分(2b)中的碳和/或氮的浓度小于0.5%。
5.如权利要求4所述的结构体,其中,所述多晶硅层的第一部分(2a)的厚度为10nm~200nm。
6.如权利要求4或5所述的结构体,其中,所述多晶硅层(2)的厚度为20nm~500nm。
7.如权利要求1至6任一项所述的结构体,其中,所述单晶衬底(1)包含碳化硅、锗和/或电阻率大于500欧姆·cm的单晶硅中的至少一种。
8.如权利要求1至7任一项所述的结构体,其中,所述有源层(3)包含半导体材料、介电材料、铁电材料和下述子结构体中的至少一种,所述子结构体包括至少一个腔和在所述腔上的至少一个悬挂元件。
9.如权利要求1至8任一项所述的结构体,其中,所述结构体还包括在所述多晶硅层(2)上的介电层(4),所述有源层(3)位于所述介电层(4)上。
10.一种制造用于射频应用的结构体(100)的方法,其包括:
提供单晶衬底(1),
在所述单晶衬底(1)上沉积多晶硅层(2),
提供施主衬底(30),其包括旨在容纳射频部件的有源层(3),
将所述单晶衬底(1)与所述施主衬底(30)键合以使得所述多晶硅层(2)和所述有源层(3)位于键合界面处,
将所述有源层(3)转移至所述单晶衬底(1)和所述多晶硅层(2)上,
所述方法的特征在于,在位于与所述单晶衬底的界面处的所述多晶硅层(2)的至少第一部分(2a)的沉积过程中,在所述第一部分(2a)中沉积碳和/或氮原子。
11.如权利要求10所述的方法,其中,在反应器中通过低压化学气相沉积(LPCVD)来沉积所述多晶硅层(2)。
12.如权利要求11所述的方法,其中,将含有碳和/或氮原子的气体引入LPCVD反应器中以形成至少所述第一部分(2a)。
13.如权利要求12所述的方法,其中,在整个所述多晶硅层(2)的沉积过程中将所述气体引入所述LPCVD反应器中。
14.如权利要求13所述的方法,其中,所述多晶硅层的厚度为200nm~1000nm。
15.如权利要求12所述的方法,其中,在沉积所述第一部分(2a)之后,所述方法包括:停止将含有碳和/或氮原子的气体引入所述LPCVD反应器中,并且进一步沉积所述多晶硅层(2)的不含碳和/或氮的第二部分(2b),所述第二部分(2b)中的碳和/或氮的浓度小于0.5%。
16.如权利要求15所述的方法,其中,所述多晶硅层(2)的第一区域(2a)的厚度为10nm~200nm。
17.如权利要求10至16任一项所述的方法,其中,所述方法还包括在所述多晶硅层(2)上和/或在所述施主衬底(30)的有源层(3)上形成介电层(4)。
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US10014311B2 (en) * | 2016-10-17 | 2018-07-03 | Micron Technology, Inc. | Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon |
US11063117B2 (en) * | 2017-04-20 | 2021-07-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure having carrier-trapping layers with different grain sizes |
FR3066858B1 (fr) * | 2017-05-23 | 2019-06-21 | Soitec | Procede pour minimiser une distorsion d'un signal dans un circuit radiofrequence |
FR3068506B1 (fr) * | 2017-06-30 | 2020-02-21 | Soitec | Procede pour preparer un support pour une structure semi-conductrice |
FR3079659B1 (fr) * | 2018-03-29 | 2020-03-13 | Soitec | Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree |
CN112236853A (zh) * | 2018-07-05 | 2021-01-15 | 索泰克公司 | 用于集成射频器件的衬底及其制造方法 |
FR3091011B1 (fr) * | 2018-12-21 | 2022-08-05 | Soitec Silicon On Insulator | Substrat de type semi-conducteur sur isolant pour des applications radiofréquences |
US11362176B2 (en) * | 2020-05-28 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company Limited | RFSOI semiconductor structures including a nitrogen-doped charge-trapping layer and methods of manufacturing the same |
US20220115226A1 (en) * | 2020-10-08 | 2022-04-14 | Okmetic Oy | Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure |
FR3116151A1 (fr) * | 2020-11-10 | 2022-05-13 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de formation d’une structure de piegeage d’un substrat utile |
CN112564662B (zh) * | 2020-12-11 | 2023-01-20 | 济南晶正电子科技有限公司 | 复合衬底及其制备方法、电子元器件 |
JP2023074067A (ja) * | 2021-11-17 | 2023-05-29 | 信越半導体株式会社 | 窒化物半導体基板及び窒化物半導体基板の製造方法 |
FR3133481A1 (fr) * | 2022-03-11 | 2023-09-15 | Soitec | Procédé de fabrication d’une structure multicouche de type semi-conducteur sur isolant |
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CN106548928B (zh) | 2019-09-24 |
KR102535458B1 (ko) | 2023-05-23 |
EP3144958A1 (en) | 2017-03-22 |
US9824915B2 (en) | 2017-11-21 |
US20170084478A1 (en) | 2017-03-23 |
JP2017059830A (ja) | 2017-03-23 |
SG10201607776YA (en) | 2017-04-27 |
TW201724467A (zh) | 2017-07-01 |
TWI702710B (zh) | 2020-08-21 |
EP3144958B1 (en) | 2021-03-17 |
KR20170033792A (ko) | 2017-03-27 |
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