TWI702710B - 用於射頻應用之結構及用於製備此結構之方法 - Google Patents

用於射頻應用之結構及用於製備此結構之方法 Download PDF

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TWI702710B
TWI702710B TW105129964A TW105129964A TWI702710B TW I702710 B TWI702710 B TW I702710B TW 105129964 A TW105129964 A TW 105129964A TW 105129964 A TW105129964 A TW 105129964A TW I702710 B TWI702710 B TW I702710B
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single crystal
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賓雁 阮
克里斯多夫 馬拉維里
西楠 構堤皮里
安東尼 M. 密西歐尼
阿萊恩 杜瓦雷特
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法商索泰克公司
美商派瑞格恩半導體有限公司
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Abstract

本發明係有關於一種用於射頻應用之結構，其包含： - 一單晶基材， - 一多晶矽層，其係直接位於單晶基材上， - 一活性層，其係於多晶矽層上，意在承接射頻組件， 特徵在於自多晶矽層與單晶層之界面延伸之多晶矽層的至少一第一部份含有位於多晶矽的顆粒邊界處之碳及/或氮原子，其係包含2%與20%間之濃度。 本發明進一步係有關於一種用於製備此一結構之方法。

Description

用於射頻應用之結構及用於製備此結構之方法
發明領域 本發明係有關於一種用於射頻應用之結構及一種用於製備此結構之方法。
發明背景 於射頻(RF)應用，不同型式之結構可被用於製造RF組件。
於此等結構中，HR-SOI(“高電阻率絕緣層上覆矽”之縮寫字)型式之基材係受注意。
於本文中，”高電阻率”意指多於500 Ohm.cm之電阻率。
一絕緣層上覆矽(SOI)結構依序包括一矽基底基材、一介電(氧化物)層(通常稱為”埋藏氧化物”(BOX)層)，及一矽活性層。
為改善射頻(RF)開關所需之插入損耗、諧波失真，及隔離性能，一SOI基材之矽基底基材係以一高電阻率基底基材替代，以便形成一HR-SOI。
採用HR-SSOI晶圓用於RF應用已能使RF前端模組單石積體化。此導致較小尺寸、較佳可靠性、改良性能，及較低系統成本。
雖然HR-SOI基材係適於2G及3G應用，但由於固定氧化物電荷 吸引接近Si/SiO2界面之游離載體，其等遭受於埋藏氧化物下誘發之寄生表面導電(PSC)層。
此使基材有效電阻率戲劇性地降低一級數值，限制基材符合用於下一代之性能需求的能力。
為解決此固有限制及改良有效電阻率，一多晶矽層被引入介 電層與高電阻率基底基材之間，以於介電層下提供用以凍結PSC之一多陷阱層。
此等陷阱源自多晶矽層之顆粒邊界，RF組件係於其間製成。
可參考文獻WO 2012/127006。
圖1顯示一增強式HR-SOI結構，其包含一HR矽基材1，其係依序以一多晶矽(亦稱為”多矽”)層2’、一氧化物層4，及形成基材之活性層的一單晶矽層3覆蓋。
此一增強式HR-SOI結構可以 Smart Cut™方法製造，其包含下列步驟： -提供一HR矽基材， -使一多晶矽層沉積於該HR矽基材上， 提供一單晶矽供體基材，其包含一弱化區，其界定將被轉移至HR矽基材上之活性層；該弱化區可藉由使原子物種植入供體基材內而獲得； -於多晶矽基材及單晶供體基材之至少一者上形成一介電層，例如，藉由使該等基材之至少一者氧化， -使供體基材與HR矽基材結合，此至少一介電層係於結合界面處；該至少一介電層形成BOX層， -使供體層材沿著弱化區脫離，藉此，使單晶活性層轉移至HR矽基材上。
自此方法造成之此增強式HR-SOI結構於BOX層與底下層間之界面處含有殘餘電荷，此係由於植入及氧化步驟。
該等電荷使其後於活性層內或其上形成之組件的RF性能退化。特別地，該等電荷會使相鄰RF組件間產生非所欲交互作用。
多晶矽層係意欲捕捉該等電荷，且因此避免RF性能之不利作用。事實上，多晶矽層之表面包含複數個顆粒邊界，此等能捕捉於與BOX層之界面處的該等電荷。
有關於此主題之進一步資訊可於由下述所寫之出版物中發現， D. Lederer、R. Lobet及J.-P. Raskin，“Enhanced high resistivity SOI wafers for RF applications”，IEEE Intl. SOI Conf. ，46-47頁，2004；D. Lederer及J.-P. Raskin，“New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity”，IEEE Electron Device Letters ，第26刪，編號11，805-807頁，2005；D. Lederer及J.-P. Raskin，“RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate”，IEEE Transactions on Electron Devices，第55冊，編號7，1664-1671頁，2008；及D. C. Kerr等人，“Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer”，978-1-4244-1856-5/08，IEEE 2008 IEEE。
但是，此一HR-SOI結構之製備涉及於高溫實行之某些步驟(例如，一熱處理係於結合後實行，以便強化結合強度)。該高溫誘發多晶矽層再結晶，底下之HR矽基材-其係單晶-作為此再結晶之晶種。換言之，一再結晶前端係自與HR單晶矽基材之界面擴散通過多矽層。
當再結晶時，多矽層損失其捕捉效率，其係由於顆粒邊界數量下降及較大顆粒尺寸變化，此等會造成較大表面粗糙度及電荷捕捉均一性。
為限制再結晶，多矽層之厚度可被設定為一足夠高之厚度，使得於高溫步驟結束時，至少一部份之多矽層尚未再結晶。
此外，亦需要一大沉積厚度補償多矽層需於沉積後拋光以便降低其粗糙度之事實，該拋光步驟移除一特定厚度之多矽層。
因為此等原因，於現今之增強式HR-SOI結構，沉積之多矽層典型上具有比2 µm更厚之厚度。
但是，增加多矽層厚度具有缺點。事實上，當多矽層使用化學蒸氣沉積(CVD)而沉積時，多矽係先於HR矽基材之表面上形成核，然後，形成小顆粒，其於多矽層之厚度生長時以一實質上錐形方式不停地變化。因此，多矽層之與HR矽基材相對之表面包含比位於與HR矽基材之界面處的表面更少之顆粒邊界。因此，多矽 層厚度愈大，顆粒邊界數量愈小，且因此 多矽層之捕捉效率愈小。
發明簡要說明 本發明之一目的係克服上述問題，且特別係容許降低多晶矽層之厚度，且不會使該層之捕捉效率退化。
因此，本發明提供一種用於射頻應用之結構，其包含： - 一單晶基材， - 一多晶矽層，其係直接位於單晶基材上， - 一活性層，其係於多晶矽層上，意在承接射頻組件， 該結構特徵在於自多晶矽層與單晶層之界面延伸之多晶矽層的至少一第一部份含有位於多晶矽的顆粒邊界處之碳及/或氮原子，其係包含2%與20%間之濃度。
如下將更詳細解釋般，碳及/或氮原子係於多晶矽之顆粒邊界被捕捉，此減慢再結晶動力學。
此容許降低多矽層之厚度，同時仍能避免於熱處理結束時該層完全再結晶。
具有降低厚度之此一多矽層於與單晶基材相對之表面處包含較大數量之顆粒邊界，且因此比一較厚之層更有效率地捕捉存在於該表面處之電荷。此外，此多矽之較小厚度誘發一有限的表面粗糙度，且因此使拋光步驟達最小，且於晶圓及晶圓到晶圓上更均一顆粒尺寸。
依據一實施例，整個多晶矽層含有碳及/或氮原子。
於此情況，多晶矽層之厚度範圍係從200至1000 nm。
依據另一實施例，多晶矽層進一步包含無碳及/或氮原子之一第二部份，其係於含有碳及/或氮原子之第一部份上。
以“無”係意指碳及/或氮原子之濃度係少於0.5%。
於此情況，多晶矽層之第一部份的厚度有利地範圍係從10至200 nm。多晶矽層之整個厚度因而較佳地係範圍從20至500 nm。
依據一實施例，單晶基材包含下列之至少一者：具有大於500 Ohm.cm之電阻的單晶矽、碳化矽，及/或鍺。
依據一實施例，活性層包含下列之至少一者：一半導材料、一介電材料、一鐵電材料，及包含至少一孔洞及於該孔洞上之至少一懸浮元素的一次結構。
依據另一實施例，此結構進一步包含於多晶矽層上之一介電層，活性層係於該介電層上。
本發明之另一目的係有關於一種用於製備此一結構之方法。
該方法包含： - 提供一單晶基材， - 於該單晶基材上沉積一多晶矽層， - 提供一供體基材，其包含一活性層，其係意在承接射頻組件， - 使單晶基材與供體基材連接，使得多晶矽層與活性層係於此結合界面處， - 使活性層轉移至單晶基材及多晶矽層上， 該方法特徵在於在沉積位於與單晶基材之界面處的多晶矽層之至少一第一部份期間，碳及/或原子係沉積於該第一部份。
有利地，多晶矽層係於一反應器中藉由低壓化學蒸氣沉積(LPCVD)而沉積。
含有碳及/或氮原子之一氣體被引入LPCVD反應器中形成至少此第一部份。
依據一實施例，該氣體係於沉積整個多晶矽層期間引入LPCVD反應器中。
多晶矽層之厚度因此較佳係範圍從200至1000 nm。
依據另一實施例，於第一部份已沉積後，此方法包含停止使含有碳及/或氮原子之氣體引入LPCVD反應器中，且進一步沉積多晶層之一無碳及/或氮之第二部份，第二部份中之碳及/或氮之濃度係少於0.5%。
多晶矽層之第一部份的厚度因此較佳係範圍從10至200 nm。
依據另一實施例，此方法進一步包含於多晶矽層上及/或於供體基材之活性層上形成一介電層。
發明實施例之詳細說明 圖2例示依據本發明第一實施例之一結構100。
結構100包含一單晶基材1。
單晶基材可為由單一材料製成之一大塊基材，或由不同材料之一堆疊物製成之一複合基材，至少一單晶材料位於基材之一主要表面。
有利地，單晶基材係由具有大於500 Ohm.cm之電阻的單晶矽製成，即使其它材料可被選擇。
例如，下列材料可用以形成單晶基材：矽、碳化矽、鍺，或該等材料之至少二者的組合。
一多晶矽層2係於單晶基材1上直接延伸。以“直接”係意指多晶矽係於界面I與單晶基材之材料接觸；特別地，無多晶或非結晶層被插入單晶基材1與多晶矽層2之間。
多晶矽層2含有碳及/或氮，意指碳及/或氮係位於多晶矽之顆粒邊界。如下將更 詳細解釋般，該碳及/或氮原子典型上係於多矽生長期間被引入。
多矽層2中之碳原子的濃度係於2–20%範圍，其可使用化學組成特徵化技術判定，諸如，歐格電子光譜術(Auger Electron Spectroscopy)或二次離子質譜術(Secondary Ion Mass Spectrometry)。
該碳及/或氮濃度於層2之厚度各處可為均一，或可沿著層2之厚度改變。
多晶矽層2之厚度範圍典型上係從200至1000 nm，其係遠比圖1例示之習知技術結構更薄。
一介電層4，諸如，一氧化物層，可存在於多矽層2上。但是，此層4係選擇性的。
然後，結構100包含位於多矽層2上(或若存在，位於介電層4上)之一活性層，其意在承接射頻組件。該等射頻組件(未被例示)可因此形成於該活性層3上或其內。
活性層3可包含一半導材料．一介電材料、一鐵電材料，及/或包含至少一孔洞及於該孔洞上之至少一懸浮元素的一次結構。
圖3例示依據本發明第二實施例之一結構100。
與圖2相同參考編號指定之元件係相同，因此，無需被再次詳細說明。
與圖2之結構相比，圖3之結構包含一多矽層2，其係由二部份製成：自界面I延伸之一第一部份2a，及於第一部份2a上延伸之一第二部份2b。
第一部份2a含有碳及/或氮。
多矽層之第一部份2a中之碳及/或氮原子之濃度係於2%-20%範圍。
該第一部份2a之厚度係範圍從10至200 nm。
相反地，第二部份2b係實質上無碳及/或氮原子。假設一些碳及/或氮原子可能已污染該第二部份，例如，於製備方法期間，該第二部份之碳及/或氮原子之濃度係少於0.5%。
於圖2及3例示之結構的一製備方法係參考圖4A至4D作說明。
一方面，如圖4A所示，提供一單晶基材1。
該基材被引入一反應器中，以便實行沉積多晶層。沉積技術有利地係低壓化學蒸氣沉積(LPCVD)或電漿增強式LPCVD。
為此，矽烷(SiH4 )、二矽烷(S2 H6 )或三矽烷(Si3 H8 )及甲烷(CH4 )或甲基矽烷(SiH3 CH3 )被引入反應器中。反應器中之溫度典型上範圍係從500°C至900°C。
與甲基矽烷或甲烷引入同時，含有碳及/或氮之一氣體被引入反應器中，以便使該碳及/或氮原子引至生長之多矽層內。該含碳及/或氮之氣體的濃度係包含於50與300 sccm之間。
因此，含有碳及/或氮之多矽之一第一部份2a於單晶基材1上獲得。此第一部份2a之厚度係包含10與200 nm之間。
依據一實施例，多矽之生長及含碳及/或氮之氣體的引入可實行至獲得具有200與1000間之厚度的最終多矽層為止。於此情況，整個多矽層含有碳及/或氮(圖4B，左)。
依據另一實施例，含碳及/或氮之氣體的引入係於第一部份2a形成後停止，且無碳及/或氮之多矽的一第二部份2b之生長係進行至獲得從20至500 nm之多矽層2的總厚度為止(圖4B，右)。此實施例的優點係引入反應器中之碳的量被限制，及反應器壁被碳弄污因而達最小。因此，反應器需要比先前實施例更少之清理。
然後，以多矽層覆蓋之單晶基材自反應器取得。
另一方面，如圖4C所示，提供一供體基材30，其包含意在形成此結構之活性層的一層3。此層3可於供體基材3中，例如，以一弱化區31分隔。弱化區可藉由植入物種或藉由任何其它適合方法形成。此等技術本身係已知，且無需於此更詳細地說明。
一介電層可於多矽層上及/或於供體基材之活性層上形成。例如，該介電層可藉由使多矽層及/或供體基材氧化而獲得。舉例而言，此一介電層4於圖4C中係例示位於供體基材30之活性層3上。當介電層於多矽層及供體基材二者上形成時，二介電層於結合後一起形成一埋藏介電層。
然後，如圖4D所示，使單晶基材1及供體基材30結合，使得多晶矽層2及活性層3(或若適合，存在於層2及/或3上之介電層)係位於結合界面。
實行一熱處理強化結合強度。此熱處理之溫度典型上係包含於100與1250°C之間，且其持續時間一般範圍係從10秒至2小時。
此一處理之熱積存會足以誘發一多矽層從與單晶基材之界面再結晶，其形成用於再結晶之一晶種。但是，由於在與單晶基材1接觸之多矽層的至少此部份2a中之碳原子存在，再結晶動力學係實質上顯示下降，因為碳原子阻斷多矽之顆粒邊界。因此，即使小到約100 nm之含碳及/或氮之多矽區的厚度，多矽層2於熱處理結束時不會完全再結晶。
然後，藉由移除供體基材30之剩餘物32使活性層3轉移至單晶基材1及多矽層2上。該移除可藉由使供體基材沿著弱化區31破裂(Smart Cut™ 法)，或藉由使供體基材蝕刻及/或研磨而實行，以便僅留下活性層3。
形成之結構係顯示於圖2(於其整個厚度上含有碳及/或氮之一多矽層的情況)或於圖3(僅多矽層之第一部份含有碳及/或氮之情況)。
於此一結構，多矽層2具有200至1000nm間之厚度(或甚至於參考圖3所述的情況之從10至500 nm)，其於與單晶基材相對之表面提供比如圖1中之一較厚層2’更大數量之顆粒邊界。因此，該多矽層比一更厚層更有效率地捕捉存在於該表面之電荷。
此外，因為多矽層2係比圖1之層2’更薄，其亦更不粗糙，且因此於與供體基材結合前需要較少拋光。因此，較小之由於拋光的材料損失於形成多矽層時被考量。
參考文獻 WO 2012/127006 D. Lederer、R. Lobet及J.-P. Raskin，“Enhanced high resistivity SOI wafers for RF applications”，IEEE Intl. SOI Conf. ，46-47頁，2004 D. Lederer及J.-P. Raskin，“New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity”，IEEE Electron Device Letters ，第26冊，編號11，805-807頁，2005 D. Lederer及J.-P. Raskin，“RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate”，IEEE Transactions on Electron Devices，第55冊，編號7，1664-1671頁，2008 D. C. Kerr等人，“Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer”，978-1-4244-1856-5/08，IEEE 2008 IEEE
1‧‧‧HR矽基材 2’‧‧‧多晶矽層 3‧‧‧單晶矽層 4‧‧‧氧化物層 100‧‧‧結構 1‧‧‧單晶基材 2‧‧‧多晶矽層 3‧‧‧活性層 4‧‧‧介電層 I‧‧‧界面 2a‧‧‧第一部份 2b‧‧‧第二部份 30‧‧‧供體基材 31‧‧‧弱化區 32‧‧‧剩餘物
圖式簡要說明 本發明之進一步特徵及優點以所附圖式為基礎，自下列詳細說明會變得明顯，其中： -圖1顯示包含一多矽層之一已知的絕緣體上半導體結構之截面圖； -圖2顯示依據本發明一實施例之一結構的截面圖； -圖3顯示依據本發明另一實施例之一結構的截面圖； -圖4A至4D顯示依據本發明之一結構的製備方法之數個步驟。 注意此等圖式可能不是依比例。
100‧‧‧結構
1‧‧‧單晶基材
2‧‧‧多晶矽層
3‧‧‧活性層
4‧‧‧介電層
I‧‧‧界面

Claims (17)

  1. 一種用於射頻應用之結構，其包含：一單晶基材，一多晶矽層，其係直接位於該單晶基材上，一活性層，其係於該多晶矽層上，意在承接射頻組件，該結構之特徵在於，自該多晶矽層與該單晶層之界面延伸之該多晶矽層的至少一第一部份含有位於該多晶矽的顆粒邊界處之碳及/或氮原子，其係以2%與20%間之濃度所包含。
  2. 如請求項1之結構，其中，整個該多晶矽層含有碳及/或氮原子。
  3. 如請求項2之結構，其中，該多晶矽層之厚度範圍為從200至1000nm。
  4. 如請求項1至3中任一項之結構，其中，該多晶矽層進一步包含位於含有碳及/或氮原子之該第一部份上之一無碳及/或氮原子之第二部份，其中，該第二部份之碳及/或氮的濃度係少於0.5%。
  5. 如請求項4之結構，其中，該多晶矽層之該第一部份的厚度範圍為從10至200nm。
  6. 如請求項4之結構，其中，該多晶矽層之厚度範圍為從20至500nm。
  7. 如請求項1至3中任一項之結構，其中，該單晶基材包含下述之至少一者：具有大於500Ohm.cm的電阻之單晶矽、碳化矽，及/或鍺。
  8. 如請求項1至3中任一項之結構，其中，該活性層包含下述之至少一者：一半導材料、一介電材料、一鐵電材料，及包含至少一孔洞及於該孔洞上之至少一懸浮元素的一次結構 (substructure)。
  9. 如請求項1至3中任一項之結構，其中，該結構進一步包含一介電層，其係於該多晶矽層上，該活性層係於該介電層上。
  10. 一種用來製備用於射頻應用的結構之方法，其包含：提供一單晶基材，於該單晶基材上沉積一多晶矽層，提供一供體基材，其包含一活性層，該活性層意在承接射頻組件，使該單晶基材與該供體基材連接，使該得多晶矽層與該活性層係於該單晶基材與該供體基材之間的結合界面處，使該活性層轉移至該單晶基材及該多晶矽層上，該方法特徵在於，在沉積位於與該單晶基材之界面處的該多晶矽層之至少一第一部份的期間，碳及/或氮原子係沉積於該第一部份，該碳及/或氮原子係以2%與20%間之濃度所包含。
  11. 如請求項10之方法，其中，該多晶矽層係於一反應器中藉由低壓化學蒸氣沉積(LPCVD)而沉積。
  12. 如請求項11之方法，其中，含有碳及/或氮原子之一氣體被引入該LPCVD反應器中以形成至少該第一部份。
  13. 如請求項12之方法，其中，該氣體係於沉積整個該多晶矽層期間被引入該LPCVD反應器中。
  14. 如請求項13之方法，其中，該多晶矽層之厚度範圍為從200至1000nm。
  15. 如請求項12之方法，其中，於該第一部份已沉積後，該方法包含停止使含有碳及/或氮原子之該氣體引入該LPCVD反應器中，且進一步沉積該多晶層之一無碳及/或氮之第二部 份，該第二部份中之碳及/或氮之濃度係少於0.5%。
  16. 如請求項15之方法，其中，該多晶矽層之該第一部份的厚度範圍為從10至200nm。
  17. 如請求項10至16中任一項之方法，其中，該方法進一步包含於該多晶矽層上及/或於該供體基材之該活性層上形成一介電層。
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US10014311B2 (en) * 2016-10-17 2018-07-03 Micron Technology, Inc. Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon
US11063117B2 (en) * 2017-04-20 2021-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure having carrier-trapping layers with different grain sizes
FR3066858B1 (fr) * 2017-05-23 2019-06-21 Soitec Procede pour minimiser une distorsion d'un signal dans un circuit radiofrequence
FR3068506B1 (fr) * 2017-06-30 2020-02-21 Soitec Procede pour preparer un support pour une structure semi-conductrice
FR3079659B1 (fr) * 2018-03-29 2020-03-13 Soitec Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree
CN112236853A (zh) * 2018-07-05 2021-01-15 索泰克公司 用于集成射频器件的衬底及其制造方法
FR3091011B1 (fr) * 2018-12-21 2022-08-05 Soitec Silicon On Insulator Substrat de type semi-conducteur sur isolant pour des applications radiofréquences
US11362176B2 (en) * 2020-05-28 2022-06-14 Taiwan Semiconductor Manufacturing Company Limited RFSOI semiconductor structures including a nitrogen-doped charge-trapping layer and methods of manufacturing the same
US20220115226A1 (en) * 2020-10-08 2022-04-14 Okmetic Oy Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure
FR3116151A1 (fr) * 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de formation d’une structure de piegeage d’un substrat utile
CN112564662B (zh) * 2020-12-11 2023-01-20 济南晶正电子科技有限公司 复合衬底及其制备方法、电子元器件
JP2023074067A (ja) * 2021-11-17 2023-05-29 信越半導体株式会社 窒化物半導体基板及び窒化物半導体基板の製造方法
FR3133481A1 (fr) * 2022-03-11 2023-09-15 Soitec Procédé de fabrication d’une structure multicouche de type semi-conducteur sur isolant

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050106888A1 (en) * 2003-11-14 2005-05-19 Taiwan Semiconductor Manufacturing Co. Method of in-situ damage removal - post O2 dry process
US20100065914A1 (en) * 2008-09-15 2010-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a single metal that performs n and p work functions in high-k/metal gate devices
TW201101432A (en) * 2007-11-01 2011-01-01 Semiconductor Energy Lab Semiconductor substrate and method for manufacturing the same, and method for manufacturing semiconductor device
TW201241877A (en) * 2010-12-24 2012-10-16 Io Semiconductor Inc Trap rich layer for semiconductor devices
TW201436046A (zh) * 2013-03-13 2014-09-16 Taiwan Semiconductor Mfg 射頻裝置及射頻裝置之製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914046A (en) * 1989-02-03 1990-04-03 Motorola, Inc. Polycrystalline silicon device electrode and method
CN1226774C (zh) * 2003-08-11 2005-11-09 中国科学院上海技术物理研究所 含氧化多孔硅的低阻硅衬底及其制备
US20070202360A1 (en) * 2005-10-04 2007-08-30 Nitronex Corporation Gallium nitride material transistors and methods for wideband applications
FR2953640B1 (fr) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
US8536021B2 (en) * 2010-12-24 2013-09-17 Io Semiconductor, Inc. Trap rich layer formation techniques for semiconductor devices
FR2973158B1 (fr) 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
US8951896B2 (en) * 2013-06-28 2015-02-10 International Business Machines Corporation High linearity SOI wafer for low-distortion circuit applications
US9768056B2 (en) * 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
US10079170B2 (en) 2014-01-23 2018-09-18 Globalwafers Co., Ltd. High resistivity SOI wafers and a method of manufacturing thereof
FR3029682B1 (fr) 2014-12-04 2017-12-29 Soitec Silicon On Insulator Substrat semi-conducteur haute resistivite et son procede de fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050106888A1 (en) * 2003-11-14 2005-05-19 Taiwan Semiconductor Manufacturing Co. Method of in-situ damage removal - post O2 dry process
TW201101432A (en) * 2007-11-01 2011-01-01 Semiconductor Energy Lab Semiconductor substrate and method for manufacturing the same, and method for manufacturing semiconductor device
US20100065914A1 (en) * 2008-09-15 2010-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a single metal that performs n and p work functions in high-k/metal gate devices
TW201241877A (en) * 2010-12-24 2012-10-16 Io Semiconductor Inc Trap rich layer for semiconductor devices
TW201436046A (zh) * 2013-03-13 2014-09-16 Taiwan Semiconductor Mfg 射頻裝置及射頻裝置之製造方法

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