CN106537601A - 晶体管 - Google Patents
晶体管 Download PDFInfo
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- CN106537601A CN106537601A CN201580024522.8A CN201580024522A CN106537601A CN 106537601 A CN106537601 A CN 106537601A CN 201580024522 A CN201580024522 A CN 201580024522A CN 106537601 A CN106537601 A CN 106537601A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 133
- 238000010276 construction Methods 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 49
- 239000003989 dielectric material Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- 239000000203 mixture Substances 0.000 claims description 18
- 229910052732 germanium Inorganic materials 0.000 claims description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 7
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 7
- 239000000758 substrate Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
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- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 150000001247 metal acetylides Chemical class 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- PFNQVRZLDWYSCW-UHFFFAOYSA-N (fluoren-9-ylideneamino) n-naphthalen-1-ylcarbamate Chemical compound C12=CC=CC=C2C2=CC=CC=C2C1=NOC(=O)NC1=CC=CC2=CC=CC=C12 PFNQVRZLDWYSCW-UHFFFAOYSA-N 0.000 description 1
- WUPHOULIZUERAE-UHFFFAOYSA-N 3-(oxolan-2-yl)propanoic acid Chemical compound OC(=O)CCC1CCCO1 WUPHOULIZUERAE-UHFFFAOYSA-N 0.000 description 1
- IGPFOKFDBICQMC-UHFFFAOYSA-N 3-phenylmethoxyaniline Chemical compound NC1=CC=CC(OCC=2C=CC=CC=2)=C1 IGPFOKFDBICQMC-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000006011 Zinc phosphide Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- FSIONULHYUVFFA-UHFFFAOYSA-N cadmium arsenide Chemical compound [Cd].[Cd]=[As].[Cd]=[As] FSIONULHYUVFFA-UHFFFAOYSA-N 0.000 description 1
- 229910052980 cadmium sulfide Inorganic materials 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 230000001419 dependent effect Effects 0.000 description 1
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- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- HOKBIQDJCNTWST-UHFFFAOYSA-N phosphanylidenezinc;zinc Chemical compound [Zn].[Zn]=P.[Zn]=P HOKBIQDJCNTWST-UHFFFAOYSA-N 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- GGYFMLJDMAMTAB-UHFFFAOYSA-N selanylidenelead Chemical compound [Pb]=[Se] GGYFMLJDMAMTAB-UHFFFAOYSA-N 0.000 description 1
- 238000005987 sulfurization reaction Methods 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229940048462 zinc phosphide Drugs 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H10B12/05—Making the transistor
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- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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Abstract
一些实施例包含在第一半导体材料上具有第二半导体材料的构造。归因于所述第一及第二半导体材料的不同晶格特性,所述第二半导体材料接近所述第一半导体材料的区域具有应变。晶体管栅极向下延伸到所述第二半导体材料中。栅极电介质材料是沿着所述晶体管栅极的侧壁及底部。源极/漏极区域是沿着所述晶体管栅极的所述侧壁,且所述栅极电介质材料处于所述源极/漏极区域与所述晶体管栅极之间。沟道区域在所述源极/漏极区域之间延伸且处于所述晶体管栅极的所述底部下方。所述沟道区域中的至少一些处于所述应变区域内。
Description
技术领域
本发明涉及晶体管、存储器阵列及半导体构造。
背景技术
晶体管通常用于集成电路中且贯穿存储器、逻辑等等可具有许多应用。例如,晶体管可用于电阻式随机存取存储器(RRAM)阵列、动态随机存取存储器(DRAM)阵列等等中。
集成电路制造的持续目标是创造更高的集成度,且因此减小现有组件的尺寸及间隔。归因于较小的沟道效应及其它复杂性,减小晶体管的尺寸变得越来越难。
晶体管性能可通过众多度量表征,其包含(例如)驱动电流(即,流经接通状态的晶体管的电流(Ion))。在一些应用中,将需开发相对于常规晶体管具有一或多个经改进度量(例如,增强驱动电流)的晶体管。
附图说明
图1到4是半导体构造的包括实例实施例晶体管的区域的概略横截面图。
图5A及5B分别是实例实施例存储器阵列的区域的概略横截面侧视图及概略俯视图。图5A是沿着图5B的横截面b-b’。
具体实施方式
一些实施例包含具有在应变半导体材料内延伸的沟道区域的晶体管。应变半导体材料可改进沟道区域内的电子迁移率且由此改进驱动电流。晶体管可用于凹入存取装置中,且在一些实施例中,可用于掩埋凹入存取装置(BRAD)中。参考图1到5描述实例实施例。
参考图1,构造10包括支撑于半导体基座12上的凹入晶体管14。
基座12可包括半导体材料,且可(例如)包括单晶硅、基本上由或由单晶硅组成。在一些实施例中,基座12可被视为包括半导体衬底。术语“半导体衬底”表示包括半导电材料的任何构造,其包含(但不限于)例如半导电晶片的块状半导电材料(其是单独的或在包括其它材料的组合件中)及半导电材料层(其是单独的或在包括其它材料的组合件中)。术语“衬底”指代任何支撑结构,其包含(但不限于)上文所描述的半导体衬底。在一些实施例中,基座12可对应于含有与集成电路制造相关联的一或多种材料的半导体衬底。所述材料中的一些可处于基座12的所展示区域下方及/或可横向邻近基座12的所展示区域;且可对应于(例如)耐火金属材料、屏障材料、扩散材料、绝缘体材料等等中的一或多者。
第一半导体材料16形成于基座12上,且第二半导体材料18形成于所述第一半导体材料上。所述第一及第二半导体材料彼此不同,且在所展示的实施例中,沿着界面19结合。归因于第一及第二半导体材料的不同晶格特性,在接近界面19的半导体材料中引发应变。应变区域可跨越从界面19向外延伸的体积散布。具体来说,应变区域可向上延伸实质距离到第二半导体材料18中,且也可向下延伸到第一半导体材料16中。术语“应变区域”用于指代含有因材料16与18之间的晶格失配引发的应变的区域。此类应变区域可(例如)相对于材料16及18结合的界面延伸20nm或更多到半导体材料18中。
在一些实施例中,第二半导体材料18可包括硅、基本上由或由硅组成;且第一半导体材料16可包括从周期表的IV族选择的除硅以外的元素(例如,碳、锗等等)。在一些实施例中,第一半导体材料16可包括与来自周期表的IV族的一或多个其它元素组合的硅;且可(例如)包括与碳及锗中的一者或两者组合的硅。例如,第一半导体材料可包括Si(1-x)Gex、基本上由或由Si(1-x)Gex组成;其中x处于从大约0.2到大约0.5的范围内。
在其中第一半导体材料16包括与来自周期表的IV族的一或多种其它材料组合的硅的实施例中,且在其中第二半导体材料18包括硅的实施例中,第一半导体材料可包括贯穿其整体的硅与其它组分的单一均匀比率,或可包括硅浓度相对于其它组分的浓度的梯度。例如,在一些实施例中,第一半导体材料16可包括与碳及锗中的一者或两者组合的硅,且硅的浓度可沿着梯度17减小使得相较于材料16内的较深处,接近界面19处存在更低的硅浓度。这可使得能够针对特定应用调整应变特性。
第一及第二半导体材料16及18可包括任何合适的材料;且在一些实施例中,第一半导体材料16可包括II/V族混合物(例如,磷化镉、砷化镉、磷化锌等等)、II/VI族混合物(例如,硒化镉、硫化镉、硒化锌、碲化锌等等)或IV/VI族混合物(例如,硒化铅(II族)、硫化锡、碲化铊锗等等);且第二半导体材料18可包括不同混合物,或可包括硅、基本上由或由硅组成。
第一半导体材料16可包括任何合适的厚度,且在一些实施例中可具有小于大约2μm的厚度;例如(举例来说)处于从大约1μm到大约2μm的范围内的厚度。
凹槽20延伸到第二半导体材料18中。晶体管栅极22在此类凹槽的底部上,且可被视为向下延伸到第二半导体材料18中。所述晶体管栅极包括栅极材料24。所述栅极材料可包括任何合适的组合物或组合物的组合;且在一些实施例中可包括以下各者中的一或多者、基本上由或由以下各者中的一或多者组成:各种金属(例如,钨、钛等等)、含有金属的组合物(例如,金属氮化物、金属碳化物、金属硅化物等等)及导电性掺杂半导体材料(例如,导电性掺杂硅、导电性掺杂锗等等)。
电绝缘材料26在凹槽20内且处于栅极22上。绝缘材料26可包括任何合适的组合物或组合物的组合;且在一些实施例中可包括氮化硅、基本上由或由氮化硅组成。
栅极22可被视为包括邻近绝缘材料26的顶面25、与顶面呈相对关系的底面27及侧壁表面29。
栅极电介质材料28沿着栅极22的底面27及侧壁表面29延伸。在所展示的实施例中,栅极电介质材料也沿着绝缘材料26的侧壁表面延伸;但在其它实施例中,栅极电介质材料可仅是沿着栅极22的表面。
栅极22可为字线的部分,所述字线相对于图1的横截面图延伸进出页面。
栅极22的底部27可被视为处于半导体材料18的中介区域30上,其中此类中介区域处于栅极与第一半导体材料16之间。中介区域可(例如)具有处于从大约10nm到大约20nm的范围内的厚度。由材料16及18的晶格失配引发的应变可传播完全通过中介区域30。
源极/漏极区域32及34是沿着栅极22的侧壁,且由栅极电介质材料28与栅极间隔开。源极/漏极区域可对应于半导体材料18的导电性掺杂区域,且使用虚线31概略说明源极/漏极区域的底部。源极/漏极区域的底部可为扩散边界,其中掺杂剂浓度减少到低于与源极/漏极区域相关联而非突变梯级的水平的水平。尽管两个源极/漏极区域被展示为延伸到大约彼此相同的深度,但在其它实施例中源极/漏极区域可相对于彼此延伸到不同深度。
在图1的实施例中,源极/漏极区域延伸到大约等于栅极22在半导体材料18内的深度的深度。在其它实施例中,如下文参考图2到4更详细所论述,源极/漏极区域可相对于栅极22的深度延伸到不同深度。
图1展示源极/漏极区域32及34上的导电区域36。在所说明的实施例中,此类导电区域包括第一导电材料38及第二导电材料40。导电材料38可包括(例如)金属硅化物(例如,硅化钛、硅化钴等等),且导电材料40可包括金属(例如,钨、钛等等)或含有金属的组合物(例如,金属碳化物、金属氮化物等等)。导电区域36可用于形成到源极/漏极区域32及34的电接触,且在其它实施例中可以任何其它合适的结构取代。
沟道区域42在源极/漏极区域32与34之间延伸,且处于晶体管栅极22的底部下方。由材料16及18的晶格失配所引发的应变可至少部分跨越中介区域30延伸,且具体来说可至少部分跨越沟道区域延伸。此可使得能够增强跨越沟道区域的电子迁移率,这可使得晶体管14能够具有比常规晶体管更高的驱动电流。在一些实施例中,沟道区域42整体可处于应变半导体材料内。
在一些实例实施例(例如,其中第二半导体材料18包括硅且第一半导体材料16包括Si(1-x)Gex(其中,例如x处于从大约0.2到大约0.5的范围内)的实施例)中,可使用压电电阻系数计算跨越中介区域30的应变:
在上文方程式中,μe(xx)、μ0、Sxx、Syy及Szz分别是x轴中具有应变的电子迁移率、无应力的电子迁移率及沿着x轴、y轴及z轴的沟道应力。所述方程式提供给n型MOSFET以辅助阅读者理解本发明,且将不限制本发明的任何方面,除非在所附权利要求书中明确陈述此方程式(如果有)。x轴及z轴的定向是相对于图1的构造展示的。
图1的实施例的优势在于:电子在沟道区域42内主要沿着x轴方向迁移,且不具有沿着z轴方向的实质迁移。因此,中介区域30内的应变对于沟道区域内的电子迁移率可具有实质影响。
沟道区域42可多数掺杂为与源极/漏极区域32及34相反的类型。例如,沟道区域42可为p型掺杂区域且源极/漏极区域32及34可为n型掺杂区域。在一些实施例中,沟道区域42可被掺杂到阈值电压(VT)植入水平,且源极/漏极区域32及34可被掺杂到轻掺杂扩散(LDD)植入水平。
图1的实施例包括晶体管,其中源极/漏极区域具有与晶体管栅极的底部大约共同延伸的底部。图2展示构造10a,其说明其中源极/漏极区域的底部延伸到晶体管栅极的底部下方的替代性实施例。具体来说,图2展示具有源极/漏极区域32及34的晶体管14a,源极/漏极区域32及34在半导体材料18内延伸的深度大于晶体管栅极22。在一些实施例中,中介区域30可具有处于从大约10nm到大约20nm的范围内的厚度,且源极/漏极区域32及34可延伸到比栅极22的深度大处于从大约5nm到大约10nm的范围内的量的深度。因此,源极/漏极区域32及34可延伸到是中介区域30的厚度的四分之三、是中介区域30的厚度的二分之一等等的深度。
在图2的实施例中,沟道区域42可完全处于半导体材料18的应变区域内,且沟道区域内的电子迁移率可为主要沿着x轴方向。因此,可充分实现上文参考图1所描述的优势以实现高驱动电流。
图3展示另一实例实施例晶体管。具体来说,图3展示包括具有深度小于栅极22的源极/漏极区域32及34的晶体管14b的构造10b。晶体管14b包括沟道区域42,沟道区域42沿着栅极22的底部27部分处于中介区域30内,但也沿着栅极22的侧壁29的最低部分延伸。相对于图1及2的晶体管14及14a,晶体管14b可具有两个缺点。首先,部分沟道区域42可延伸超过半导体材料18的应变区域。具体来说,半导体材料18的应变区域可涵盖中介区域30,但可或可不一直延伸到所说明的源极/漏极区域32及34的底部边界。如果部分沟道区域处于半导体材料18的应变区域外部,那么可仅由半导体材料18的应变区域内的沟道区域的部分而非由整个沟道区域来实现应变半导体材料内的增强电子迁移率的优势。晶体管14b的第二个缺点在于:沿着z轴方向且沿着x轴方向存在实质电子迁移,且相较于图1及2的其中电子迁移主要沿着x轴方向的晶体管14及14a,此可减少增强电子迁移率的优势。
尽管两个源极/漏极区域被展示为延伸到彼此相同的深度,但在其它实施例中源极/漏极区域可相对于彼此延伸到不同深度。例如,源极/漏极区域中的一者可延伸到至少等于晶体管栅极的深度的深度,且另一者可延伸到小于晶体管栅极的深度的深度。因此,沟道区域可不对称,其中沟道区域的一侧沿着栅极的侧壁延伸(如同图3的实施例)且另一侧不沿着侧壁延伸(如同图1或图2的实施例)。此类非对称沟道区域可具有介于图3的实施例与图1及2的实施例中间的性质及特性(例如,应变区域引发的驱动电流增强)。
即使相对于图1及2的实施例,图3的晶体管14b可具有缺点,但相对于常规晶体管,晶体管14b可仍具有增强驱动电流,且因此仍可为适于在一些应用中利用的经改进装置。
在一些实施例中,可修改跨越半导体材料16的上表面的形貌使得在其中源极/漏极区域延伸的深度小于晶体管的栅极的实施例中,沟道区域整体处于应变材料内。例如,图4展示包括与图3的晶体管14b类似的晶体管14c的构造10c,其中晶体管14c的源极/漏极区域32及34延伸的深度与栅极22不同。然而,界面19经配置以具有容器形状。此类容器形状与栅极22沿着底部27且沿着侧壁29的最低段的外周边互补。因此,沟道42是容器形的,且嵌套于界面19的容器形配置内。
在所展示的实施例中,沟道区域42沿着侧壁29的最低段与沿着栅极22的底部27具有大体上一致的厚度,但在其它实施例中沿着侧壁29可具有与沿着栅极的底部27不同的厚度。
在一些实施例中,可贯穿整个沟道区域,且具体来说贯穿沟道区域沿着侧壁29的部分且贯穿沿着栅极22的底部27的部分,保持沟道区域42内的应变大体上一致。因此,高电子迁移率可完全贯穿沟道区域42延伸,且即使源极/漏极区域32及34的深度小于栅极22,图4的晶体管14c的驱动电流仍可与图1及2的实施例的驱动电流相当。
在一些应用中,可将上文所描述的晶体管实施例并入存储器阵列(例如(举例来说)RRAM阵列、DRAM阵列等等)中。图5A及5B展示实例阵列60,其包括上文参考图1所描述的类型的多个大体上相同的晶体管14,(其中术语“大体上相同”表示在合理制造及测量公差内,晶体管相同)。源极/漏极区域被标记为图5A中的区域61,且与图1的区域32/34相同。
在所展示的实施例中,晶体管中的一些是“有源”晶体管且与电荷存储装置电耦合;且其它晶体管用于隔离区域。隔离区域用于使邻近有源晶体管中的一些彼此隔离。位线(未展示)可电耦合到有源晶体管的源极/漏极区域中的一些。有源晶体管的栅极22可为沿着字线,所述字线相对于图5A的横截面延伸进出页面。如在图5B的俯视图中所展示,浅沟槽隔离(STI)在正交于包括有源及隔离晶体管的沟槽的沟槽内延伸。
可将上文所论述的装置及结构并入电子系统中。此类电子系统可用于(例如)存储器模块、装置驱动器、电力模块、通信调制解调器、处理器模块及专用模块中,且可包含多层、多芯片模块。电子系统可为广泛范围的系统(例如(举例来说)时钟、电视、手机、个人计算机、汽车、工业控制系统、航空器等等)中的任一者。
除非另有指定,否则可使用现已知或尚待开发的任何合适的方法(其包含,例如原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)等等)形成本文所描述的各种材料、物质、组合物等等。
术语“电介质”及“电绝缘”两者都用于描述具有绝缘电性质的材料。在本发明中两个术语被视为同义。在一些实例中利用术语“电介质”,且在其它实例中利用术语“电绝缘”以在本发明内提供语言变化以简化所附权利要求书内的前置基础,且并非用于指示任何显著化学或电差异。
各种实施例在图式中的特定定向仅出于说明的目的,且在一些应用中实施例可相对于所展示的定向旋转。本文所提供的描述及所附权利要求书涉及在各种特征之间具有所描述的关系的任何结构,而无论结构是否处于图式的特定定向中或相对于此类定向旋转。
所附说明的横截面图仅展示横截面的平面内的特征,且不展示横截面的平面后的材料以便简化图式。
当结构在上文中被称作在另一结构“上”或“抵靠”另一结构时,其可直接在所述另一结构上或也可存在中介结构。相比之下,当结构被称作“直接在另一结构上”或“直接抵靠另一结构”时,不存在中介结构。当结构被称作“连接”或“耦合”到另一结构时,其可直接连接或耦合到所述另一结构,或可存在中介结构。相比之下,当结构被称作“直接连接”或“直接耦合”到另一结构时,不存在中介结构。
一些实施例包含半导体构造,所述半导体构造包括:第二半导体材料,其在第一半导体材料上,且归因于第一及第二半导体材料的不同晶格特性具有接近第一半导体材料的应变区域。晶体管栅极向下延伸到第二半导体材料中。栅极电介质材料是沿着晶体管栅极的侧壁及底部。源极/漏极区域是沿着晶体管栅极的侧壁,且栅极电介质材料处于源极/漏极区域与晶体管栅极之间。沟道区域在源极/漏极区域之间延伸且处于晶体管栅极的底部下方。沟道区域中的至少一些在应变区域内。
一些实施例包含半导体构造,所述半导体构造包括邻近第二半导体材料的第一半导体材料。归因于第一及第二半导体材料的不同晶格特性,第二半导体材料具有应变区域。晶体管栅极延伸到第二半导体材料中。第二半导体材料的中介区域处于晶体管栅极的底部与第一半导体材料之间。中介区域整体由应变区域涵盖。栅极电介质材料是沿着晶体管栅极的侧壁及底部。源极/漏极区域是沿着晶体管栅极的侧壁,且由栅极电介质材料与晶体管栅极间隔开。源极/漏极区域延伸到第二半导体材料中到至少大约等于晶体管栅极在第二半导体材料内的深度的深度。沟道区域在源极/漏极区域之间延伸且处于晶体管栅极的底部下方。
一些实施例包含半导体构造,所述半导体构造包括第一半导体材料及沿着界面结合所述第一半导体材料的第二半导体材料。归因于第一及第二半导体材料的不同晶格特性,第二半导体材料接近界面的区域具有应变。晶体管栅极延伸到第二半导体材料中。第二半导体材料的中介区域处于晶体管栅极的底部与第一半导体材料之间。中介区域整体由应变区域涵盖。栅极电介质材料是沿着晶体管栅极的侧壁及底部。源极/漏极区域是沿着晶体管栅极的侧壁,且由栅极电介质材料与晶体管栅极间隔开。源极/漏极区域延伸到第二半导体材料中到小于晶体管栅极在第二半导体材料内的深度的深度。沟道区域在源极/漏极区域之间延伸且处于晶体管栅极的底部下方。
Claims (33)
1.一种半导体构造,其包括:
第一半导体材料;
第二半导体材料,其在所述第一半导体材料上且归因于所述第一及第二半导体材料的不同晶格特性具有接近所述第一半导体材料的应变区域;
晶体管栅极,其向下延伸到所述第二半导体材料中;
栅极电介质材料,其是沿着所述晶体管栅极的侧壁及底部;
源极/漏极区域,其是沿着所述晶体管栅极的所述侧壁,所述栅极电介质材料处于所述源极/漏极区域与所述晶体管栅极之间;且
其中沟道区域在所述源极/漏极区域之间延伸且处于所述晶体管栅极的所述底部下方,所述沟道区域中的至少一些在所述应变区域内。
2.根据权利要求1所述的构造,其中所述源极/漏极区域在所述第二半导体材料内延伸到大约彼此相同的深度。
3.根据权利要求1所述的构造,其中所述源极/漏极区域在所述第二半导体材料内的深度至少与所述栅极相同。
4.根据权利要求1所述的构造,其中所述源极/漏极区域在所述第二半导体材料内的深度大于所述栅极。
5.根据权利要求1所述的构造,其中所述源极/漏极区域在所述第二半导体材料内的深度小于所述栅极。
6.根据权利要求5所述的构造,其中所述沟道区域是容器形且沿着所述晶体管栅极侧壁的最低段且沿着所述晶体管栅极的所述底部延伸;且其中所述第一与第二半导体材料结合的界面被配置为容器形,其中所述容器形沟道区域嵌套于所述容器形界面内。
7.根据权利要求1所述的构造,其中所述第一半导体材料包括锗且所述第二半导体材料包括硅。
8.根据权利要求1所述的构造,其中所述第一半导体材料包括锗及硅的混合物,且其中所述第二半导体材料包括硅。
9.根据权利要求1所述的构造,其中所述第一半导体材料包括锗及碳的混合物,且其中所述第二半导体材料包括硅。
10.根据权利要求1所述的构造,其中所述第一半导体材料包括II/VI族混合物、IV/VI族混合物或II/V族混合物。
11.根据权利要求10所述的构造,其中所述第二半导体材料包括硅。
12.根据权利要求1所述的构造,其中所述沟道区域是p型掺杂且所述源极/漏极区域是n型掺杂。
13.根据权利要求1所述的构造,其中所述沟道区域整体处于所述应变区域内。
14.根据权利要求1所述的构造,其中仅所述沟道区域的部分处于所述应变区域内。
15.根据权利要求1所述的构造,其中所述晶体管栅极及所述源极/漏极区域一起构成晶体管,且其中此晶体管是存储器阵列内许多大体上相同的晶体管中的一者。
16.一种半导体构造,其包括:
第一半导体材料;
第二半导体材料,其邻近所述第一半导体材料,且归因于所述第一及第二半导体材料的不同晶格特性具有接近所述第一半导体材料的应变区域;
晶体管栅极,其延伸到所述第二半导体材料中;
所述第二半导体材料的中介区域,其处于所述晶体管栅极的底部与所述第一半导体材料之间;所述中介区域整体由所述应变区域涵盖;
栅极电介质材料,其是沿着所述晶体管栅极的侧壁及所述底部;
源极/漏极区域,其是沿着所述晶体管栅极的所述侧壁,且由所述栅极电介质材料与所述晶体管栅极间隔开;所述源极/漏极区域延伸到所述第二半导体材料中到至少大约等于所述晶体管栅极在所述第二半导体材料内的深度的深度;且
其中沟道区域在所述源极/漏极区域之间延伸且处于所述晶体管栅极的所述底部下方。
17.根据权利要求17所述的构造,其中所述源极/漏极区域的所述深度大约等于所述晶体管栅极的所述深度。
18.根据权利要求17所述的构造,其中所述源极/漏极区域的所述深度大于所述晶体管栅极的所述深度。
19.根据权利要求19所述的构造,其中所述中介区域在所述晶体管栅极的所述底部与所述第一半导体材料的顶部之间具有处于从大约10纳米到大约20纳米的范围内的厚度,且其中所述源极/漏极区域在所述晶体管栅极的所述底部下方的深度处于从大约5纳米到大约10纳米的范围内。
20.根据权利要求17所述的构造,其中所述第一半导体材料包括锗且所述第二半导体材料包括硅。
21.根据权利要求17所述的构造,其中所述第一半导体材料包括锗及硅的混合物,且其中所述第二半导体材料包括硅。
22.根据权利要求22所述的构造,其中所述第一半导体材料包括硅浓度相对于锗浓度的梯度,且其中所述硅浓度随着到所述第二半导体材料的接近度增加而降低。
23.根据权利要求22所述的构造,其中所述第一半导体材料包括贯穿其整体硅对锗的单一均匀比率。
24.根据权利要求24所述的构造,其中所述第一半导体材料包括Si(1-x)Gex;其中x处于从大约0.2到大约0.5的范围内。
25.根据权利要求17所述的构造,其中所述第一半导体材料包括锗及碳的混合物,且其中所述第二半导体材料包括硅。
26.一种半导体构造,其包括:
第一半导体材料;
第二半导体材料,其在所述第一半导体材料上且沿着界面结合所述第一半导体材料;归因于所述第一及第二半导体材料的不同晶格特性,所述第二半导体材料接近所述界面的区域具有应变;
晶体管栅极,其延伸到所述第二半导体材料中;
所述第二半导体材料的中介区域,其处于所述晶体管栅极的底部与所述第一半导体材料之间;所述中介区域整体由所述应变区域涵盖;
栅极电介质材料,其是沿着所述晶体管栅极的侧壁与所述底部;
源极/漏极区域,其是沿着所述晶体管栅极的所述侧壁,且由所述栅极电介质材料与所述晶体管栅极间隔开;所述源极/漏极区域延伸到所述第二半导体材料中到小于所述晶体管栅极在所述第二半导体材料内的深度的深度;且
其中沟道区域在所述源极/漏极区域之间延伸且处于所述晶体管栅极的所述底部下方。
27.根据权利要求27所述的构造,其中所述沟道区域是容器形且沿着所述晶体管栅极侧壁的最低段且沿着所述晶体管栅极的所述底部延伸;且其中所述界面也是容器形,其中所述容器形沟道区域嵌套于所述容器形界面内。
28.根据权利要求28所述的构造,其中所述沟道区域沿着所述栅极的所述侧壁与沿着所述栅极的所述底部的厚度大体上一致。
29.根据权利要求27所述的构造,其中所述第二半导体材料包括硅。
30.根据权利要求30所述的构造,其中所述第一半导体材料包括锗及硅的混合物。
31.根据权利要求30所述的构造,其中所述第一半导体材料包括锗及碳的混合物。
32.根据权利要求30所述的构造,其中所述第一半导体材料包括II/VI族混合物、IV/VI族混合物或II/V族混合物。
33.根据权利要求27所述的构造,其中所述沟道的区域是沿着所述晶体管栅极的最低段且不在所述应变区域内。
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