CN106531844B - A kind of double-side cell edge not damaged partition method - Google Patents
A kind of double-side cell edge not damaged partition method Download PDFInfo
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- CN106531844B CN106531844B CN201611110157.5A CN201611110157A CN106531844B CN 106531844 B CN106531844 B CN 106531844B CN 201611110157 A CN201611110157 A CN 201611110157A CN 106531844 B CN106531844 B CN 106531844B
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000005192 partition Methods 0.000 title claims abstract description 37
- 238000009792 diffusion process Methods 0.000 claims abstract description 80
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052796 boron Inorganic materials 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 7
- 239000011574 phosphorus Substances 0.000 claims abstract description 7
- 238000003892 spreading Methods 0.000 claims abstract description 6
- 230000007480 spreading Effects 0.000 claims abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 229910004286 SiNxOy Inorganic materials 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 9
- 125000004437 phosphorous atom Chemical group 0.000 abstract description 6
- -1 region Chemical compound 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910004205 SiNX Inorganic materials 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010329 laser etching Methods 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
This application discloses a kind of double-side cell edge not damaged partition method, including：The dorsal edge of silicon chip after spreading and etching by front boron and side, the diffusion impervious layer of annular is made, wherein, the diffusion impervious layer of the dorsal edge of the silicon chip has predetermined width；In the circular region of the diffusion impervious layer of the silicon chip back side, carry out phosphorus diffusion and form n+ layers and PSG layers；Remove the diffusion impervious layer and the PSG layers.The double-side cell edge not damaged partition method that the application provides, can suppress the cross-diffusion of boron and phosphorus atoms edge region, realize not damaged edge isolation, and the problem of the process costs increase for avoiding the introducing of etching technics and bringing and edge current leakage.
Description
Technical field
The invention belongs to new and effective crystal silicon solar batteries technical field, more particularly to a kind of double-side cell edge without
Damage partition method.
Background technology
AT＆T Labs of the U.S. in 1954 prepares the single crystal silicon solar cell that first piece of conversion efficiency is 6% in the world,
By scientist's continuous exploration of 60 years, solar cell achieves huge breakthrough, and highest conversion efficiency has reached
46% (light-focusing multi-junction GaAs), and occupy the p-type crystal silicon solar battery of photovoltaic market for many years gradually show efficiency increase tired state,
The inferior positions such as light decay amplitude is excessive.Although being substituted with Ga, B is atom doped can avoid photo attenuation effect, therefrom it is caused compared with
Wide resistivity distribution and Fe element pollution problems, can still restrict the further raising of p-type battery efficiency.And N-type
Solar cell then has benefited from its high efficiency, the advantage of low decay, turns into study hotspot new in photovoltaic industry.In high-efficiency N-type skill
In terms of art, most typical representative is the IBC batteries of SunPower companies of the U.S. and the HIT batteries of Japanese Panasonic companies.But
The shortcomings that both battery technologies is that very expensive production equipment, complex process, manufacturing cost are very high, is also had in addition very high
Technology barriers.And the final goal of photovoltaic industry is to reduce cost of electricity-generating, the research and development of N-type high-efficiency battery must avoid the skill of complexity
Art route is to reduce process costs.The technology path of N-type double-side cell than conventional P-type battery merely add back side diffusion with it is blunt
Chemical industry skill, nearly all equipment can be developed using existing volume production equipment, and increased equipment and technology cost is very low, is most
It is possible to realize volume production.
In the prior art, the back side can cause front boron and back side phosphorus atoms in edge cross-diffusion without mask diffusion, this
PN junction edge current leakage can be caused, make battery loss increase, reduce the conversion efficiency of battery.Conventional settling mode is to work as to be passivated
Cheng Hou, battery edge is performed etching using laser or plasma, then silk-screen printing forms battery, although using laser or
The modes such as plasma etching can get rid of cross-diffusion region, and still, the increase of technique inevitably results in the life of battery
Produce cost to improve, while etching will also result in edge damage, reduce the parallel resistance of battery, causes the open-circuit voltage of battery and fills out
It is all relatively low to fill the factor.
The content of the invention
To solve the above problems, the invention provides a kind of double-side cell edge not damaged partition method, boron can be suppressed
With the cross-diffusion of phosphorus atoms edge region, not damaged edge isolation is realized, and avoids the introducing of etching technics and brings
Process costs increase and the problem of edge current leakage.
A kind of double-side cell edge not damaged partition method provided by the invention, including：
The dorsal edge of silicon chip after spreading and etching by front boron and side, make the diffusion barrier of annular
Layer, wherein, the diffusion impervious layer of the dorsal edge of the silicon chip has predetermined width；
In the circular region of the diffusion impervious layer of the silicon chip back side, carry out phosphorus diffusion and form n+ layers and PSG layers；
Remove the diffusion impervious layer and the PSG layers.
Preferably, in above-mentioned double-side cell edge not damaged partition method,
It is described make annular diffusion impervious layer be：
Make the SiN of annularxOyMask layer.
Preferably, in above-mentioned double-side cell edge not damaged partition method,
The predetermined width is 1 millimeter to 3 millimeters.
Preferably, in above-mentioned double-side cell edge not damaged partition method,
The dorsal edge and side in the silicon chip, while making the diffusion impervious layer of annular, in addition to：
Diffusion impervious layer is made in the front of the silicon chip.
Preferably, in above-mentioned double-side cell edge not damaged partition method,
It is described make annular diffusion impervious layer be：
Using PECVD methods or LPCVD methods, annular diffusion impervious layer is made.
Preferably, in above-mentioned double-side cell edge not damaged partition method,
It is described make annular diffusion impervious layer be：
The silicon chip is positioned over to shape is identical and size is less than on the substrate of the silicon chip, the silicon chip back side only has side
Edge point is exposed, and makes the diffusion impervious layer of annular.
Preferably, in above-mentioned double-side cell edge not damaged partition method,
It is described make annular diffusion impervious layer be：
Make the annular diffusion impervious layer that thickness range is 40 nanometers to 60 nanometers.
Preferably, in above-mentioned double-side cell edge not damaged partition method,
The removal diffusion impervious layer and the PSG layers are：
Etched 10 minutes to 20 minutes using hydrofluoric acid solution, remove the diffusion impervious layer and the PSG layers.
By foregoing description, above-mentioned double-side cell edge not damaged partition method provided by the invention, due to including：
The dorsal edge of silicon chip after spreading and etching by front boron and side, the diffusion impervious layer of annular is made, wherein, institute
The diffusion impervious layer for stating the dorsal edge of silicon chip has predetermined width；In the diffusion impervious layer ring of the silicon chip back side
Around region in, carry out phosphorus diffusion and form n+ layers and PSG layers；The diffusion impervious layer and the PSG layers are removed, therefore can be pressed down
The cross-diffusion of boron and phosphorus atoms edge region processed, realizes not damaged edge isolation, and avoid the introducing of etching technics and
The problem of process costs increase brought and edge current leakage.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is the schematic diagram for the first double-side cell edge not damaged partition method that the embodiment of the present application provides.
Embodiment
The present invention core concept be to provide a kind of double-side cell edge not damaged partition method, boron and phosphorus can be suppressed
The cross-diffusion of atom edge region, not damaged edge isolation is realized, and the work for avoiding the introducing of etching technics and bringing
The problem of increase of skill cost and edge current leakage.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The first double-side cell edge not damaged partition method that the embodiment of the present application provides is as shown in figure 1, Fig. 1 is this Shen
Please embodiment provide the first double-side cell edge not damaged partition method schematic diagram.This method comprises the following steps：
S1：The dorsal edge of silicon chip after spreading and etching by front boron and side, make the diffusion resistance of annular
Barrier, wherein, the diffusion impervious layer of the dorsal edge of the silicon chip has predetermined width；
It should be noted that first silicon chip can be cleaned before this step, and using the side of wet chemical etching technique
Method prepares surface pyramid matte, can use ripe monocrystalline silicon wafer alkaline flocking technique, form 45 degree of positive pyramid mattes, then
B is formed on silicon chip two sides and expands layer and bsg layer, is exactly that p is formed on pyramid for N-type silicon substrate+Type area, specifically, expanding
It is about 60-200 Ω/sq to clear into rear sheet resistance, and junction depth is 0.3 μm to 0.6 μm, and BSG thickness about 80nm is to 100nm, then etches just
BSG, edge and the back surface B of reverse side expand layer, and front retains B and expands layer.
The step is exactly that overleaf edge and side all set diffusion impervious layer, this diffusion resistance relative to prior art
Barrier can be formed in follow-up diffusing step it is effective stop and isolation, the predetermined width to ensure to be enough to be formed effectively every
From can set corresponding width as the case may be, not do any restrictions herein.The step and laser or plasma etching
Compare, process safety is high, the cost increase that laser or plasma etching equipment can be avoided to introduce and bring, and will not carve
Edge damage is introduced during erosion, is advantageous to the high conversion efficiency of battery.
S2：In the circular region of the diffusion impervious layer of the silicon chip back side, carry out phosphorus diffusion and form n+ layers and PSG
Layer；
Specifically, it can be realized using diffusion technique ripe on manufacture of solar cells line, sheet resistance after the completion of diffusion
About 80 to 100 Ω/sq, junction depth are about 0.3um, and just because of diffusion impervious layer being present, therefore the n+ layers diffused out will not be with
Front face, so as to suppress the cross-diffusion of boron atom and phosphorus atoms edge region.
S3：Remove the diffusion impervious layer and the PSG layers.
It should be noted that after backside deposition, avoid the need for the diffusion impervious layer, thus can by its with
PSG layers remove simultaneously.
By foregoing description, the above-mentioned double-side cell edge not damaged partition method of the embodiment of the present application offer, by
In including：The dorsal edge of silicon chip after spreading and etching by front boron and side, the diffusion impervious layer of annular is made,
Wherein, the diffusion impervious layer of the dorsal edge of the silicon chip has predetermined width；In the diffusion of the silicon chip back side
In the circular region in barrier layer, carry out phosphorus diffusion and form n+ layers and PSG layers；The diffusion impervious layer and the PSG layers are removed, because
This can suppress the cross-diffusion of boron and phosphorus atoms edge region, realize not damaged edge isolation, and avoid etching technics
Introducing and the process costs increase that brings and the problem of edge current leakage.
Second of double-side cell edge not damaged partition method that the embodiment of the present application provides, it is that the first is two-sided above-mentioned
On the basis of battery edge not damaged partition method, in addition to following technical characteristic：
It is described make annular diffusion impervious layer be：
Make the SiN of annularxOyMask layer.
It should be noted that SiOx the or SiNx films for making annular are can also be, all with the stability under high temperature
The advantages of good and cleanliness factor is high, so as to be polluted to process bands, it can also form effective isolation.
The third double-side cell edge not damaged partition method that the embodiment of the present application provides, is two-sided at above-mentioned second
On the basis of battery edge not damaged partition method, in addition to following technical characteristic：
The predetermined width is 1 millimeter to 3 millimeters.
It should be noted that the predetermined width can not realize effective edge isolation if too small, and it is too big if
Back side diffusion quality can be influenceed again, therefore can be preferably the scope.
The 4th kind of double-side cell edge not damaged partition method that the embodiment of the present application provides, it is that the third is two-sided above-mentioned
On the basis of battery edge not damaged partition method, in addition to following technical characteristic：
The dorsal edge and side in the silicon chip, while making the diffusion impervious layer of annular, in addition to：
Diffusion impervious layer is made in the front of the silicon chip.
It should be noted that diffusion impervious layer can be made in front side of silicon wafer, diffusion impervious layer can not also be made, herein
It is not intended to limit, can be determined according to concrete technology.
The 5th kind of double-side cell edge not damaged partition method that the embodiment of the present application provides, is two-sided at above-mentioned 4th kind
On the basis of battery edge not damaged partition method, in addition to following technical characteristic：
It is described make annular diffusion impervious layer be：
Using PECVD methods or LPCVD methods, annular diffusion impervious layer is made.
Wherein, LPCVD is low-pressure chemical vapour deposition technique, and PECVD is plasma reinforced chemical vapour deposition method, the two
It may serve to make the diffusion impervious layer of annular, and PECVD methods are more preferable, depositing temperature is low, adhesive force is good, and step covers
Lid ability is strong.It is of course also possible to use other method, is not intended to limit herein.
The 6th kind of double-side cell edge not damaged partition method that the embodiment of the present application provides, is two-sided at above-mentioned 5th kind
On the basis of battery edge not damaged partition method, in addition to following technical characteristic：
It is described make annular diffusion impervious layer be：
The silicon chip is positioned over to shape is identical and size is less than on the substrate of the silicon chip, the silicon chip back side only has side
Edge point is exposed, and makes the diffusion impervious layer of annular.
For example, in the case where silicon chip is circle, selected is exactly circular substrate, and the diameter of the circular substrate can compare
The diameter of silicon chip is small 1 millimeter to 3 millimeters, by circular substrate with silicon chip is concentric places, silicon chip is located above circular substrate, so
Region, side and the face exposure of 1 millimeter to 3 millimeters of silicon chip bottom edge will be come out, so as to just can on these surfaces
Produce diffusion impervious layer.
The 7th kind of double-side cell edge not damaged partition method that the embodiment of the present application provides, is two-sided at above-mentioned 6th kind
On the basis of battery edge not damaged partition method, in addition to following technical characteristic：
It is described make annular diffusion impervious layer be：
Make the annular diffusion impervious layer that thickness range is 40 nanometers to 60 nanometers.
It should be noted that this thickness range can effectively isolate, and it is easily removed, subsequent technique will not be made
Into adverse effect.
The 8th kind of double-side cell edge not damaged partition method that the embodiment of the present application provides, be it is above-mentioned the first to the
In seven kinds of double-side cell edge not damaged partition methods it is any on the basis of, in addition to following technical characteristic：
The removal diffusion impervious layer and the PSG layers are：
Etched 10 minutes to 20 minutes using hydrofluoric acid solution, remove the diffusion impervious layer and the PSG layers.
It should be noted that subsequent technique also includes：Silicon chip tow sides PECVD deposits SiNxAntireflective coating, the SiNxSubtract
Reflectance coating can reduce positive light reflection, can play effective surface passivation effect, SiN againxAntireflective coating can use folding
The plural layers of rate gradual change are penetrated, refractive index is between 2.04-2.11, positive SiNxThe thickness of film is about 60-80nm, the back side
SiNxThe thickness of film is about 80-100nm, then screen printing sizing agent, and electrode and back electrode before preparation, preceding electrode use silk screen
Printing Ag/Al slurry modes are completed, and back electrode is completed using silk-screen printing Ag slurry modes, finally using sintering process, are formed
Good Ohmic contact, in practice, also the modes such as evaporation, sputtering can be used to prepare battery electrode.
In summary, such scheme is by the ultra-fine annular membrane SiN in the back sidexOyDeposition applications are in N-type double-sided solar battery side
In the technique of edge isolation, laser or plasma etching industrial are avoided, to passivating film not damaged, and reduces N-type double-side cell
Manufacturing cost.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (3)
- A kind of 1. double-side cell edge not damaged partition method, it is characterised in that including：The dorsal edge of silicon chip after spreading and etching by front boron and side, the diffusion impervious layer of annular is made, its In, the diffusion impervious layer of the dorsal edge of the silicon chip has predetermined width, and the predetermined width is 1 millimeter to 3 millimeters；In the circular region of the diffusion impervious layer of the silicon chip back side, carry out phosphorus diffusion and form n+ layers and PSG layers；Remove the diffusion impervious layer and the PSG layers；The diffusion impervious layer for making annular is the silicon chip to be positioned over into shape is identical and size is less than the lining of the silicon chip On bottom, the silicon chip back side only has marginal portion to be exposed, and annular is made using PECVD methods or LPCVD methods SiNxOyMask layer；The dorsal edge and side in the silicon chip, while making the diffusion impervious layer of annular, it is additionally included in the silicon The front of piece makes diffusion impervious layer.
- 2. double-side cell edge not damaged partition method according to claim 1, it is characterised in thatIt is described make annular diffusion impervious layer be：Make the annular diffusion impervious layer that thickness range is 40 nanometers to 60 nanometers.
- 3. the double-side cell edge not damaged partition method according to claim any one of 1-2, it is characterised in thatThe removal diffusion impervious layer and the PSG layers are：Etched 10 minutes to 20 minutes using hydrofluoric acid solution, remove the diffusion impervious layer and the PSG layers.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882651A (en) * | 2010-07-16 | 2010-11-10 | 山东力诺太阳能电力股份有限公司 | Solar cell making process capable of blocking edge diffusion by using masks |
| CN203807551U (en) * | 2014-03-18 | 2014-09-03 | 泉州市博泰半导体科技有限公司 | Carrier plate for deposition of silicon wafer during manufacturing of solar cells |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882651A (en) * | 2010-07-16 | 2010-11-10 | 山东力诺太阳能电力股份有限公司 | Solar cell making process capable of blocking edge diffusion by using masks |
| CN203807551U (en) * | 2014-03-18 | 2014-09-03 | 泉州市博泰半导体科技有限公司 | Carrier plate for deposition of silicon wafer during manufacturing of solar cells |
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