CN112151641B - Method for preparing N-type battery by using insulating edge protective layer - Google Patents
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention discloses a method for preparing an N-type battery by using an insulating edge protection layer. The method comprises the following specific steps: (1) selecting an N-type monocrystalline silicon wafer, cleaning and texturing, diffusing boron and removing BSG; (2) uniformly coating a dielectric layer film on the edge of the silicon wafer by using a roller transmission device; (3) micro-sintering the dielectric layer and the silicon wafer by using high temperature before phosphorus diffusion is carried out by using diffusion or before polycrystalline silicon is deposited by LPCVD; (4) degumming, namely stripping the insulated dielectric layer and the phosphorus deposited on the dielectric layer by using HF; (5) after removing the PSG layer or the polysilicon layer of RCA by winding plating, AlOx and SiNx passivation is carried out on the front surface, SiNX passivation is carried out on the back surface, silver paste is printed on the front surface, and sintering is carried out. The method can effectively solve the problem of electric leakage at the edge of the N-type silicon wafer.
Description
Technical Field
The invention provides a method for solving edge leakage in the process of preparing an N-type battery by using an insulating material, and relates to the technical field of solar batteries.
Background
With the rapid development of the photovoltaic industry, the market urgently needs a solar cell industrialized preparation technology with simple process flow and high photoelectric conversion efficiency to reduce the photovoltaic power generation cost, so that the photovoltaic power generation cost reaches the goal of being at the same price as or lower than the commercial power price. Since the P-type PERC has only one diffusion process of phosphorus diffusion, the phosphorus removal process can be completed simultaneously with the phosphorus washing process when the plating and the leakage are generated. However, the cost of the N-type silicon wafer is gradually reduced in the following, the efficiency of the N-type silicon wafer such as a Topcon battery reaches 23.5%, and the market of the N-type silicon wafer is gradually developed by the market. However, in the process of manufacturing the N-type transistor, a PN junction and a back electric field need to be prepared, namely, boron diffusion and phosphorus diffusion or phosphorus injection are needed, and the problems of potential rounding plating and edge leakage are caused by the two kinds of diffusion, which are the problems of the N-type PERT and the Topcon. The phosphorus injection adopts ion injection to inject phosphorus into the silicon wafer, and the ion injection can effectively avoid the problems of plating and edge leakage, but the ion injection equipment is expensive, high in maintenance cost, high in production cost and the like, and is not beneficial to large-scale mass production; and the damage of the traditional insulating layer to the battery piece is large, the battery piece is lost when the battery piece is sliced and insulated, and a damage layer exists in edge splinters. The problems of phosphorus electroplating and phosphorus edge leakage are inevitably solved by adopting low-cost phosphorus diffusion, one mode adopts laser insulation, but the laser insulation has large damage to a silicon wafer and is easy to generate damages such as cracks, hidden cracks and the like, and the edge cracks have damaged layers and have large influence on the efficiency of the cell.
In the manufacturing process of the solar cell with the mask for blocking edge diffusion, CN201010228706.5 is a process for manufacturing a solar cell with the mask for blocking edge diffusion, wherein before the diffusion step, the periphery of the edge of a silicon wafer is covered with a mask for blocking diffusion, and the mask for blocking diffusion is a silicon dioxide film or a silicon nitride film. PECVD and furnace tube growth of SiNx or SiO 2 Insulation is carried out, whether the process is carried out after boron diffusion or phosphorus diffusion is not described, and how to solve the problem that the edge is not etched by back polishing if the process is carried out after boron diffusion; if the phosphorus is expanded, SiNx and SiO can not be solved 2 The problem of the electroplating of the PECVD tube deposited with SiNx and SiO2 can not be solved, and the insulating layer of SiNx or SiO2 is not removed, so that the phosphorus electroplating edge has the risk of electric leakage.
Therefore, how to solve the problems of edge plating and edge leakage caused by boron and phosphorus diffusion is a main problem which troubles an N-type silicon wafer (non-heterojunction battery).
Disclosure of Invention
The invention aims to solve the problem that the current N-type PERT and Topcon preparation process is difficult to solve the problem of electric leakage around the edge in the processes of boron diffusion, phosphorus diffusion or phosphorus ion implantation, and finally the overall efficiency of a battery piece is influenced. According to the method, the dielectric layer film prepared by using the glass powder is uniformly coated on the edge after phosphorus washing, then the dielectric layer film is pushed by using the high temperature of diffusion to protect the edge, the edge is separated, and HF is subsequently used for stripping.
The technical scheme adopted by the invention is as follows:
(1) selecting an N-type monocrystalline silicon wafer, cleaning and texturing, boron diffusion and BSG removal by a conventional process;
preferably, the method comprises the following steps: placing the silicon wafer subjected to surface texturing treatment in a furnace tube for boron diffusion, wherein the boron source can be liquid BBr 3 Also in the gaseous state 3 The diffusion temperature is 800-1200 ℃, and the diffusion time is 1-3 h;
removing BSG: placing the silicon chip after boron diffusion in BSG removing equipment for back polishing and BSG removing treatment, wherein the solution adopted by the back polishing is HCl/HNO 3 Or NH 3 H 2 O/H 2 O 2 Or one group of KOH/additives is combined for back polishing, and the BSG is removed by adopting 3 to 30 percent of HF for removing the BSG layer on the surface.
(2) Uniformly coating a dielectric film on the side edge of the silicon wafer (the edge of the silicon wafer refers to the side edge of the edge only and does not contain a bottom) by using a roller transmission device
The dielectric layer film is uniformly coated on the edge of the silicon wafer by using a roller transmission device, the used equipment can uniformly coat the dielectric layer with the thickness of 0.1-5 mm, and the material of the dielectric layer mainly comprises glass powder and an additive. The glass powder comprises 80-100% by mass of glass powder and 0-20% by mass of ceramic powder, wherein: the glass powder comprises, by mass, 3-25% of BaO, 25-60% of ZnO and 15-35% of B 2 O 3 、3～30％SiO 2 、0.2～6％Li 2 O and 0 to 1.5% Al 2 O 3 (ii) a The ceramic powder is at least one selected from the group consisting of alumina, zirconia, zircon, titania, cordierite, mullite, silica, willemite, tin oxide, and zinc oxide.
The additive consists of an organic solvent and an organic adhesive. The organic solvent is generally one of alcohol, ester, ketone organic substances, such as terpineol, tributyl citrate, acetate, etc., and the organic binder is generally one of high molecular polymer resins, such as ethyl cellulose, styrene, nitrocellulose, etc.
Preferably, the method comprises the following steps: the dielectric layer is prepared by mixing 20% of glass powder, 35% of ethyl cellulose and 45% of terpineol by mass percentage.
(3) Before carrying out phosphorus diffusion by using diffusion or depositing polycrystalline silicon by LPCVD (low pressure chemical vapor deposition), carrying out micro-sintering on the dielectric layer and the silicon wafer by using high temperature;
wherein, before phosphorus diffusion or polysilicon preparation, furnace tube is utilized to carry out micro-sintering, wherein, the process N 2 : 100 to 5000sccm, 500 to 900 ℃ for 1 to 30 min.
The process is superposed on a phosphorus diffusion or LPCVD polycrystal deposition process, wherein the temperature of the phosphorus diffusion is set to be 800-880 ℃, and the time is set to be 60-150 min. The temperature of depositing the polysilicon by LPCVD is set to be 500-800 ℃, and the time is set to be 60-120 min.
(4) Degumming, namely stripping the insulated dielectric layer and phosphorus deposited on the dielectric layer by utilizing HF;
and stripping the insulated dielectric layer and the phosphorus deposited on the dielectric layer by utilizing HF, wherein the concentration of the HF is set to be 1-15% by mass, and the time is set to be 30-600 s.
(5) After removing the PSG layer or the polysilicon layer of RCA by winding plating, carrying out AlOx and SiNx passivation on the front surface and carrying out SiNX passivation on the back surface;
(6) the front surface is printed with silver paste and then sintered, and the method can effectively solve the problem of electric leakage at the edge of the N-type silicon wafer.
Compared with the prior art, the invention has the following excellent effects: before the silicon chip is subjected to phosphorus diffusion or LPCVD (low pressure chemical vapor deposition) polysilicon, the edge insulation is prepared by using the glass powder as the material of the dielectric layer, so that PN junctions are not formed around the edge of the silicon chip in the diffusion process, and the PN junctions on the front side and the back side of the silicon chip are isolated, so that the edge etching of the silicon chip is not needed, the problem of short circuit of the upper electrode and the lower electrode of the silicon chip can be directly solved, the damage, efficiency reduction and other losses of the battery piece caused by the edge etching can be avoided, the photoelectric efficiency of the battery is improved, the edge insulation can be used for stripping the insulated dielectric layer and the phosphorus deposited on the dielectric layer by using HF, the operation is simple, and the method is suitable for industrial production.
Drawings
Fig. 1 is a flow chart comparing the conventional method for manufacturing an N-type cell and the method of the present invention for manufacturing an N-type cell.
Fig. 2 is a flow chart of the steps for manufacturing an N-type cell according to the present invention.
Fig. 3 is a structural view of the present invention for preparing an N-type battery.
Detailed Description
For better understanding of the present invention, the technical solution of the present invention will be described in detail with specific examples, but the present invention is not limited thereto.
The method comprises the steps of preparing an N-type monocrystalline silicon wafer by adopting a traditional method, cleaning and texturing the textured surface of the silicon wafer, performing front-side boron diffusion to form BSG, removing the BSG, performing phosphorus diffusion to form a PSG layer, removing the PSG, ALD, front plating, back plating and printing to obtain the N-type monocrystalline silicon wafer.
As shown in FIG. 1, before phosphorus diffusion by diffusion or polysilicon deposition by LPCVD, the invention uses high temperature to micro-sinter the dielectric layer and the silicon chip edge; and (4) carrying out phosphorus diffusion after micro-sintering, and cleaning and removing the edge protection layer after diffusion.
Example 1
The specific operating conditions of the high-efficiency N-type TOPCon battery of example 1 are preferably as follows:
(1) cleaning and texturing treatment: selecting an N-type crystal silicon substrate, and carrying out treatment such as metal ion removal, surface texturing and the like on an N-type silicon wafer;
(2) front side boron diffusion: placing the silicon wafer treated in the step (1) in a furnace tube for boron diffusion, wherein the adopted boron source can be liquid BBr 3 Also in the gaseous state 3 The diffusion temperature is 800-1200 ℃, and the diffusion time is 2 h;
(3) removing BSG: placing the silicon wafer obtained in the step (2) in a BSG removing device for back polishing and BSG removing treatment, wherein the solution adopted in the back polishing is HCl/HNO 3 Or NH 3 ﹒H 2 O/H 2 O 2 Or one group of KOH/additives is subjected to back polishing and removalBSG was resurfaced with 15% HF.
(4) Uniformly coating a dielectric layer film on the edge of a silicon wafer by using a roller transmission device:
the dielectric layer film is uniformly coated on the edge of the silicon wafer by using a roller transmission device, the used equipment can uniformly coat the dielectric layer with the thickness of 0.1mm, and the material of the dielectric layer is obtained by mixing 20% of glass powder, 35% of ethyl cellulose and 45% of terpineol according to mass percentage. Wherein the glass frit comprises 80% by mass of glass powder and 20% by mass of ceramic powder, wherein: the glass powder comprises, by mass, 25% of BaO, 25% of ZnO and 15% of B 2 O 3 、29％SiO 2 、5％Li 2 O and 1.0% Al 2 O 3 (ii) a The ceramic powder is prepared by mixing aluminum oxide and titanium oxide according to a mass ratio of 7: 3.
(5) Micro-sintering the dielectric layer and the silicon wafer by using high temperature before phosphorus diffusion is carried out by using diffusion or before polycrystalline silicon is deposited by LPCVD;
and (3) micro-sintering the dielectric layer and the silicon wafer by using high temperature before phosphorus diffusion is carried out by using diffusion or before polycrystalline silicon is deposited by LPCVD. Wherein, before phosphorus diffusion or polysilicon preparation, furnace tube is utilized to carry out micro-sintering, wherein, the process N 2 : 4000sccm, 800 ℃ for 25 min. The process is superposed on a phosphorus diffusion or LPCVD polycrystalline deposition process, wherein the temperature of phosphorus diffusion is set to be 800-880 ℃, and the time is set to be 100 min. The LPCVD deposition of polysilicon was set at a temperature of 600 deg.C for a time period of between 100 min.
(6) Degumming, namely stripping the insulated dielectric layer and the phosphorus deposited on the dielectric layer by using HF;
the insulating dielectric layer and the phosphorus deposited on the dielectric layer were stripped together with HF, wherein the concentration of HF was set to 10 mass% and the time was set to 100 s.
(7) After the RCA PSG layer or the polysilicon layer is removed, AlOx and SiNx passivation is carried out on the front surface, and SiNX passivation is carried out on the back surface;
(8) and printing silver paste on the front surface and sintering.
The method can effectively solve the problem of electric leakage at the edge of the N-type silicon wafer.
The structure of the resulting N-type TOPCon cell is shown in fig. 1.
Example 2 (wherein the same conditions as in example 1 are not defined.)
(1) Selecting an N-type monocrystalline silicon wafer, and cleaning, texturing, boron diffusion and phosphorus washing;
(2) uniformly coating a dielectric layer film on the edge of the silicon wafer by using a roller transmission device;
the dielectric layer film is uniformly coated on the edge of the silicon wafer by using a roller transmission device, the used equipment can uniformly coat the dielectric layer with the thickness of 3mm, and the material of the dielectric layer mainly comprises glass powder and an additive. The glass powder contains 90% by mass of glass powder and 10% by mass of ceramic powder, wherein: the glass powder comprises, by mass, 10% of BaO, 25% of ZnO and 30% of B 2 O 3 、30％SiO 2 、3.5％Li 2 O and 1.5% Al 2 O 3 (ii) a The ceramic powder is obtained by mixing alumina, zirconia, tin oxide and zinc oxide according to equal mass ratio.
(3) Micro-sintering the dielectric layer and the silicon wafer by using high temperature before phosphorus diffusion is carried out by using diffusion or before polycrystalline silicon is deposited by LPCVD;
and (3) micro-sintering the dielectric layer and the silicon wafer by using high temperature before phosphorus diffusion is carried out by using diffusion or before polycrystalline silicon is deposited by LPCVD. Wherein, before phosphorus diffusion or polysilicon preparation, furnace tube is utilized to carry out micro-sintering, wherein, the process N 2 : 1000sccm, 900 ℃ temperature and 5min time.
(4) Degumming, namely stripping the insulated dielectric layer and the phosphorus deposited on the dielectric layer by using HF;
the insulating dielectric layer and the phosphorus deposited on the dielectric layer were stripped together with HF, wherein the concentration of HF was set to 10 mass% and the time was set to 100 s.
(5) After removing the PSG layer or the polysilicon layer of RCA by winding plating, carrying out AlOx and SiNx passivation on the front surface and carrying out SiNX passivation on the back surface;
(6) and printing silver paste on the front surface and sintering.
Comparative example 1
Comparative example 1 is different from example 1 in that: the protection of the dielectric layer film in the steps (3) and (4) is omitted, and the other operations and structures are the same as those in example 1, thereby preparing an N-type battery.
The N-type cells prepared in example 1 and comparative example 1 were compared in electrical properties and the results are as follows:
in light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (2)
1. A method for preparing an N-type battery using an insulating edge protection layer, comprising the steps of:
(1) selecting an N-type monocrystalline silicon wafer, cleaning and texturing, diffusing boron and removing BSG;
(2) uniformly coating the dielectric layer film on the edge of the silicon wafer by using a roller transmission device, wherein the coating thickness is 0.1-5 mm; the dielectric layer is prepared by mixing 20% of glass powder, 35% of ethyl cellulose and 45% of terpineol in percentage by mass; the edge is a side edge of the silicon wafer and does not contain a bottom;
wherein the glass powder comprises 80-100% by mass of glass powder and 0-20% by mass of ceramic powder, wherein: the glass powder comprises, by mass, 3-25% of BaO, 25-60% of ZnO and 15-35% of B 2 O 3 、3~30％SiO 2 、0.2~6％Li 2 O and 0 to 1.5% Al 2 O 3 (ii) a The ceramic powder is at least one selected from the group consisting of alumina, zirconia, zircon, titania, cordierite, mullite, silica, willemite, tin oxide, and zinc oxide;
(3) phosphorus by diffusionBefore diffusion or LPCVD deposition of polysilicon, micro-sintering the dielectric layer and the silicon wafer by using high temperature; the conditions of micro-sintering are as follows: n is a radical of 2 : 100-5000 sccm, 500-900 ℃ temperature and 1-30 min time;
(4) degumming, namely stripping the insulated dielectric layer and the phosphorus deposited on the dielectric layer by using HF;
(5) AlO is carried out on the front surface after RCA PSG layer removal or polysilicon layer winding plating x 、SiN x Passivation of backside SiN x Passivating;
(6) and printing silver paste on the front surface and sintering.
2. The method for manufacturing an N-type battery using an insulating edge protection layer according to claim 1, wherein: and (4) degumming, namely stripping the insulated dielectric layer and the phosphorus deposited on the dielectric layer by using HF, wherein the concentration of the HF is set to be 1-15% by mass, and the time is set to be 30-600 s.
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| CN102487106A (en) * | 2010-12-02 | 2012-06-06 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Crystalline silica solar cell and manufacture method thereof |
| CN102263167B (en) * | 2011-08-15 | 2013-04-17 | 英利能源（中国）有限公司 | Method for passivating edge of monocrystalline silicon solar cell, monocrystalline silicon solar cell and manufacturing method thereof and photovoltaic module |
| US20130247981A1 (en) * | 2012-03-21 | 2013-09-26 | Suniva, Inc. | Solar cell fabrication using a pre-doping dielectric layer |
| US9478679B2 (en) * | 2013-12-11 | 2016-10-25 | Varian Semiconductor Equipment Associates, Inc. | Dielectric coating of the edge of a solar cell |
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