CN106462523A - 经由分布式时钟同步对输出数据的独立同步 - Google Patents

经由分布式时钟同步对输出数据的独立同步 Download PDF

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Publication number
CN106462523A
CN106462523A CN201580030386.3A CN201580030386A CN106462523A CN 106462523 A CN106462523 A CN 106462523A CN 201580030386 A CN201580030386 A CN 201580030386A CN 106462523 A CN106462523 A CN 106462523A
Authority
CN
China
Prior art keywords
data
clock
end points
data strobe
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580030386.3A
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English (en)
Chinese (zh)
Inventor
P·M·克洛维斯
Y-H·程
X·黄
S·奇卢库里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106462523A publication Critical patent/CN106462523A/zh
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CN201580030386.3A 2014-06-12 2015-05-15 经由分布式时钟同步对输出数据的独立同步 Pending CN106462523A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/302,727 US9478268B2 (en) 2014-06-12 2014-06-12 Distributed clock synchronization
US14/302,727 2014-06-12
PCT/US2015/031044 WO2015191235A1 (en) 2014-06-12 2015-05-15 Independent synchronization of output data via distributed clock synchronization

Publications (1)

Publication Number Publication Date
CN106462523A true CN106462523A (zh) 2017-02-22

Family

ID=53298600

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580030386.3A Pending CN106462523A (zh) 2014-06-12 2015-05-15 经由分布式时钟同步对输出数据的独立同步

Country Status (5)

Country Link
US (1) US9478268B2 (https=)
EP (1) EP3155529B1 (https=)
JP (1) JP2017517820A (https=)
CN (1) CN106462523A (https=)
WO (1) WO2015191235A1 (https=)

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KR101263663B1 (ko) * 2011-02-09 2013-05-22 에스케이하이닉스 주식회사 반도체 장치
US9123408B2 (en) * 2013-05-24 2015-09-01 Qualcomm Incorporated Low latency synchronization scheme for mesochronous DDR system
US9715914B1 (en) * 2015-09-26 2017-07-25 Syntropy Systems, Llc Polyphase buffer for rate-conversion
KR102518983B1 (ko) * 2016-05-18 2023-04-07 에스케이하이닉스 주식회사 직/병렬화 회로 및 이를 이용한 데이터 처리 시스템
US10254782B2 (en) * 2016-08-30 2019-04-09 Micron Technology, Inc. Apparatuses for reducing clock path power consumption in low power dynamic random access memory
KR102597343B1 (ko) * 2018-08-20 2023-11-06 에스케이하이닉스 주식회사 데이터 입력 회로를 포함하는 반도체 장치
KR102691395B1 (ko) * 2018-12-20 2024-08-05 에스케이하이닉스 주식회사 메모리 시스템, 메모리 시스템의 동작 방법 및 메모리 콘트롤러
US11082036B2 (en) * 2019-06-26 2021-08-03 SanDiskTechnologies LLC Memory interface system for duty-cycle error detection and correction
CN115333527B (zh) * 2022-07-21 2026-03-06 中国电子科技集团公司第二十九研究所 一种实现分布式频率源输出信号同步的电路及方法
US12537521B2 (en) * 2023-04-21 2026-01-27 Xilinx, Inc. DFxNoC—a multi-protocol, multi-cast, and multi-root network-on-chip with dynamic resource allocation
US12556188B2 (en) * 2023-09-08 2026-02-17 Qualcomm Incorporated Analog-to-digital converter (ADC) clock phase continuity across user equipment microsleep mode

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US20050138458A1 (en) * 2003-12-23 2005-06-23 Smith Victoria L. System and method for signal timing
US7127584B1 (en) * 2003-11-14 2006-10-24 Intel Corporation System and method for dynamic rank specific timing adjustments for double data rate (DDR) components
US7342521B1 (en) * 2006-06-28 2008-03-11 Chrontel, Inc. System and method for multi-channel delay cell based clock and data recovery
US7469328B1 (en) * 2003-02-06 2008-12-23 Cisco Technology, Inc. Synchronization technique for high speed memory subsystem
US20090154285A1 (en) * 2007-12-14 2009-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US20140052951A1 (en) * 2012-08-17 2014-02-20 Renesas Mobile Corporation Method and Apparatus for Transferring Data from a First Domain to a Second Domain

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US7127584B1 (en) * 2003-11-14 2006-10-24 Intel Corporation System and method for dynamic rank specific timing adjustments for double data rate (DDR) components
US20050138458A1 (en) * 2003-12-23 2005-06-23 Smith Victoria L. System and method for signal timing
US7342521B1 (en) * 2006-06-28 2008-03-11 Chrontel, Inc. System and method for multi-channel delay cell based clock and data recovery
US20090154285A1 (en) * 2007-12-14 2009-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US20140052951A1 (en) * 2012-08-17 2014-02-20 Renesas Mobile Corporation Method and Apparatus for Transferring Data from a First Domain to a Second Domain

Also Published As

Publication number Publication date
US20150364170A1 (en) 2015-12-17
US9478268B2 (en) 2016-10-25
WO2015191235A1 (en) 2015-12-17
JP2017517820A (ja) 2017-06-29
EP3155529B1 (en) 2018-08-22
EP3155529A1 (en) 2017-04-19

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