CN106341939A - Multi-layer line board structure and manufacturing method thereof - Google Patents

Multi-layer line board structure and manufacturing method thereof Download PDF

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Publication number
CN106341939A
CN106341939A CN201610794954.3A CN201610794954A CN106341939A CN 106341939 A CN106341939 A CN 106341939A CN 201610794954 A CN201610794954 A CN 201610794954A CN 106341939 A CN106341939 A CN 106341939A
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CN
China
Prior art keywords
layer
circuit board
multilayer circuit
copper foil
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610794954.3A
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Chinese (zh)
Inventor
柯勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kinwong Electronic Technology Longchuan Co Ltd
Original Assignee
Kinwong Electronic Technology Longchuan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kinwong Electronic Technology Longchuan Co Ltd filed Critical Kinwong Electronic Technology Longchuan Co Ltd
Priority to CN201610794954.3A priority Critical patent/CN106341939A/en
Publication of CN106341939A publication Critical patent/CN106341939A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/068—Features of the lamination press or of the lamination process, e.g. using special separator sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to the multi-layer line board field and particularly relates to a multi-layer line board structure and a manufacturing method thereof. The multi-layer line board structure mainly comprises multiple inner-layer substrates which are sequentially laminated, light core boards are arranged among adjacent inner-layer substrates, outer-layer copper foils are arranged both above the first inner-layer substrate and below the last inner-layer substrate, and prepregs are respectively arranged among the inner-layer substrates and the adjacent light core boards or the outer-layer copper foils. According to the multi-layer line board structure, through combination of the light core boards and the prepregs, lamination of the multiple prepregs is reduced, and problems of board sliding and interlayer offset during stitching of the multiple prepregs are avoided. According to the method, small-current long-time electroplating technological parameters are employed, uniformity of electroplating copper thickness is improved, a copper thickness range value is reduced, and manufacturing precision of an etching line is improved; dense lines and isolate lines are designed in a segment compensation mode, line etching excess and under etching rates are reduced, and a line making qualified rate is improved.

Description

A kind of multilayer circuit board structure and preparation method thereof
Technical field
The present invention relates to multilayer circuit board field, more particularly, to a kind of multilayer circuit board structure and preparation method thereof.
Background technology
Develop towards directions such as high accuracy, high density, high reliability with electronic product, conventional host, mobile phone, flat board electricity The printed wiring boards such as brain machinery through hole class product, circuit is designed as 75 μm of 75 μm/line-spacing of live width has become the normal of printed wiring board Use design specification.The fine-line technological ability improving multilayer circuit board at present relies primarily on equipment automatization scheme to realize, As automatic exposure machine, vcp plating line, fine-line etching machine etc. import high-end automated production equipment.But, multilayer circuit board Pressing laminated construction be related to internal substrate, prepreg, Copper Foil etc. multiple, multiple material be superimposed, and live width 75 μm of 75 μm/line-spacing waits and makes difficult point, based on industry technology limitation, interlayer dislocation easily, etch net, erosion in production Carve the problems such as excessive, circuit is bad.
Content of the invention
In view of the shortcomings of the prior art, it is an object of the invention to provide a kind of multilayer circuit board structure and its making Method.
For achieving the above object, the present invention can be achieved by the following technical programs:
A kind of multilayer circuit board structure, including some internal substrates being sequentially overlapped, sets between adjacent described internal substrate There is light central layer, be equipped with outer copper foil with the following of last block internal substrate above first piece of internal substrate, described internal layer It is equipped with prepreg between substrate and adjacent light central layer or outer copper foil.
Further, the thickness of described smooth central layer is 0.6-0.8.
Further, the thickness of described internal substrate is 0.1.
A kind of preparation method of multilayer circuit board, comprises the following steps:
(1) internal layer circuit make: substrate cuts, microetch is roughened, internal layer Ink Application, exposure imaging, internal layer acid etching, Striping, forms internal layer circuit；
(2) press: after internal layer circuit plate brown is processed, internal substrate, light central layer, prepreg, outer copper foil are pressed and folded Rotating fields order is superimposed together, and is pressed into multilayer circuit board in the presence of high pressure, high temperature；
(3) thinning copper: use level brown line subtracts Copper Foil technique and carries out thinning copper to outer copper foil；
(4) outer-layer circuit makes: carries out plated-through-hole operation to multilayer circuit board, including digital control hole drilling, removes boring glue residue And burr；Then electric plating of whole board, after the transfer of outer layer image, then carries out graphic plating, goes dry film, outer layer alkali etching to be formed Outer-layer circuit；
(5) it is surface-treated: carry out solder mask technique and text printout, stamp necessary mark, then be surface-treated；
(6) processing and forming.
Further, in step (1) inner operative egative film harmomegathus distance controlling in ± 25 μm, internal layer etching after pipe position away from From controlling in ± 50 μm, level to level alignment degree≤100 μm.
Further, brown line transfer rate 2.5-3.5/min in step (3), each Copper Foil microetch amount 1-2 μm, outward Layer copper thickness reduces to 7-9 μm.
Further, 600# adhesive-bonded fabric polish-brush is used twice to outer copper foil.
Further, be etched in step (4) compensate, 15 μm of the pre- large compensation of live width at dense wire it is ensured that circuit Small Distance is 60 μm, one line of outermost when isolated line build-out, outwards 30 μm of pre- large compensation, same ensure that circuit minimum spacing is 60μm；At bga pad clamp, segmented compensation is made in 10 μm of the not enough compensation of spacing, 20-30 μm of normal compensatory elsewhere.
Further, in step (4), electric plating of whole board parameter is 11asf × 30min, hole copper thickness >=5 μm, and plate face copper thickness is 11～16 μm, 5 μm of extreme difference；Graphic plating parameter is 9asf × 120min, hole copper thickness >=23 μm, table copper thickness >=30 μm.
Further, etch segments adjustment pressure in step (4), etching first paragraph presses 3kg/cm2, push 2kg/cm2； 0.8kg/cm is pressed on second segment2, push 0.4kg/cm2.
The structure of the present invention is combined with prepreg by light central layer, reduces the superposition of multiple prepregs, prevents many The problems such as when opening prepreg pressing, slide plate, interlayer misplace.The method of the present invention adopts small current, long-time electroplating technology ginseng Number, improves the thick uniformity of electro-coppering, decreases copper thickness extreme difference value, improves the making precision of circuit etching.To intensive line Road and the design of isolated circuit segmented compensation, decrease the probability that circuit etching is excessive, etching is not net, improve circuit making qualified Rate.
Brief description
Fig. 1 is the structural representation of the present invention；
Fig. 2 is method of the present invention flow chart；
In figure: 1- internal substrate, 2- light central layer, 3- outer copper foil, 4- prepreg.
Specific embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated:
As shown in figure 1, multilayer circuit board structure of the present invention, including some internal substrates 1 being sequentially overlapped, adjacent It is provided with light central layer 2 between internal substrate 1, be equipped with the following of last block internal substrate 1 above first piece of internal substrate 1 Outer copper foil 3, is equipped with prepreg 4 between internal substrate 1 and adjacent light central layer 2 or outer copper foil 3.The thickness of light central layer 2 Degree is preferably 0.6-0.8, and the thickness of internal substrate 1 is preferably 0.1.Replace the semi-solid preparation of original technology using light central layer 1 Piece 5, controls pressing heating rate, prevents the problems such as during the pressing of multiple prepregs, slide plate, interlayer misplace.
As shown in Fig. 2 a kind of preparation method of multilayer circuit board, comprise the following steps:
(1) internal layer circuit make: substrate cuts, microetch is roughened, internal layer Ink Application, exposure imaging, internal layer acid etching, Striping, forms internal layer circuit.Wherein, inner operative egative film harmomegathus distance controlling is in ± 25 μm, pipe position distance after internal layer etching Control in ± 50 μm, level to level alignment degree≤100 μm.
(2) press: after internal layer circuit plate brown is processed, internal substrate, light central layer, prepreg, outer copper foil are pressed and folded Rotating fields order is superimposed together, and is pressed into multilayer circuit board in the presence of high pressure, high temperature；
(3) thinning copper: use level brown line subtracts Copper Foil technique and carries out thinning copper to outer copper foil.Brown line transfer rate 2.5-3.5/min, each Copper Foil microetch amount 1-2 μm, outer copper foil thickness reduces to 7-9 μm from 17.5 ± 2 μm, to outer layer copper Paper tinsel use 600# adhesive-bonded fabric polish-brush twice it is ensured that copper thickness uniformity.
(4) outer-layer circuit makes: carries out plated-through-hole operation to multilayer circuit board, including digital control hole drilling, removes boring glue residue And burr；Then electric plating of whole board, after the transfer of outer layer image, then carries out graphic plating, goes dry film, outer layer alkali etching to be formed Outer-layer circuit.It is etched compensating, dense wire (75 μm of 75 μm/line-spacing of live width) 15 μm of the pre- large compensation of place's live width is it is ensured that circuit Minimum spacing is 60 μm, one line of outermost when isolated line build-out, outwards 30 μm of pre- large compensation, same ensure circuit minimum spacing For 60 μm；At bga pad clamp, segmented compensation is made in 10 μm of the not enough compensation of spacing, 20-30 μm of normal compensatory elsewhere.Full plate electricity Plating (traditional plating line) parameter is 11asf × 30min, hole copper thickness >=5 μm, and plate face copper is thick to be 11～16 μm, 5 μm of extreme difference；Figure Shape plating (traditional plating line) parameter is 9asf × 120min (program of normal 60min twice, after wherein having plated a 60min Centre needs to exchange chuck it is ensured that copper-plated uniformity), hole copper thickness >=23 μm, table copper thickness >=30 μm.Etch segments adjustment pressure Power, etching first paragraph presses 3kg/cm2, push 2kg/cm2；0.8kg/cm is pressed on second segment2, push 0.4kg/cm2.
(5) it is surface-treated: after outer-layer circuit is formed, carry out solder mask technique and text printout, stamp necessary mark, It is surface-treated (anti-oxidation or chemical nickel plating is golden) again.
(6) processing and forming: after surface treatment, multilayer circuit board now is to be made with jigsaw form, needs to adopt With CNC milling machine, multilayer circuit board is decomposed forming unit, the wiring board being molded the most at last carries out electric performance test and quality inspection Complete multilayer circuit board after testing to make.
For a person skilled in the art, other can be made various corresponding according to above technical scheme and design Change and deformation, and all these change and deformation all should belong within the protection domain of the claims in the present invention.

Claims (10)

1. a kind of multilayer circuit board structure it is characterised in that: include some internal substrates being sequentially overlapped, adjacent described internal layer base It is provided with light central layer between plate, above first piece of internal substrate, be equipped with outer copper foil with the following of last block internal substrate, It is equipped with prepreg between described internal substrate and adjacent light central layer or outer copper foil.
2. multilayer circuit board structure according to claim 1 it is characterised in that: the thickness of described smooth central layer be 0.6-0.8 ㎜.
3. multilayer circuit board structure according to claim 1 it is characterised in that: the thickness of described internal substrate be 0.1.
4. a kind of preparation method of the arbitrary described multilayer circuit board of claim 1-3 is it is characterised in that comprise the following steps:
(1) internal layer circuit makes: substrate cuts, microetch is roughened, internal layer Ink Application, exposure imaging, internal layer acid etching, go Film, forms internal layer circuit；
(2) press: after internal layer circuit plate brown is processed, internal substrate, light central layer, prepreg, outer copper foil are pressed lamination knot Structure order is superimposed together, and is pressed into multilayer circuit board in the presence of high pressure, high temperature；
(3) thinning copper: use level brown line subtracts Copper Foil technique and carries out thinning copper to outer copper foil；
(4) outer-layer circuit makes: carries out plated-through-hole operation to multilayer circuit board, including digital control hole drilling, removes boring glue residue and hair Thorn；Then electric plating of whole board, after the transfer of outer layer image, then carries out graphic plating, goes dry film, outer layer alkali etching to form outer layer Circuit；
(5) it is surface-treated: carry out solder mask technique and text printout, stamp necessary mark, then be surface-treated；
(6) processing and forming.
5. multilayer circuit board according to claim 4 preparation method it is characterised in that: inner operative bottom in step (1) Piece harmomegathus distance controlling in ± 25 μm, internal layer etching after pipe position distance controlling in ± 50 μm, level to level alignment degree≤100 μm.
6. multilayer circuit board according to claim 4 preparation method it is characterised in that: in step (3) brown line transmission Speed 2.5-3.5/min, each Copper Foil microetch amount 1-2 μm, outer copper foil thickness reduces to 7-9 μm.
7. multilayer circuit board according to claim 6 preparation method it is characterised in that: to outer copper foil use 600# not Weave cotton cloth polish-brush twice.
8. multilayer circuit board according to claim 4 preparation method it is characterised in that: be etched in step (4) mend Repay, 15 μm of the pre- large compensation of live width at dense wire it is ensured that circuit minimum spacing is 60 μm, mend when isolated circuit by one line of outermost Repay, outwards 30 μm of pre- large compensation, same ensure that circuit minimum spacing is 60 μm；At bga pad clamp, spacing is not enough compensates 10 μm Make segmented compensation, elsewhere 20-30 μm of normal compensatory.
9. multilayer circuit board according to claim 4 preparation method it is characterised in that: in step (4) electric plating of whole board ginseng Number is 11asf × 30min, hole copper thickness >=5 μm, and plate face copper is thick to be 11～16 μm, 5 μm of extreme difference；Graphic plating parameter is 9asf × 120min, hole copper thickness >=23 μm, table copper thickness >=30 μm.
10. multilayer circuit board according to claim 4 preparation method it is characterised in that: in step (4) etch segments adjust Seamless power, etching first paragraph presses 3kg/cm2, push 2kg/cm2；0.8kg/cm is pressed on second segment2, push 0.4kg/cm2.
CN201610794954.3A 2016-08-31 2016-08-31 Multi-layer line board structure and manufacturing method thereof Pending CN106341939A (en)

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106961787A (en) * 2017-04-17 2017-07-18 四川深北电路科技有限公司 A kind of preparation technology of the thick copper foil circuit plate of high heat conduction
CN107493650A (en) * 2017-08-22 2017-12-19 景旺电子科技(龙川)有限公司 A kind of automotive electronics high-frequency multi-layer circuit board laminated construction and process for pressing
CN109548279A (en) * 2018-12-29 2019-03-29 广州兴森快捷电路科技有限公司 Prepreg lamination design method
CN109640529A (en) * 2018-12-29 2019-04-16 深圳万基隆电子科技有限公司 A kind of manufacture craft of two-sided super thick copper sheet
CN110996566A (en) * 2019-12-27 2020-04-10 大连崇达电路有限公司 Manufacturing method of high-precision multilayer circuit board
CN111148376A (en) * 2019-12-24 2020-05-12 江门崇达电路技术有限公司 Laminating method of thick dielectric layer PCB
CN111263518A (en) * 2020-01-22 2020-06-09 惠州中京电子科技有限公司 Manufacturing method of packaging substrate of novel LED electronic display screen
CN111328215A (en) * 2020-02-21 2020-06-23 竞华电子(深圳)有限公司 Printed circuit board manufacturing method and printed circuit board
CN112261788A (en) * 2020-10-22 2021-01-22 江门崇达电路技术有限公司 Manufacturing method of thick copper high-density interconnection printed board
CN112601387A (en) * 2021-03-08 2021-04-02 四川英创力电子科技股份有限公司 Manufacturing method of large-size printed multilayer board
CN116456602A (en) * 2023-05-09 2023-07-18 江门全合精密电子有限公司 Manufacturing method of wafer packaging test PCB motherboard

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CN102740598A (en) * 2011-04-13 2012-10-17 昆山华晨电子有限公司 Three-layer anti-fake label PCB plate and preparation process thereof
CN103014799A (en) * 2012-12-05 2013-04-03 深圳市兴达线路板有限公司 Electroplating process of circuit board of burning-resistant board
CN103108485A (en) * 2011-11-11 2013-05-15 北大方正集团有限公司 Multi-layer printed circuit board and manufacturing method thereof
CN105072808A (en) * 2015-07-09 2015-11-18 华进半导体封装先导技术研发中心有限公司 Etching compensation method for high-precision packaging substrate

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CN101054701B (en) * 2007-02-08 2010-12-08 上海美维科技有限公司 Method of increasing electroplating evenness
CN102014590A (en) * 2010-12-18 2011-04-13 广东生益科技股份有限公司 Production method of multi-layer printed circuit board and multi-layer printed circuit board
CN102740598A (en) * 2011-04-13 2012-10-17 昆山华晨电子有限公司 Three-layer anti-fake label PCB plate and preparation process thereof
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CN103108485A (en) * 2011-11-11 2013-05-15 北大方正集团有限公司 Multi-layer printed circuit board and manufacturing method thereof
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106961787A (en) * 2017-04-17 2017-07-18 四川深北电路科技有限公司 A kind of preparation technology of the thick copper foil circuit plate of high heat conduction
CN107493650A (en) * 2017-08-22 2017-12-19 景旺电子科技(龙川)有限公司 A kind of automotive electronics high-frequency multi-layer circuit board laminated construction and process for pressing
CN109548279A (en) * 2018-12-29 2019-03-29 广州兴森快捷电路科技有限公司 Prepreg lamination design method
CN109640529A (en) * 2018-12-29 2019-04-16 深圳万基隆电子科技有限公司 A kind of manufacture craft of two-sided super thick copper sheet
CN111148376A (en) * 2019-12-24 2020-05-12 江门崇达电路技术有限公司 Laminating method of thick dielectric layer PCB
CN110996566A (en) * 2019-12-27 2020-04-10 大连崇达电路有限公司 Manufacturing method of high-precision multilayer circuit board
CN111263518A (en) * 2020-01-22 2020-06-09 惠州中京电子科技有限公司 Manufacturing method of packaging substrate of novel LED electronic display screen
CN111328215A (en) * 2020-02-21 2020-06-23 竞华电子(深圳)有限公司 Printed circuit board manufacturing method and printed circuit board
CN112261788A (en) * 2020-10-22 2021-01-22 江门崇达电路技术有限公司 Manufacturing method of thick copper high-density interconnection printed board
CN112601387A (en) * 2021-03-08 2021-04-02 四川英创力电子科技股份有限公司 Manufacturing method of large-size printed multilayer board
CN112601387B (en) * 2021-03-08 2021-05-25 四川英创力电子科技股份有限公司 Manufacturing method of large-size printed multilayer board
CN116456602A (en) * 2023-05-09 2023-07-18 江门全合精密电子有限公司 Manufacturing method of wafer packaging test PCB motherboard
CN116456602B (en) * 2023-05-09 2024-05-14 江门全合精密电子有限公司 Manufacturing method of wafer packaging test PCB motherboard

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