CN106330174B - The electronic device of CMOS inverter and the application CMOS inverter - Google Patents
The electronic device of CMOS inverter and the application CMOS inverter Download PDFInfo
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- CN106330174B CN106330174B CN201610671927.7A CN201610671927A CN106330174B CN 106330174 B CN106330174 B CN 106330174B CN 201610671927 A CN201610671927 A CN 201610671927A CN 106330174 B CN106330174 B CN 106330174B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The invention discloses a kind of CMOS inverters, including first selector, second selector, and the first transistor of CMOS inverter input terminal is connected by grid respectively, second transistor, third transistor and the 4th transistor, the first transistor, second transistor, the drain electrode of third transistor and the 4th transistor is all connected with the output end of CMOS inverter, first, the source electrode of third transistor is connected respectively the first output end and second output terminal of first selector, second, the source electrode of 4th transistor is connected respectively the first output end and second output terminal of second selector；First selector and second selector access the first control signal and second control signal of opposite in phase, and are all connected with the input terminal.The deterioration of transistor can be reduced using the CMOS inverter, improve device service life.
Description
Technical field
The present invention relates to field of circuit technology, and in particular to a kind of CMOS inverter and the electronics using the CMOS inverter
Device.
Background technique
CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor)
Phase inverter is the device being commonly used in circuit, and CMOS inverter receives an input signal and exports and input signal logical inverse
The output signal turned.
Referring to Fig. 1, Fig. 1 is the circuit structure diagram of CMOS inverter in the prior art.As shown in Figure 1, the phase inverter by
One P type metal oxide semiconductor (PMOS) transistor T1 and N-type metal-oxide semiconductor (MOS) (NMOS) transistor T2 is formed,
However since the supply voltage Vdd of the high level of access and low level supply voltage Vss are invariable, it is assumed that Vdd,
Vss is respectively 30V and -6V.As the input signal in of input high level, NMOS transistor T2 conducting, the phase inverter exports Vss
Low level -6V, the voltage Vds between the drain electrode of PMOS transistor T1, source electrode always remains as the exhausted of Vdd, Vss pressure difference at this time
To value (36V), until input end signal in becomes low level, this period PMOS transistor T1 be constantly subjected to the stress of 36V
(stress) voltage.Similarly, when input signal in is low level, until before becoming high level, NMOS transistor
T2 is similarly constantly subjected to high stress voltage.When the voltage difference (i.e. voltage Vds) of Vdd and Vss is larger, in CMOS inverter
Core transistor under higher stress voltage state, is easy to cause transistor ageing and damage, and then reduce in long-time
The service life of phase inverter.
Summary of the invention
The embodiment of the present invention provides a kind of CMOS inverter and application, it is possible to reduce what the pressure difference of output end changed greatly
The stress time of core transistor, reduction transistor deterioration, improve the service life of CMOS inverter in CMOS inverter.
In a first aspect, the embodiment of the invention provides a kind of complementary metal oxide semiconductor (CMOS) phase inverter, it is described
CMOS inverter includes that first selector and second selector, the first transistor, second transistor, third transistor and the 4th are brilliant
Body pipe, in which:
The first transistor, second transistor, third transistor and the 4th transistor grid be connected to it is described
The drain electrode of the input terminal of CMOS inverter, the first transistor, second transistor, third transistor and the 4th transistor connects
It is connected to the output end of the CMOS inverter, the source electrode of the first transistor is connected to the first output of the first selector
End, the source electrode of the third transistor are connected to the second output terminal of the first selector, the source electrode of the second transistor
It is connected to the first output end of the second selector, the source electrode of the 4th transistor is connected to the of the second selector
Two output ends；
The first selector and the second selector access first control signal and second control signal, and described
The opposite in phase of one control signal and the second control signal, the first selector and the second selector electrically connect
Connect the input terminal of the CMOS inverter；
When the second control signal is the input terminal input high level signal of high level or the CMOS inverter,
First output end of the first selector exports second control signal；When the first control signal is high level or described
When the input terminal input high level signal of CMOS inverter, second output terminal output the first control letter of the first selector
Number；It is described when the first control signal is the input terminal input low level signal of low level or the CMOS inverter
The second output terminal of second selector exports first control signal；When the second control signal is low level or the CMOS
When the input terminal input low level signal of phase inverter, the first output end of the second selector exports second control signal.
Wherein, the first selector includes first choice circuit and the second selection circuit, in which:
The first choice circuit and second selection circuit access the first control signal and second control
Signal processed, the first choice circuit and the second selection circuit are electrically connected the input terminal of the CMOS inverter, and described
One selection circuit is electrically connected the source electrode of the first transistor, and second selection circuit is electrically connected the third transistor
Source electrode.
Wherein, the second selector includes third selection circuit and the 4th selection circuit, in which:
The third selection circuit and the 4th selection circuit access the first control signal and the second control letter
Number, the third selection circuit and the 4th selection circuit are electrically connected the input terminal of the CMOS inverter, the third choosing
The source electrode of second transistor described in circuit connection is selected, the 4th selection circuit connects the source electrode of the 4th transistor.
Wherein, the first choice circuit includes the 5th transistor and the 6th transistor, in which:
The grid of 5th transistor accesses the first control signal, described in the grid connection of the 6th transistor
The input terminal of CMOS inverter, the drain electrode of the source electrode and the 6th transistor of the 5th transistor access second control
Signal processed, the drain electrode of the 5th transistor and the source electrode of the 6th transistor are electrically connected to the first selector
First output end.
Wherein, second selection circuit includes the 7th transistor and the 8th transistor, in which:
The grid of 7th transistor accesses the second control signal, described in the grid connection of the 8th transistor
The input terminal of CMOS inverter, the drain electrode of the source electrode and the 8th transistor of the 7th transistor access first control
Signal processed, the drain electrode of the 7th transistor and the source electrode of the 8th transistor are electrically connected to the first selector
Second output terminal.
Wherein, the third selection circuit includes the 9th transistor and the tenth transistor, in which:
The grid of 9th transistor accesses the first control signal, described in the grid connection of the tenth transistor
The input terminal of CMOS inverter, the drain electrode of the source electrode and the tenth transistor of the 9th transistor access second control
Signal processed, the drain electrode of the 9th transistor and the source electrode of the tenth transistor are electrically connected to the second selector
First output end.
Wherein, the 4th selection circuit includes the 11st transistor and the tenth two-transistor, in which:
The grid of 11st transistor accesses the second control signal, the grid connection of the tenth two-transistor
The drain electrode of the input terminal of the CMOS inverter, the source electrode and the tenth two-transistor of the 11st transistor accesses institute
First control signal is stated, the drain electrode of the 11st transistor and the source electrode of the tenth two-transistor are electrically connected to described
The second output terminal of second selector.
Wherein, the first transistor and the third transistor are PMOS tube, the second transistor and described
Four transistors are NMOS tube.
Wherein, the first control signal and the high level accounting duration of the second control signal in one cycle with
Low level accounting duration is equal.
Second aspect, the embodiment of the invention also provides a kind of electronic device, the electronic device includes above-mentioned CMOS
Phase inverter.
In the CMOS inverter provided in the embodiment of the present invention, when the second control signal is high level, described
When first control signal is low level, the first output end of the first selector exports second control signal, second choosing
The second output terminal for selecting device exports the first control signal；If the input terminal input high level signal of the CMOS inverter,
Then the second output terminal of the first selector exports the first control signal；The second transistor, the 4th transistor are led
Logical, the pressure difference of the source and drain interpolar of the third transistor is zero, and the pressure difference of the source and drain interpolar of the first transistor is larger；If institute
The input terminal input low level signal for stating CMOS inverter then selects the first output end of the second selector to export the second control
Signal processed, the first transistor, third transistor conducting, the pressure difference of the source and drain interpolar of the second transistor is zero, described
The pressure difference of the source and drain interpolar of 4th transistor is larger.When the first control signal is high level, second control signal is
When low level, the second output terminal output first control signal of the first selector, the first of the second selector
Output end exports second control signal, if the input terminal input high level signal of the CMOS inverter, selects first choosing
The first output end output second control signal of device is selected, the pressure difference of the source and drain interpolar of the first transistor is zero, the third
The pressure difference of the source and drain interpolar of transistor is big；If the input terminal input low level signal of the CMOS inverter, described second is selected
The second output terminal of selector exports the first control signal；The pressure difference of the source and drain interpolar of 4th transistor is zero, institute
The pressure difference for stating the source and drain interpolar of the first transistor is big.It can be seen that in the course of work of the CMOS inverter, according to
One, the level height of the level height and inverter input signal of second control signal, within the same time, only
The transistor stated in the first transistor, second transistor, third transistor and the 4th transistor is in stress state, relatively
Reduce the stress time of each transistor, implements the CMOS inverter in the embodiment of the present invention, can solve in existing reverse phase
Core transistor easily causes asking for transistor life decline because being chronically at high-voltage state in the device output biggish circuit of pressure difference
Topic.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the electrical block diagram of CMOS inverter in the prior art；
Fig. 2 is a kind of circuit diagram of CMOS inverter disclosed by the embodiments of the present invention；
Fig. 3 is the circuit diagram of another CMOS inverter disclosed by the embodiments of the present invention；
Fig. 4 is the circuit diagram of another CMOS inverter disclosed by the embodiments of the present invention；
Fig. 5 is the timing diagram of two control signals in the CMOS inverter of the embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in embodiment of the present invention, the technical solution in embodiment of the present invention is carried out clear
Chu is fully described by.Obviously, described embodiment is a part of embodiment of the invention, rather than whole embodiment party
Formula.Based on the embodiment in the present invention, those of ordinary skill in the art are obtained without making creative work
The every other embodiment obtained, all should belong to the scope of protection of the invention.
In addition, the explanation of following embodiment is referred to the additional illustration, the spy that can be used to implement to illustrate the present invention
Determine embodiment.Direction terms mentioned in the present invention, for example, "upper", "lower", "front", "rear", "left", "right", "inner",
"outside", " side " etc. are only the directions with reference to annexed drawings, and therefore, the direction term used is to more preferably, more clearly say
The bright and understanding present invention, rather than indicate or imply signified device or element and must have a particular orientation, with specific square
Position construction and operation, therefore be not considered as limiting the invention.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be fixedly connected, is also possible to detachably connected, or integrally connects
It connects；It can be mechanical connection；It can be directly connected, can also can be in two elements indirectly connected through an intermediary
The connection in portion.For the ordinary skill in the art, the tool of above-mentioned term in the present invention can be understood with concrete condition
Body meaning.
In addition, in the description of the present invention, unless otherwise indicated, the meaning of " plurality " is two or more.If this
Occur the term of " process " in specification, refers not only to independent process, when can not clearly be distinguished with other process, as long as
Effect desired by the process is able to achieve then to be also included in this term.In addition, the numerical value indicated in this specification with " ~ "
The range that the numerical value that range is recorded before and after referring to " ~ " is included as minimum value and maximum value.In the accompanying drawings, it ties
The similar or identical unit of structure is indicated by the same numeral.
The embodiment of the invention provides a kind of CMOS inverter, answering for core transistor in CMOS inverter can be reduced
The power time reduces transistor deterioration, improves the service life of CMOS inverter.It is described in detail separately below.
Fig. 2 is please referred to, Fig. 2 is a kind of complementary metal oxide semiconductor (CMOS) phase inverter disclosed by the embodiments of the present invention
Circuit diagram.
In the present embodiment, the CMOS inverter includes first selector 100 and second selector 200, first crystal
Pipe T1, second transistor T2, third transistor T3 and the 4th transistor T4, in which: the first transistor T1, second transistor
The grid of T2, third transistor T3 and the 4th transistor T4 are connected to the input terminal In of the CMOS inverter；Described first
The drain electrode of transistor T1, second transistor T2, third transistor T3 and the 4th transistor T4 are connected to the CMOS inverter
Output end Out, specifically, the drain electrode of the first transistor T1 is connected to after connecting with the drain electrode of the second transistor T2
The drain electrode of the output end Out, the third transistor T3 are connected to described after connecting with the drain electrode of the 4th transistor T4
Output end Out.The source electrode of the first transistor T1 connects the first output terminals A 1 of the first selector 100, the third
The source electrode that the source electrode of transistor T3 is connected to the second output terminal A2, the second transistor T2 of the first selector 100 connects
It is connected to the first output end B1 of the second selector 200, the source electrode of the 4th transistor T4 is connected to second selection
The second output terminal B2 of device 200.Wherein, in the present embodiment, the first transistor T1 and third transistor T3 is P
Type metal oxide semiconductor transistor (PMOS tube), the second transistor T2 and the 4th transistor T4 are N-type gold
Belong to oxide semi conductor transistor (NMOS tube).
The first selector 100 and second selector 200 can access first control signal LC1 and second control signal
LC2, wherein the opposite in phase of the first control signal LC1 and second control signal LC2.The first selector 100 and institute
State the input terminal In that second selector 200 is electrically connected the CMOS inverter.Specifically, the first selector 100
Control terminal C1 is connected to the defeated of the CMOS inverter by the grid of the first transistor T1 and the third transistor T3
Enter to hold In；The control terminal C2 of the second selector 200 passes through the grid of the second transistor T2 and the 4th transistor T4
Pole is connected to the input terminal In of the CMOS inverter.
When the second control signal LC2 is high level (when the i.e. described first control signal LC1 is low level), Huo Zhesuo
When stating the input terminal In input high level signal of CMOS inverter (when meeting any of the above-described condition), then the first selector
100 the first output terminals A 1 exports the second control signal LC2.Specifically, working as the input terminal In of the CMOS inverter
When input high level signal, no matter the second control signal LC2 is high level or low level, the first selector at this time
100 the first output terminals A 1 exports second control signal LC2.When the second control signal LC2 be high level when, at this time without
By the input terminal In input low level signal or input terminal In input high level signal of the CMOS inverter, described
First output terminals A 1 of one selector 100 exports the second control signal LC2 of high level.
When the first control signal LC1 is high level (when the i.e. described second control signal LC2 is low level), Huo Zhesuo
When stating the input terminal In input high level signal of CMOS inverter (when meeting any of the above-described condition), then first choosing is selected
The second output terminal A2 for selecting device 100 exports the first control signal LC1.Specifically, defeated when the CMOS inverter
When entering to hold In input high level signal, no matter the first control signal LC1 is high level or low level, first choosing at this time
The second output terminal A2 for selecting device 100 exports first control signal LC1.When the second control signal LC1 is high level, this
When no matter the input terminal In input low level signal or input terminal In input high level signal of the CMOS inverter, institute
The first output terminals A 1 for stating first selector 100 exports the second control signal LC2 of high level.
When the input terminal In input low level that the first control signal LC1 is low level or the CMOS inverter
When signal (when meeting any of the above-described condition), then the second output terminal B2 of the second selector 200 exports described first
Control signal LC1.Specifically, no matter described at this time when the input terminal In input low level signal of the CMOS inverter
First control signal LC1 is low level or is high level, and the second output terminal B2 of the second selector 200 exports the first control
Signal LC1 processed.When the first control signal LC1 be low level when, at this time no matter the CMOS inverter input terminal In it is defeated
Enter low level signal or input terminal In input high level signal, the second output terminal B2 of the second selector 200 are defeated
Low level first control signal LC1 out.
When the input terminal In input low level that the second control signal LC2 is low level or the CMOS inverter
When signal (when meeting any of the above-described condition), then the first output end B1 of the second selector 200 exports described second
Control signal LC2.Specifically, no matter described at this time when the input terminal In input low level signal of the CMOS inverter
Second control signal LC2 is low level or is high level, and the first output end B1 of the second selector 200 exports the second control
Signal LC2 processed.When the second control signal LC2 be low level when, at this time no matter the CMOS inverter input terminal In it is defeated
Enter low level signal or input terminal In input high level signal, the second output terminal B2 of the second selector 200 are defeated
Low level second control signal LC2 out.
In the CMOS inverter structure of Fig. 2 description, when the second control signal LC2 is high level or described first
When control signal LC1 is low level, the first output terminals A 1 of the first selector 100 exports second control signal LC2, described
The second output terminal B2 of second selector 200 exports first control signal LC1；If the input terminal In of the CMOS inverter is inputted
High level signal, then the second output terminal A2 of the first selector 100 exports first control signal LC1, due to described at this time
Input terminal In be high level signal, then the second transistor T2 and the 4th transistor T4 conducting, the CMOS inverter it is defeated
Outlet Out exports low level first control signal LC1, and the pressure difference of the source and drain interpolar of the third transistor T3 is zero at this time,
And the pressure difference of the source and drain interpolar of the first transistor T1 is larger, is equal to the control letter of the first control signal LC1 and second
The current potential absolute value of the difference of number LC2, i.e., the only the first transistor T1 are in the stress state of high voltage.If the CMOS reverse phase
The input terminal In input low level signal of device then selects the first output end B1 of the second selector 200 to export the second control
Signal LC2, since the input terminal In is low level signal at this time, then the first transistor T1 and third transistor T3 are led
Logical, the output end Out of the CMOS inverter exports the second control signal LC2 of high level, at this time the second transistor T2
The pressure difference of source and drain interpolar be zero, and the pressure difference of the source and drain interpolar of the 4th transistor T4 is larger, is equal to first control
The current potential absolute value of the difference of signal LC1 and second control signal LC2 processed, i.e., only the 4th transistor T4 is in answering for high voltage
Power state.
When the first control signal LC1 is high level or second control signal LC2 is low level, first choosing
Select the second output terminal A2 output first control signal LC1 of device 100, the first output end B1 output of the second selector 200
Second control signal LC2.If the input terminal In input high level signal of the CMOS inverter, the first selector 100
The first output terminals A 1 export second control signal LC2, since the input terminal In at this time is high level signal, described second is brilliant
The output end Out of body pipe T2 and the 4th transistor T4 conducting, the CMOS inverter exports low level second control signal
LC2, the pressure difference of the source and drain interpolar of the first transistor T1 is zero at this time, and the pressure of the source and drain interpolar of the third transistor T3
Difference is larger, is equal to the current potential absolute value of the difference of the first control signal LC1 and second control signal LC2, i.e., and only described the
Three transistor T3 are in the stress state of high voltage.If the input terminal In input low level signal of the CMOS inverter, institute
The second output terminal B2 output first control signal LC1 for stating second selector 200, since the input terminal In is low level at this time
Signal, the first transistor T1 and third transistor T3 conducting, the output end Out output high level of the CMOS inverter
First control signal LC1, the pressure difference of the source and drain interpolar of the 4th transistor T4 is zero at this time, and the second transistor T2
Pressure difference between source-drain electrode is larger, absolute equal to the potential difference of the first control signal LC1 and second control signal LC2
Value, i.e., the only second transistor T2 are in the stress state of high voltage.
It can be seen that the level according to the first, second control signal is high in the course of work of the CMOS inverter
Low and the CMOS inverter input terminal In signal level height only has the first transistor T1, the within the same time
A transistor in two-transistor T2, third transistor T3 and the 4th transistor T4 is in stress state, relatively reduces every
A transistor is in the stress time under high-voltage state, implements the CMOS inverter in the embodiment of the present invention, can solve
In the existing phase inverter output biggish circuit of pressure difference, core transistor easily causes the transistor longevity because being chronically at high-voltage state
The problem of life decline.
Referring to Fig. 3, Fig. 3 is the schematic diagram of another CMOS inverter disclosed by the embodiments of the present invention.
As shown in figure 3, the circuit framework and group of CMOS inverter shown in the present embodiment and CMOS inverter shown in Fig. 2
It is integral identical, the description in above-described embodiment to CMOS inverter shown in Fig. 2 is specifically please referred to, details are not described herein.
Further, difference is, in CMOS inverter described in embodiment shown in Fig. 3, first choosing
Selecting device 100 includes first choice circuit 101 and the second selection circuit 102, in which: the first choice circuit 101 and the second choosing
It selects circuit 102 and accesses the first control signal LC1 and second control signal LC2, the first choice circuit 101 and second
Selection circuit 102 (the control terminal C1 for the first selector 100 being mentioned above) is electrically connected the CMOS inverter
Input terminal In (the control terminal C1 of the i.e. described first selector 100 is electrically connected the input terminal In of the CMOS inverter).It is described
First choice circuit 101 is electrically connected source electrode (i.e. the first output terminals A 1 company of first selector 100 of the first transistor T1
Connect the source electrode of the first transistor T1), second selection circuit 102 is electrically connected the source electrode of the third transistor T3
(i.e. the drain electrode that the second output terminal A2 of first selector 100 connects the third transistor T3).
In the schematic diagram of CMOS inverter shown in Fig. 3, when the second control signal LC2 is low level or the CMOS
When the input terminal In input high level signal of phase inverter, second selection circuit 102 works, then the first selector 100
Second output terminal A2 export first control signal LC1.When the first control signal LC1 is low level or the CMOS reverse phase
When the input terminal In input high level signal of device, the first choice circuit 101 works, then the of the first selector 100
One output terminals A 1 exports second control signal LC2.
Further, the second selector 200 includes third selection circuit 201 and the 4th selection circuit 202, in which:
The third selection circuit 201 and the 4th selection circuit 202 access the first control signal LC1 and second control signal
LC2, the 202 (control terminal for the second selector 200 being mentioned above of the third selection circuit 201 and the 4th selection circuit
C2) being electrically connected the input terminal In of the CMOS inverter, (the control terminal C2 of the i.e. described second selector 200 is electrically connected
The input terminal In of the CMOS inverter).The third selection circuit 201 connects the source electrode (i.e. of the second transistor T2
First output end B1 of two selectors 200 connects the source electrode of the second transistor T2), the 4th selection circuit 202 connection
(i.e. the second output terminal B2 of second selector 200 connects the source of the 4th transistor T4 to the source electrode of the 4th transistor T4
Pole).
In the schematic diagram of CMOS inverter shown in Fig. 3, when the first control signal LC1 is high level or described
When the input terminal In input low level signal of CMOS inverter, the third selection circuit 201 works, then the second selector
200 the first output end B1 exports second control signal LC2；When the second control signal LC2 is high level or described
When the input terminal In input low level signal of CMOS inverter, the 4th selection circuit 202 works, then the second selector
200 second output terminal B2 exports first control signal LC1.
In the schematic diagram of CMOS inverter shown in Fig. 3, in the first control signal LC1 and the second control letter
Under the control of number LC2, an output end (the first output terminals A 1 or second output terminal A2) for the first selector 100 is exported
The control signal of high level, an output end (the first output end B1 or second output terminal B2) for the second selector 200
Export low level control signal；Wherein, the second output terminal A2 and the second selector 200 of the first selector 100
The first output end B1 synchronism output opposite levels, the first output terminals A 1 of the first selector 100 and it is described second selection
The second output terminal B2 synchronism output opposite levels of device 200.When the input terminal In input high level signal of the CMOS inverter
When, another output end of the first selector 100 exports low level, when the input terminal In of the CMOS inverter inputs low electricity
When ordinary mail, another output end of the second selector 200 exports high level.
Referring to Fig. 4, Fig. 4 is the schematic diagram of another CMOS inverter disclosed by the embodiments of the present invention.As shown in figure 3,
CMOS inverter shown in the present embodiment and the circuit framework and group of Fig. 2 and CMOS inverter shown in Fig. 3 are integral identical,
The description in above-described embodiment to CMOS inverter shown in Fig. 2 and Fig. 3 is specifically please referred to, details are not described herein.
Further, difference is, in CMOS inverter described in embodiment shown in Fig. 4, first choosing
Selecting circuit 101 includes the 5th transistor T5 and the 6th transistor T6.Wherein: the grid of the 5th transistor T5 access described the
One control signal LC1, the grid of the 6th transistor T6 connects the input terminal In of the CMOS inverter, and (i.e. the grid of T6 connects
Meet the control terminal C1 for the first selector 100 being mentioned above), the source electrode and the 6th transistor of the 5th transistor T5
The drain electrode of T6 accesses the second control signal LC2, and the drain electrode of the 5th transistor T5 is with the 6th transistor T6's
Source electrode is electrically connected to the first output terminals A 1 of the first selector 100.
Second selection circuit 102 includes the 7th transistor T7 and the 8th transistor T8.Wherein: the 7th transistor
The grid of T7 accesses the second control signal LC2, and the grid of the 8th transistor T8 connects the defeated of the CMOS inverter
Enter to hold In (the i.e. control terminal C1 for the first selector 100 that the grid connection of T8 is mentioned above, it is understood that be transistor
The grid of T6 and T8 constitutes the control terminal C1 of the first selector 100), the source electrode of the 7th transistor T7 and described
The drain electrode of eight transistor T8 accesses the first control signal LC1, the drain electrode of the 7th transistor T7 and the 8th crystalline substance
The source electrode of body pipe T8 is electrically connected to the second output terminal A2 of the first selector 100.
The third selection circuit 201 includes the 9th transistor T9 and the tenth transistor T10.Wherein: the 9th crystal
The grid of pipe T9 accesses the first control signal LC1, and the grid of the tenth transistor T10 connects the CMOS inverter
Input terminal In (i.e. the control terminal C2 for the second selector 200 that the grid connection of T10 is mentioned above), the 9th transistor T9
The drain electrode of source electrode and the tenth transistor T10 access the second control signal LC2, the leakage of the 9th transistor T9
The source electrode of pole and the tenth transistor T10 are electrically connected to the first output end B1 of the second selector 200.
4th selection circuit 202 includes the 11st transistor T11 and the tenth two-transistor T12, in which: the described tenth
Described in the grid connection of grid access the second control signal LC2, the tenth two-transistor T12 of one transistor T11
(i.e. the control terminal C2 for the second selector 200 that the grid connection of T12 is mentioned above, can also by the input terminal In of CMOS inverter
To be interpreted as, the grid of transistor T10 and T12 constitute the control terminal C2 of the second selector 200), the described 11st is brilliant
The drain electrode of the source electrode of body pipe T11 and the tenth two-transistor T12 access the first control signal LC1, and the described 11st
The drain electrode of transistor T11 and the source electrode of the tenth two-transistor T12 are electrically connected to the second of the second selector 200
Output end B2.
In the embodiment of the present invention, the opposite in phase of the first control signal LC1 and second control signal LC2, it is assumed that two
The high level of a control signal is 30V, and low level is -6V, and the waveform timing chart of two control signals is as shown in figure 5, following press
The two periods of t1, t2 shown in Fig. 5 illustrate the working condition of the CMOS inverter one by one:
Within the t1 period in waveform timing chart shown in fig. 5, the first control signal LC1 is high level,
Second control signal LC2 is low level, and the stress voltage of 4 core transistors of the CMOS inverter is as shown in table 1 below:
Concrete analysis process is as follows: within the t1 period, the first control signal LC1 is high level, the second control letter
Number LC2 is low level, the 7th transistor T7 and the 9th transistor T9 conducting, the second output of the first selector 100
Hold the first control signal LC1 of A2 output high level, the first output end B1 output the second control letter of the second selector 200
Number LC2, if within the t1 period CMOS inverter input terminal In input high level signal, the first selector
The 6th transistor T6 and the 8th transistor T8 conducting, the first output terminals A 1 of the first selector 100 in 100 export low electricity
Flat second control signal LC2, at this point, the input terminal In of the CMOS inverter is also brilliant by the second transistor T2 and the 4th
Body pipe T4 conducting, i.e. the pressure difference of the source and drain interpolar of second transistor T2 and the 4th transistor T4 is zero.The CMOS inverter
Output end Out export low level second control signal LC2, at this point, the voltage of the source-drain electrode of the first transistor T1 is equal
Pressure difference for LC2, i.e. the source and drain interpolar of the first transistor T1 is zero, and the pressure difference of the source and drain interpolar of the third transistor T3
It is larger, it is equal to the current potential absolute value of the difference of the first control signal LC1 and the second control signal LC2, is equal to 36V,
The i.e. only third transistor T3 is in the stress state of high voltage.
If the input terminal In input low level signal of the CMOS inverter in the t1 period, will be in second selector 200
The tenth transistor T10 and the tenth two-transistor T12 conducting, the high electricity of second output terminal B2 output of the second selector 200
Flat first control signal LC1, at this point, also the first transistor T1 and third transistor T3 are connected by input terminal In, i.e., the
The pressure difference of the source and drain interpolar of one transistor T1 and third transistor T3 is zero.The output end Out of the CMOS inverter is exported
The first control signal LC1 of high level, the voltage of the source and drain interpolar of the 4th transistor T4 is LC1 at this time, i.e., and the 4th
The pressure difference of the source and drain interpolar of transistor T4 is zero, and the pressure difference between the source-drain electrode of the second transistor T2 is larger, is equal to
The current potential absolute value of the difference of the first control signal LC1 and the second control signal LC2 are equal to 36V, i.e., only described second
Transistor T2 is in the stress state of high voltage.
It as the above analysis, is high level in the first control signal LC1, with the input terminal of the CMOS inverter
The variation of the high and low ordinary mail number of In, the second transistor T2 and the third transistor T3 are in the stress of high voltage in turn
State.
When in the t2 period in Fig. 5 waveform timing chart, the first control signal LC1 is low level, the second control
Signal LC2 is high level, and the concrete analysis process of the stress voltage of 4 core transistors of the CMOS inverter is similar with table 1,
Detailed analysis is no longer carried out herein, and concrete outcome is as shown in table 2 below:
Similarly, when the second control signal LC2 is high level, with the input terminal In of the CMOS inverter
The variation of high and low ordinary mail number, the first transistor T1 and the 4th transistor T4 are in the stress state of high voltage in turn.
It, can be according to the first control signal LC1's and second control signal LC2 in CMOS inverter shown in Fig. 4
The level height of level height and the inverter input In signal, within the same time, the only described the first transistor
A transistor in T1, second transistor T2, third transistor T3 and the 4th transistor T4 is in the stress state of high voltage,
The stress time that each transistor is in high-voltage state is relatively reduced, the CMOS inverter in the embodiment of the present invention is implemented,
Core transistor be can solve in existing phase inverter because being chronically at the problem of high-voltage state easily causes the transistor life to decline.
Preferably, the first control signal LC1 and the high level of the second control signal LC2 in one cycle
Accounting duration is equal with low level accounting duration, i.e., the height electricity of the described first control signal LC1 and the second control signal LC2
It is flat equal with low level duty ratio.It can make the first transistor T1, second transistor T2, third transistor T3 in this way
The time for being in stress state with the 4th transistor T4 is almost equal, and the loss of each transistor is identical.
Preferably, the 5th transistor T5, the 7th transistor T7, the tenth transistor T10, the tenth two-transistor T12 are
PMOS tube, the 6th transistor T6, the 8th transistor T8, the 9th transistor T9 and the 11st transistor T11 are NMOS tube.
Alternatively it is also possible to the type of the transistor in Fig. 4 and the control signal of access are accordingly changed,
It can achieve the effect of the embodiment of the present invention, herein with regard to no longer being repeated.
The embodiment of the present invention also provides a kind of electronic device using above-mentioned Fig. 2 to CMOS inverter shown in Fig. 4.This hair
CMOS inverter in bright embodiment can be adapted for being particularly suitable for anti-in any required electronic device using phase inverter
The occasion that the pressure difference of phase device output end changes greatly, i.e. first control signal LC1, the potential difference of second control signal LC2 are larger
When.For example, the CMOS inverter in the embodiment of the present invention can be applied in CMOS GOA circuit, GOA circuit can be improved
Stability.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means particular features, structures, materials, or characteristics described in conjunction with this embodiment or example
It is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are different
Surely identical embodiment or example is referred to.Moreover, the particular features, structures, materials, or characteristics of description can be any one
It can be combined in any suitable manner in a or multiple embodiment or examples.
It is provided for the embodiments of the invention CMOS inverter above and application is described in detail, it is used herein
A specific example illustrates the principle and implementation of the invention, and the above embodiments are only used to help understand originally
The method and its core concept of invention；At the same time, for those skilled in the art, according to the thought of the present invention, specific
There will be changes in embodiment and application range, in conclusion the content of the present specification should not be construed as to of the invention
Limitation.
Claims (10)
1. a kind of complementary metal oxide semiconductor (CMOS) phase inverter, which is characterized in that the CMOS inverter includes first
Selector and second selector, the first transistor, second transistor, third transistor and the 4th transistor, in which:
The first transistor, second transistor, third transistor and the 4th transistor grid to be connected to the CMOS anti-
The drain electrode of the input terminal of phase device, the first transistor, second transistor, third transistor and the 4th transistor is connected to institute
The output end of CMOS inverter is stated, the source electrode of the first transistor is connected to the first output end of the first selector, institute
The source electrode for stating third transistor is connected to the second output terminal of the first selector, and the source electrode of the second transistor is connected to
First output end of the second selector, the source electrode of the 4th transistor are connected to the second output of the second selector
End；
The first selector and the second selector access first control signal and second control signal, first control
The opposite in phase of signal processed and the second control signal, the first selector and the second selector are electrically connected institute
State the input terminal of CMOS inverter；
It is described when the second control signal is the input terminal input high level signal of high level or the CMOS inverter
First output end of first selector exports second control signal；When the first control signal is high level or the CMOS
When the input terminal input high level signal of phase inverter, the second output terminal of the first selector exports first control signal；When
When the first control signal is the input terminal input low level signal of low level or the CMOS inverter, second choosing
Select the second output terminal output first control signal of device；When the second control signal is low level or the CMOS inverter
Input terminal input low level signal when, the first output end of the second selector exports second control signal.
2. CMOS inverter according to claim 1, which is characterized in that the first selector includes first choice circuit
With the second selection circuit, in which:
The first choice circuit and second selection circuit access the first control signal and the second control letter
Number, the first choice circuit and the second selection circuit are electrically connected the input terminal of the CMOS inverter, first choosing
The source electrode that circuit is electrically connected the first transistor is selected, second selection circuit is electrically connected the source of the third transistor
Pole.
3. CMOS inverter according to claim 1, which is characterized in that the second selector includes third selection circuit
With the 4th selection circuit, in which:
The third selection circuit and the 4th selection circuit access the first control signal and the second control letter
Number, the third selection circuit and the 4th selection circuit are electrically connected the input terminal of the CMOS inverter, the third choosing
The source electrode of second transistor described in circuit connection is selected, the 4th selection circuit connects the source electrode of the 4th transistor.
4. CMOS inverter according to claim 2, which is characterized in that the first choice circuit includes the 5th transistor
With the 6th transistor, in which:
The grid of 5th transistor accesses the first control signal, and the grid of the 6th transistor connects the CMOS
The input terminal of phase inverter, the drain electrode of the source electrode and the 6th transistor of the 5th transistor access the second control letter
Number, the drain electrode of the 5th transistor and the source electrode of the 6th transistor are electrically connected to the first of the first selector
Output end.
5. CMOS inverter according to claim 2, which is characterized in that second selection circuit includes the 7th transistor
With the 8th transistor, in which:
The grid of 7th transistor accesses the second control signal, and the grid of the 8th transistor connects the CMOS
The input terminal of phase inverter, the drain electrode of the source electrode and the 8th transistor of the 7th transistor access the first control letter
Number, the drain electrode of the 7th transistor and the source electrode of the 8th transistor are electrically connected to the second of the first selector
Output end.
6. CMOS inverter according to claim 3, which is characterized in that the third selection circuit includes the 9th transistor
With the tenth transistor, in which:
The grid of 9th transistor accesses the first control signal, and the grid of the tenth transistor connects the CMOS
The input terminal of phase inverter, the drain electrode of the source electrode and the tenth transistor of the 9th transistor access the second control letter
Number, the drain electrode of the 9th transistor and the source electrode of the tenth transistor are electrically connected to the first of the second selector
Output end.
7. CMOS inverter according to claim 3, which is characterized in that the 4th selection circuit includes the 11st crystal
Pipe and the tenth two-transistor, in which:
The grid of 11st transistor accesses the second control signal, described in the grid connection of the tenth two-transistor
The input terminal of CMOS inverter, the drain electrode of the source electrode of the 11st transistor and the tenth two-transistor access described
One control signal, the drain electrode of the 11st transistor and the source electrode of the tenth two-transistor are electrically connected to described second
The second output terminal of selector.
8. CMOS inverter according to claim 1, which is characterized in that the first transistor and the third transistor
It is PMOS tube, the second transistor and the 4th transistor are NMOS tube.
9. CMOS inverter according to claim 1-8, which is characterized in that the first control signal with it is described
The high level accounting duration of second control signal in one cycle is equal with low level accounting duration.
10. a kind of electronic device, which is characterized in that the electronic device includes as claimed in any one of claims 1-9 wherein
CMOS inverter.
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| CN201610671927.7A CN106330174B (en) | 2016-08-16 | 2016-08-16 | The electronic device of CMOS inverter and the application CMOS inverter |
| US15/308,586 US10050626B2 (en) | 2016-08-16 | 2016-08-31 | CMOS inverter and electronic device using the CMOS inverter |
| PCT/CN2016/097528 WO2018032538A1 (en) | 2016-08-16 | 2016-08-31 | Cmos inverter and electronic device applying same |
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| CN201610671927.7A CN106330174B (en) | 2016-08-16 | 2016-08-16 | The electronic device of CMOS inverter and the application CMOS inverter |
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| CN107196636B (en) * | 2017-05-18 | 2021-02-19 | 安徽大学 | Inverter for inhibiting single-event transient effect |
| CN109192169B (en) * | 2018-10-22 | 2020-05-26 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN116366034B (en) * | 2023-03-24 | 2023-11-07 | 江苏润石科技有限公司 | Logic circuit for solving nested control in starting process of CMOS inverter |
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| JP3468402B2 (en) * | 1997-12-26 | 2003-11-17 | シャープ株式会社 | Pass transistor circuit |
| JP2000068759A (en) * | 1998-08-25 | 2000-03-03 | Takatori Ikueikai:Kk | Inverting amplifier circuit |
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- 2016-08-16 CN CN201610671927.7A patent/CN106330174B/en active Active
- 2016-08-31 US US15/308,586 patent/US10050626B2/en active Active
- 2016-08-31 WO PCT/CN2016/097528 patent/WO2018032538A1/en active Application Filing
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| US6377086B1 (en) * | 1999-10-05 | 2002-04-23 | Agere Systems Guardian Corp. | Low power dual-voltage sense circuit buffer |
| US6975134B2 (en) * | 2004-04-08 | 2005-12-13 | International Business Machines Corporation | Buffer/driver circuits |
| US8456247B2 (en) * | 2011-01-19 | 2013-06-04 | International Business Machines Corporation | Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) |
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| Publication number | Publication date |
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| CN106330174A (en) | 2017-01-11 |
| US20180191350A1 (en) | 2018-07-05 |
| WO2018032538A1 (en) | 2018-02-22 |
| US10050626B2 (en) | 2018-08-14 |
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