JP2000114946A - Automatic reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an automatic reset circuit to be easily integrated without using an external part (capacitor or the like) on a semiconductor substrate. SOLUTION: This circuit is composed of an MOS transistor, capacitors for charging and a CMOS inverter, first receives an oscillation signal (CL1) to charge the capacitor 3 when power turned is on and next receives an oscillation signal (CL2) to charge the capacitor 4 from the capacitor 3, and these operations are repeated. When the potential of the capacitor 4 exceeds the threshold voltage of the CMOS inverter, the CMOS inverter is inverted, reset is canceled, and the device has a means which turns on a MOS transistor of feedback and holds reset cancellation once the CMOS inverter is inverted. Thus, it is possible to easily construct an auto reset circuit in a single semiconductor substrate without needing an external part because it is composed of the MOS transistor and the CMOS inverter and the capacitors for charging need only small capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an auto-reset circuit including an OS transistor.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional auto-reset circuit is configured by connecting a charging capacitor 30 and a resistor 40 having a time constant to an XRESET terminal 20 of a logic circuit 1. The operation of the conventional circuit will be described. Immediately after the power is supplied to the logic circuit 1, the capacitor 30 is at the "L" level because the capacitor 30 has not been charged. So XRES
At the ET terminal 20, a reset signal is output. Then the capacitor 30 charges through the resistor 40,
Since the signal becomes “H” level, the reset signal for the logic circuit 1 is released.

[0003]

In the conventional circuit,
The time from when the reset signal is output to when it is released is determined by the time constant CR. In an actual circuit, R is about 10
kΩ to several MΩ, C is about 0.01 μF to 1 μF, and the time constant is 1 to several hundred msec. The resistance value that can be realized on a semiconductor substrate is usually several MΩ or less, and the capacitor C is 10 pF or less.
sec. Therefore, the conventional auto reset circuit can be replaced with an IC
However, there is a problem that it is necessary to externally connect a capacitor. The present invention solves the problem of the conventional circuit (that is, it is not possible to incorporate the capacitor 3 as an internal circuit of the IC, but externally), and provides an automatic reset circuit which can be easily formed on a single semiconductor substrate. Is what you do.

[0004]

In order to solve the above-mentioned problems, an auto-reset circuit according to the present invention has a first end connected to a first power supply.
A first charging capacitor connected to the fixed potential terminal of the power supply, and a second charging capacitor connected at one end to the first fixed potential terminal of the power supply.
A charging capacitor, an oscillation circuit for generating a clock signal and an inverted signal without overlapping the clock signal by the power supply, a second fixed potential terminal of the power supply and the first
A first MOS transistor connected between the charging capacitors and a gate connected to the clock signal; a gate connected between the first charging capacitor and the second charging capacitor; A charging circuit configured to charge the first and second charging capacitors by an on / off operation, and to reset when the other end of the second charging capacitor reaches a predetermined potential. A CMOS inverter that outputs a signal, and the reset signal is input to a gate electrode and connected between the other end of the second charging capacitor and the second fixed potential terminal of the power supply. It is characterized by comprising a MOS transistor for holding the charge level at the power supply potential.

[0005]

Since the present invention has the above configuration, the reset signal is output immediately after the power is turned on, and the second charging capacitor is sequentially charged through the first charging capacitor in synchronization with the clock signal. 2 is equal to the threshold voltage Vth of the CMOS inverter.
Is exceeded, the CMOS inverter is inverted and the reset signal is released, whereby the MOS transistor whose output is connected to the gate electrode is turned on, and thereafter the reset signal is released regardless of the clock signal. Is held.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, 5, 6 and 7 are P-channel MOS transistors, 8 is a CMOS inverter, and 3,
4 is a charging capacitor, 10 and 11 are clock signal terminals, and 2 is a reset signal input terminal of the logic circuit 1. P
The source of the channel MOS transistor 5 is the power supply terminal 1
The drain 3 is connected to the source of the P-channel MOS transistor 6 and one end of the capacitor 3, and the gate is connected to the clock terminal 10. The drain of the transistor 6 is connected to one end of the capacitor 4 and the input terminal of the CMOS inverter 8, and the gate is connected to the clock terminal 11. The other end of each of the capacitors 3 and 4 is grounded. 12 is the power supply voltage VDD
A clock oscillation circuit that operates with clock terminal 1
Two non-overlapping two-phase clocks are output to 0 and 11, respectively.
A P-channel MOS transistor 7 for holding a voltage level has a source connected to a power supply terminal 13 and a drain connected to a CM.
Connected to the input gate of the OS inverter 8,
It is connected to the output of the CMOS inverter 8. The C
The output of the MOS inverter is connected to the reset signal input terminal 2 of the logic circuit 1. If the capacitances of the charging capacitors 3 and 4 are C3 and C4, respectively, C3 <C4.

Next, the operation of the present invention will be described in detail. When a power supply voltage is applied to the power supply terminal 13, FIG.
As shown in (1), it takes a finite time ta to increase from 0V to VDD. When the power is turned on, the capacitors 3 and 4 are completely discharged, and the connection portion 9 of the capacitor 4 is "L".
You are in a level state. Therefore, the reset terminal 2 through the inverter 8 is at the "H" level, and the logic circuit 1 is in a reset state. The P-channel MOS transistor 7 is turned off since the gate is at "H" level. FIG.
In (b) and (c), the clock signal CL1 (terminal 10) and the clock signal CL2 (terminal 11) of the clock oscillation circuit 12 rise as the power supply voltage rises, and the oscillation state starts. FIG. 3B shows the terminal 10, and FIG. 3C shows the terminal 1.
1 respectively. The time from power-on to clock signal input is shown in the timing chart of FIG.
Indicated by When the clock signal is input to terminals 10 and 11, P-channel transistors 5 and 6 are turned on when the gate signal is at "L" level. The on and off states are repeated in synchronization with the clock signal. When the P-channel transistor 5 is on, the P-channel transistor 6 is off, and at this time the charging capacitor 3 is charged.

Next, the P-channel transistor 5 is turned off, the P-channel transistor 6 is turned on, and the electric charge stored in the charging capacitor 3 moves to the charging capacitor 4. By this series of operations, the charging capacitor 4 is gradually charged as shown in FIG. When the potential of the connection portion 9 of the charging capacitor 4 is
Above the threshold voltage Vth, the output level of the CMOS inverter 8 is inverted to the "L" level as shown in FIG. 3E, and the logic circuit 1 is released from the reset state. As a result, the P-channel MOS transistor 7 is turned on, and the potential of the connection portion 9 of the capacitor 4 is maintained at the "H" level as shown in FIG. 3D regardless of the subsequent clock signal. In the time chart of FIG. 3, tb is the time until the reset signal is released.
Tb can be changed by changing the ratio of the capacitances C3 and C4 of the charging capacitor. As is apparent from the above operation, the circuit of the present invention is characterized in that the reset signal is output immediately after the power is turned on, and the reset state of the logic circuit is released after the clock signal becomes stable.

[0010]

As described above, in the circuit of the present invention, the resistor 40 of the conventional circuit is unnecessary and the capacitors 3 and 4 are unnecessary.
Both require only a small capacity, so there is no need to use external components.
Therefore, there is an effect that the auto reset circuit can be easily formed in a single semiconductor substrate. INDUSTRIAL APPLICABILITY The present invention can be applied as an auto reset circuit that can be incorporated in all integrated circuits having a clock signal source such as a microcomputer and a clock.

[Brief description of the drawings]

FIG. 1 is an automatic reset circuit according to the present invention.

FIG. 2 shows a conventional auto reset circuit.

FIG. 3 is a timing chart in the automatic reset circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic circuit 2 RESET terminal 3 Capacitor 4 Capacitor 5 P-channel type MOS transistor 6 P-channel type MOS transistor 7 P-channel type MOS transistor 8 CMOS inverter 10 CL1 terminal 11 CL2 terminal 12 Clock oscillation circuit 13 VDD terminal 20 XRESET terminal 30 Capacitor 40 resistance

Claims (2)

[Claims] A first charging capacitor having one end connected to a first fixed potential terminal of a power supply; a second charging capacitor having one end connected to a first fixed potential terminal of the power supply; An oscillating circuit for generating a clock signal and a non-overlapping inverted signal of the clock signal by a power supply, connected between a second fixed potential terminal of the power supply and the first charging capacitor, and a gate connected to the clock signal; Connected first
, And a second MOS transistor connected between the first charging capacitor and the second charging capacitor and having a gate connected to the inversion signal. A charging circuit for charging a second charging capacitor and the second charging capacitor;
A CMOS inverter that outputs a reset signal when the other end of the charging capacitor attains a predetermined potential, and the reset signal is input to a gate electrode, and the other end of the second charging capacitor and the second fixed potential of the power supply An auto-reset circuit comprising a MOS transistor connected between terminals and holding a charge level of the second charging capacitor at a power supply potential. 2. The semiconductor device according to claim 1, wherein said MOS transistor is a P or N type M transistor.
2. The auto reset circuit according to claim 1, wherein the auto reset circuit is an OS transistor.