JPS6017177B2 - voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage generation circuit suitable for use as a drive circuit, and particularly to a drive circuit realized as a semiconductor device.

In recent years, complementary insulated gate field effect transistors (CM) have been used to reduce power consumption in calculators and other devices.
(referred to as OSFET) is increasing in number.

FIG. 1 shows conventional C MOSFETs Q, . , Q, is an example of an inverter configured with 2. In this figure 1, Q
、． ,Q. 2 are complementary C MOSFETs Q, .
is an N-channel FET, and Q and 2 are P-channel FEs.
T, and the above Q, . The source electrodes of Q, ., are grounded, the drain electrodes of Q,2 are connected to the power supply, and The drain electrode of Q, . is connected to the source electrode of Q,2. , Q, 2 are connected to the input signal 11 to form an inverter. Q, 3 is an N-channel FET whose drain electrode is connected to the input terminal 12, whose source electrode is connected to the output terminal 0, and whose gate electrode is connected to the above-mentioned Q, . , Q, 2, the output from the inverter is input. When a high-level input is applied to the input terminal 11 in a circuit configured as described above, the P-channel type FETQ, 2 is in a cut-off state, and the N-channel type FETQ, . becomes conductive and a low level is generated as an output, and the N-channel FETQ,
A low level is applied to the gate electrode of FETQ,3.
is in a cutoff state, the signal from input signal 12 is cut off, and no output is generated at output terminal 0. Next, input signal 11
When a low level input is applied to N-channel FETQ, . is in a cut-off state, and the P-channel FET
becomes conductive, and almost the power supply voltage (10VD voltage), that is, a high level, is generated as the output of the inverter, and the high level is applied to the gate electrode of the N-channel FET Q,3 in the next stage. becomes conductive, and the signal from input signal 12 is sent to output terminal 0. However, in this case, if the output of the inverter is at a high level, there is a possibility that the N-channel type FETQ, 3 may not be in a completely conductive state, and the signal from the input terminal 12 will not be sent to the output terminal 0 as a sufficient level. There is a fear.

That is, since the drain electrode and source electrode of the N-channel FET Q,3 are not at the same potential as the substrate electrode (also called back gate voltage),
ETQ,. , Q, 2, each threshold voltage V,
It ends up being more expensive.

In other words, in order to send the signal at the input terminal 12 as it is to the output terminal 0, the voltage VG of the gate electrode of N-channel type FETQ, 3 is connected to the power supply voltage Vo and the N-channel type FETQ.
, 3 plus the threshold voltage VT3, that is, the voltage must be VGZVD + VT3. Therefore, the power supply voltage must be higher than the source voltage and drain voltage. Furthermore, inconveniences occur such that FETs Q and 3 cannot be switched near the source voltage and drain voltage (10 VD voltage). An object of the present invention is to provide a drive circuit that improves these drawbacks.

The drive circuit according to the present invention includes a logic circuit such as an inverter circuit or a NOR circuit, an insulated gate field effect transistor whose conduction is controlled by the output of the logic circuit, and a static transistor with one electrode connected to the output of the logic circuit. It is characterized by having a capacitor and means for selectively applying a periodic potential such as a clock signal to other electrodes of the capacitor, that is, in response to a predetermined logic output.

According to the present invention, the output of the logic circuit, especially the output of /... This is suitable for a drive circuit realized on a semiconductor substrate.

According to the present invention, the sources and drains of a first insulated gate field effect transistor of conductivity type and a second insulated gate field effect transistor of opposite conductivity type are connected, and the drain electrode is used as a clock pulse signal input terminal. The gate electrode is connected to one side electrode of the voltage boosting capacitor, and the control means applies an input signal and an inverted input signal of the input signal to each gate electrode, and passes or blocks the clock pulse signal. A controlled clock pulse signal is applied to the voltage boosting capacitor, and two third and fourth insulated gate field effect transistors of the same conductivity type as the first or second are connected in series, and the electrodes at both ends are different from each other. connected to a potential power supply, each gate electrode applies an input signal and an inverted input signal, and the series connection point is connected to another fin pole of the voltage boosting capacitor and has the same conductivity as the first or second. It is possible to obtain a drive circuit that is connected to the gate electrode of the fifth insulated gate field effect transistor to control conduction and cutoff of the fifth transistor.

Further, according to the invention, in a complementary insulated gate field effect transistor (IGFET) integrated circuit formed on the same semiconductor, in the IGFET integrated circuit portion including a capacitive element that generates a voltage larger than the absolute value of the power supply voltage on the substrate. A voltage that applies a voltage greater than the absolute value of the power supply voltage to the gate of at least one IGFET to make it conductive, and a voltage that makes the main stage that outputs the voltage applied to the drain of this IGFET to the source and the gate of the IGFET non-conductive. A complementary insulated gate field effect transistor integrated circuit can also be obtained that includes means for applying .

A first embodiment of the present invention will be described below with reference to FIGS. 2 and 3. In FIG. 2, the drain electrode is connected to the clock pulse terminal, the source electrode is connected to the source electrode of an N-channel FET Q2, which will be described later, and the gate electrode is connected to the output of the inverting gate G of the input signal terminal 11. P-channel type FETQ, whose drain electrode is connected to the clock pulse terminal, and whose source electrode is connected to the source electrode of the P-channel type FETQ, and to one side electrode of the voltage boosting capacitor C at the node Y, N-channel type F with gate electrode connected to input signal terminal 1
The drain electrode of ETQ2 is connected to a power supply, the source electrode is connected to the drain electrode of an N-channel type FETQ described later, and further connected to the other one side electrode of the voltage boosting capacitor C, and the gate electrode is connected to the input signal terminal 11. and an N-channel FETQ whose drain electrode is connected to the source electrode of the N-channel FETQ, whose source electrode is grounded, and whose gate electrode is connected to the output of the inverting gate G of the input signal 11. and the gate electrode is connected to the source electrode of the N-channel FETQ and the N-channel FETQ.
It is connected to the node x between the drain electrode of the channel type FETQ and the voltage boosting capacitor C, and is composed of an N-channel type FETQ5 whose drain electrode is connected to the input signal terminal 12 and whose source electrode is connected to the output terminal 0. .

Further, the voltage boosting capacitor C is charged and discharged in synchronization with the clock pulse by switching means of complementary FETs Q, Q2. Next, the operation of the drive circuit according to this embodiment will be explained with reference to FIG.

When the input signal 11 is generated during a clock pulse as shown in FIG. 3, first, when the input signal 11 is at a low level, FETs Q, , Q2 and Q4 are cut off and cut off until the clock pulse ends. Further, FETQ3 becomes conductive, and a low level is generated at the connection point X. Also FET
Q is in a cutoff state because the connection point x is at a low level, and the signal from input terminal 12 is not sent to output terminal 0. Next, when the input signal 11 becomes high level, the FET
Q, , Q2 and Q become conductive, and the clock pulse is sent to the node Y to which the voltage boosting capacitor C is connected.

Also, FET Q3 is cut off in this case. And since the low level (ground voltage) of the clock pulse ◇ as shown in Figure 3 is applied to the connection point Y, the OV (ground voltage)
It is in. Also, FETQ is in a conductive state, and the power supply voltage +V
D is sent out, but here, due to the influence of the back gate voltage as in the conventional case, a voltage lower by the threshold voltage yT of the FET Q4 is sent out to the node x. That is, the voltage at the node x is 10VD-VT. Then, a voltage of 1 VD-VT at the node X is applied to the gate electrode of the FET, so that the FET Q5 is in an unstable conductive state. Next, when the clock pulse J reaches the level (power supply voltage), the power supply voltage (10 VD voltage) is sent to the node Y, the voltage boosting capacitor C is charged with the power supply voltage (10 VD voltage), and then The voltage of 10VD-VT and the rumored voltage of 10VD at the connection point Y are superimposed.

In other words, the voltage of the clock pulse J is increased by 10 VD to the voltage of 10 VD - VT at the node Y, so the voltage at the node Y is increased by 10 VD.
A voltage of 2VD-VT is sent out. and FET
A voltage of 2VD-VT at the junction point is applied to the false gate electrode, and since the influence of the back gate voltage can be ignored,
FETQ5 can obtain a sufficient conductive state. Next, when the clock pulse ◇ becomes low level (ground voltage), OV is sent to the node Y, the 10VD voltage charged in the voltage boosting capacitor C is discharged, and the 2VD-V of the node
The voltage at T becomes 10VD-VT.

Then, the voltage at the node X, ie, 10VD-VT, is applied to the gate electrode of FETQ5, and the same operation is repeated due to the unstable clock pulse. and input signal 1
1 becomes low level, FETs Q, , Q2 and Q are cut off, and no clock pulses are sent to the node Y.

Further, FETQ becomes conductive, a low level is sent to node x, and a signal at node x is sent to the gate electrode of FETQ5.

A low level is applied, FET Q5 is completely cut off, and no signal from input signal 12 is sent to output terminal 0. In this way, the circuit according to the present invention uses a clock pulse? A signal whose level changes at a shorter cycle than the input signal 11 is used as the input signal 11, and when a low level is output to the connection point X, the transistors Q, Q2 are cut off so that the clock pulse ◇ is not supplied to the capacitor C. , it also has the following special effects: In other words, what if it's a clock pulse? When is changed at the same period as the input signal 11, charging of the node Y to the 10 Vo level during the clock pulse is performed only once during the period when the input signal 11 is at the /. The level of the boosted voltage at is reduced by leakage current, and as a result, the transistor's voltage decreases from V to V. It becomes impossible to drive above the level. Moreover, if a clock pulse with such a period is used, unless there is a timing relationship such that the clock pulse pulse is inverted from low to high level after the input signal 11 is inverted from low to /-- level, the connection point × No boosted voltage can be obtained. In other words, the clock pulse is used exclusively for boosting the voltage by the capacitor C, making it extremely difficult to use this clock pulse J to control the timing of other circuits. A timing circuit is required to create accurate timing. In the present invention, clock pulse? is input signal 1
Since the level changes in a cycle shorter than 1, the input signal 11
During the period when is at a high level, the connection point Y is
charged to the level. Therefore, the level of the boosted voltage at the node X is prevented from decreasing due to leakage current. Also,
Since it is not necessary to match the level change of the clock pulser and the level change of the input signal 11, this pulse J can be used for timing control to other circuits. When the input signal is at a low level, the transistor Q becomes conductive and the node x becomes at a low level.

At this time, in the present invention, transistors Q, , Q2 are cut off, and clock pulse J is not supplied to capacitor C. If transistors Q, . If Q2 is omitted,
Clock pulse 0 continues to be supplied to capacitor C and continues to charge it. Therefore, the potential at the node X cannot be fixed at a low level, and increases as the capacitor C is charged, which causes a malfunction in which the transistor becomes conductive. In the present invention, since the clock ◇ is not supplied to the capacitor C by the transistors Q, , Q2, the potential of the coupling line X is held at a low level. Next, a second embodiment of the present invention will be described with reference to FIGS. 4 to 6. This embodiment shows an example in which the present invention is applied to driving a four-level segment signal generation circuit for driving a liquid crystal display.

FIG. 4 shows a complementary circuit for generating four levels using a general insulated gate field effect transistor. Power supply voltage terminal -V. . Resistors R1, R2, and R3, which are connected in series and have the same resistance value, are formed using a method such as thermal diffusion or ion implantation between the terminal and the ground potential terminal GND. Therefore, the potential of contact B is 2'3Voo, and the potential of contact C is 1/3V.
. . become. In other words, the potential set by resistor division is IGF
By applying a control signal voltage to the terminals G to which the gates of ETQ2, Q22, Q-fever, and Q-heat are connected, E, F
Supplied to the terminal. In this case, IGFETQ2, ,Q2 are n-channel transistors, and IGFETQ,Q
24 is a P-channel transistor.

Further, the substrate of the n-channel transistor is connected to -VDo, and the substrate of the p-channel transistor is connected to GND (ground). Here, the sources of the transistors Q2 and Q23 and the substrate are at the same potential, but the sources of the IGFETs Q2 and Q23 are each back gate biased to IV/3l with respect to the substrate. In such a configuration, as the absolute value of the power supply voltage -Voo becomes lower and lower due to lower power consumption, the threshold value fluctuation of the IGFET due to the back gate bias effect cannot be ignored, and the following problem occurs. In other words, this circuit is generally driven by the control signal voltage at the terminal G, which oscillates between the power supply -Voo and the ground potential GND.

Normally, when the terminal is GND, ICFET2 is turned on -Voo
When , the Q base turns on, but the source is 1/3 due to resistance
Voo, 2/3V. . is applied, there is a back gate bias between the source and the substrate, and the potential between the gate and source is 12/3 Vool, so the drive current of these transistors is lower than that of IGFETs Q2, Q24, which do not have a back gate bias. small. Therefore, in order to increase the drive current of the transistor Q side Q23, the absolute value of the threshold voltage of the IGFET Q223 is reduced by a method such as ion implantation, or the decrease in current drive ability is compensated for by increasing the size of the transistor. However, the former has a low threshold voltage, which increases channel leakage, and the latter requires a large area, which not only increases the chip area, but also has the drawback that basic circuit operation may not be satisfactory. Yes, lower power consumption,
This was not desirable as it went against the trend of higher integration. In this embodiment, the terminal ○. The present invention is applied to conduction control of IGFETs Q22 and Q23 controlled by a control signal applied to H', and will be explained in detail with reference to FIGS. 5 and 6. As shown in FIG. 5, logic input 12 defines the control signal applied to the terminal
It is applied to each gate of GFETQ26, Q29 and n-channel IGFETQ. Alternatively, the logic input 12 is applied to each gate of the P-channel IGFETQ25, Q25 through the inverter GI. P-channel IGFETQ2
The source of 5 is connected to the power supply -Voo, and the drain is grounded at the connection point D of the P-channel IGFETQ.
Connected to 26 sources. P channel IGFETQ
Crab source and drain and n-channel IGFETQ
The sources and drains of 27 are connected in common to a clock signal J, a capacitance C having one electrode connected to a node D, and the other electrode connected at a node C. The source of this node C is the power supply -VD. The drain of P-channel transistor Q29 connected to is also connected. The above-mentioned IGFETs Q27 and Q28 constitute a capacitor C by CMOS and a transfer gate for charging. The IGFET Q29 is provided to sufficiently bring the output ○ to the ND level when the connection point D changes to the GND level, and is not necessarily required. Connection point D is the fourth
It is connected to the control terminal of the level drive circuit shown in the figure. The operation will be explained with reference to FIG.

When the input 12 is at a low level (one VDo level), a "high" level (GND level) is output to the output node D.
This is connected to the gate of IGFETQ23 and the IGFET
Q23 is in a non-conductive state. Input 12 is “low”
)” level to “high (GND)” level, the output D changes from “
“L (one Voo)” then “H” then “Voo”
-VT" and then "L", the level of "2V blood -VT" is output, and for the subsequent clock signal ◇, the output is 2Vo. The amplitude is between the voltages of 1VT and V..1V. The output ○ obtained in this way is connected to IGFETQ2.
When connected to the gate of 3 through the terminal, IGFETQ2
3 is turned on by its output voltage and the power supply voltage (
1V. . ) higher gate voltage l2V in absolute value than
oo-VT I works more effectively. In this case, the gate voltage of IGFETQ23 can be increased by IVDo-VTI.

Similarly, a voltage higher than the ground potential can be applied to the gate of IGFETQ22. In this way, it is possible to increase the gate voltage of the transistor that is back-gate biased, thereby increasing the drive ability of the IGFET, and at the same time being able to deal with increases in threshold voltage over a wider range. . According to the present invention, the clock pulse voltage is charged and discharged to the voltage boosting capacitor C, and the output of the charging and discharging voltage is used to control the IGFET of the next stage.
The voltage applied to the gate electrode can now ignore the influence of the back gate voltage, and a sufficiently conductive state can be obtained, which has a significant effect.

In addition, by changing the ratio of the clock pulse ◇ in the present invention or increasing the frequency, the period in which the voltage boosting capacitor C is charged and discharged is lengthened. can be reduced.

Further, in one embodiment of the present invention, the FET configuration is used as shown in FIG. 2, but it goes without saying that it can be implemented by changing the combination of channel shapes or changing the polarity of the power supply.

Further, the logic circuit is not limited to an inverter, and the structure of the logic circuit may be arbitrary.

[Brief explanation of the drawing]

Figure 1 is the slave drive circuit diagram, Figure 2 is the first diagram of the present invention.
FIG. 3 is a drive circuit diagram showing an embodiment of the present invention, and FIG. 3 is an operation waveform diagram of the embodiment. FIG. 4 shows a signal generation circuit for a liquid crystal using complementary insulated gate field effect transistors. FIG. 5 is a diagram showing a drive circuit according to a second embodiment of the present invention, which controls the gate voltage G and the gate voltage in FIG. 4. FIG. 6 is a timing chart of each input/output terminal voltage in FIG. 5. Symbols in the diagram,
Q2, Q3, Q4, Q5, Q, . ,Q,3,Q2,,Q
22, Q27...n-channel FET, Q,,Q,2
, Q23, Q Shigeru, Q25, Q26, Q28...
P channel type FET, G, G. ...Inverter,
C,C.・・・・・・Boosting capacity. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 between first and second power supply terminals, an output terminal, a first field effect transistor connected between the first power supply terminal and the output terminal, and the second power supply terminal and the output terminal; a connected second field effect transistor; when the input signal is at one logic level, at least the second transistor is conductive; when the input signal is at the other logic level, the first and second transistors are turned on; In a voltage generating circuit having circuit means for conducting and cutting off, and a capacitor having one end connected to the output terminal, a clock is supplied with a signal voltage whose level changes at a shorter period than the input signal. a terminal, a switch means connected between the other end of the capacitor and the clock terminal, and becomes conductive when the input signal is at the other logic level to supply the signal voltage to the capacitor. A voltage generation circuit further comprising: