JPH03153119A - Power supply start detection circuit - Google Patents

Abstract

PURPOSE:To start a load circuit stably by increasing a threshold voltage through the adjustment of the quantity of the impurity of a channel region of a 2nd conductive element or making the gate polarity different, and extending a power application delay time. CONSTITUTION:The level V2 of the input terminal of an inverter 5 is equal to the level VDD of a power voltage terminal. As lapse of time, a charge is stored in a capacitor 2 and the level V1 of the drain of a p-MOS 1 is gradually increased. When the gate-source voltage VGS of an n-MOS 4 is larger than the threshold voltage of the n-MOS 4, the n-MOS 4 is turned on and a charge is stored in a capacitor 3 and the level V2 of the input terminal of the inverter 5 is decreased. Moreover, when the level V2 is decreased up to a logic level of the inverter 5, the level V3 at the output terminal of the inverter 5 is inverted from a low level to a high level and an initialized signal is obtained. Thus, the load circuit is stably started while reducing the area occupied in the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power supply start detection circuit used in various electronic devices and the like.

[Prior art] A conventional power supply start-up detection circuit detects 'thi' after turning on the power.
In order to lengthen the time until the initialization signal appears at the output of the s start detection circuit (hereinafter referred to as the t4 power-on delay time), this was achieved by increasing the resistance value and capacitance value of the resistor means. . In other words, as shown in FIG. 3, by increasing the resistance value of the p-channel MO5 type transistor (hereinafter referred to as p-MO8) 10 and the value of the capacitor 11, which is the resistance means, the time constant is increased and the power is turned on. The delay time was getting longer.

[Problem to be solved by the invention] However, as in the prior art described above, the p-MOS 1 is used.

When the resistance value and the value of the capacitance 11 are increased, the pattern area becomes larger accordingly. Furthermore, as the time constant becomes larger, the rise time becomes longer and abnormal oscillation is more likely to occur in the next stage gate circuit, so it is necessary to insert a Schmitt trigger circuit or the like to adjust the waveform, which also increases the pattern area. Therefore, the conventional technique has the problem that the pattern area becomes large, and the possibility of picking up defects that exist stochastically increases.

SUMMARY OF THE INVENTION The present invention is intended to solve these problems.The purpose of the present invention is to start a power supply that can stably start a load circuit with a long power-on time while minimizing the increase in pattern area. A detection circuit is provided.

[Means for Solving the Problems] The power supply starting circuit of the present invention includes a first conductive element whose first terminal is connected to the electric R voltage gqi and whose second terminal is grounded; 1)
1j, the first charge storage means connected between the third terminal of the first conductive element and the ground, the first terminal being grounded;
a second conductive element having a second terminal connected to a third terminal of the first conductive element and having a threshold voltage larger than that of other conductive elements;
a second charge storage means connected between a third terminal of the second conductive element and a power supply voltage source; and an inverting circuit whose input terminal is connected to the third terminal of the second conductive element. It is characterized by

[Operation] According to the above configuration of the present invention, whether to adjust the amount of impurities in the channel region of the second conductive element is determined by
The threshold voltage can be increased by increasing the threshold voltage by changing the polarity of the signals to different polarities, and thereby increasing the power-on delay time. The falling time can also be shortened, making it difficult to cause abnormal oscillation of the gate.

[Examples] Examples of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram in an embodiment of the present invention. 1- is
The first conductive element is a p-MOS. The first terminal, the second terminal, and the third terminal represent a source, a gate, and a drain, respectively. Since the gate of pMO3I is grounded, it is always in the on state, and thus acts as a resistor. 2 is a capacitor which is the first charge storage means. 3
is a capacitor which is the second charge storage means. 4 is an rl MQS which performs a switching operation and is a second conductive element. The first terminal, second terminal, and third terminal represent a source, a gate, and a drain, respectively. 5 is an inverter which is an inversion circuit.

At the time when the iri source is turned on, there is no charge stored in the capacitor 2, so the current voltage between the ends of the capacitor 2 is O volts, that is, the voltage of p - M OS 1 is The potential ■1 of the input terminal is equal to the potential VSS (“0)” of the ground terminal. Therefore, n-yO34 is in an off state.

Also, the charge is not added to capacitor 3.'C1 capacitor 3
The voltage appearing between the terminals is O volts, that is, the potential ■2 at the input terminal of the inverter 50 is equal to the power supply voltage E7A, and the potential V9. be equivalent to. Therefore, the potential at the output terminal of inverter 5 is at a low level.

As time passes, charge is accumulated in capacitor 2, and p −
The potential ■1 of Do1/In of M OS ] gradually rises.

In other words, the voltage between the gate and source of n-MQS4 V GS
(=VTV55=V)) increases.

When the voltage V,s becomes larger than the threshold voltage of n-MOS 4, n-MQS4 turns on,
Charge is accumulated in the capacitor 3, and the potential 2 at the input terminal of the inverter 5 decreases. When the potential (2) further drops to the logic level of the inverter 5, the potential (3) at the output terminal of the inverter 5 is inverted from low level to high level, and an initialization signal is obtained.

Therefore, in order to lengthen the power-on delay time, n
-M O','', if you increase the J threshold voltage of 4, then J:
stomach. To increase the threshold voltage, there are methods such as adjusting the amount of impurities in the channel region and making the polarities of -4, -7, and -1 different.

FIG. 2 is a diagram that does not show the changes in potential at the famous hot springs in FIG. 1. (2), 1A represent the threshold voltage of n-MQS4, and Vl represents the logic level of inverter 5. t, represents the power-on time, t, represents the initialization signal, that is, the time when the potential of the output terminal of the inverter 5 changes from low level 17 to high level, and the power-on delay time is t, -1-
It can be found as 0.

According to our calculations, the power-on delay times of the circuit of the present invention and the conventional circuit were 31 us and 2311 s, respectively.

However, the power supply voltage is: 1.58V, capacitance 2, capacitance 3, capacitance 1] are 10 pI", 10 pF, 20 pF, respectively.
The threshold voltages of p=MO31, n-MQS4, and p-MO8IO are each 10.

Calculated at 5v, 1.2v, -0.5V.

Note that since the pattern area occupied by the transistor is smaller than that of the capacitor, the pattern areas occupied by both circuits having the above values are considered to be approximately equal. Therefore, it can be said that the pattern area occupied by the circuit required to obtain the same power-on delay time is smaller in the circuit of the present invention.

Further, in the circuit of the present invention, even if the p-MOS and nMO8 are replaced, a circuit having the same function can be constructed.

[Effects of the Invention] Although the number of elements constituting the circuit of the present invention is increased compared to the prior art, the pattern area required to obtain the same power-on delay time is smaller than n in Fig. 1. - It can be reduced by increasing the threshold voltage of MOS4. In addition, the circuit of the present invention has a waveform rise time,
Since the power-on delay time is increased without increasing the fall time, there is no need to include a Schmitt trigger circuit.

Therefore, the present invention has the effect of stably starting the load circuit while reducing the area occupied by the circuit.

[Brief explanation of the drawing]

FIG. 1 is a power supply startup circuit diagram of the present invention. FIG. 2 is a diagram showing changes in potential at each location in FIG. 1. Figure 3 is a conventional power supply startup circuit diagram. FIG. 4 is a diagram showing changes in potential at each location in FIG. 3. 1.10... p-channel MO3 type transistor 2.3.11... capacitance 41.・N-channel MO3 type transistor 5.12・
・More than inverter

Claims (1)

[Claims] a first conductive element having a first terminal connected to a power supply voltage source and a second terminal connected to ground; a first charge storage means connected between a third terminal of the first conductive element and ground; a second conductive element whose terminal is grounded, whose second terminal is connected to the third terminal of the first conductive element, and whose threshold voltage is greater than that of the other conductive elements; A power start detection circuit comprising: a second charge storage means connected between a power supply voltage source; and an inverting circuit whose input terminal is connected to a third terminal of the second conductive element.