CN104579306A - Low-power phase inverter circuit - Google Patents
Low-power phase inverter circuit Download PDFInfo
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- CN104579306A CN104579306A CN201310666639.9A CN201310666639A CN104579306A CN 104579306 A CN104579306 A CN 104579306A CN 201310666639 A CN201310666639 A CN 201310666639A CN 104579306 A CN104579306 A CN 104579306A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
The invention relates to a low-power phase inverter circuit which comprises a first transistor and a second transistor, wherein input signals are received by the grid terminals of the first transistor and the second transistor; the first transistor and the second transistor are connected to a third transistor and a fourth transistor through the source terminals of the first transistor and the second transistor respectively; the third transistor and the fourth transistor are connected with a fifth transistor and a sixth transistor in parallel. The third transistor and the fourth transistor are continuously conducted, and the fifth transistor and the sixth transistor are controlled to ensure that when the input signals are switched to be in another state from one state, short-circuit current flowing through the first transistor and the second transistor is reduced.
Description
Technical field
Present invention relates in general to electronic circuit, and relate more specifically to inverter circuit.
Background technology
In recent years witness for the growth of the demand of miniature high performance electronics.This demand mainly through the integrated circuit (IC) that utilizes very lagre scale integrated circuit (VLSIC) (VLSI) to design development and be solved.Utilize VLSI, monolithic IC can have a hundreds of thousands transistor.This is by realizing the size of transistor miniaturization to about 50 nanometers (nm) or less rank.
Although the reduction of transistor size makes disposal ability strengthen, this also can make power consumption increase.Power is divided into static state or dynamic.Static power consumption can be determined by calculating the supply voltage that is provided to the transistor of IC and the product of the size of the direct current (DC) comprised by electric current and Leakage Current, and the dynamic power consumption comprising capacitive power consumption is by computational load electric capacity, square the determining with the product of switching frequency of supply voltage.
In addition, dynamic power consumption also comprises when transistor is in inverter circuit switching state, due to the power dissipation that the short circuit in IC produces.Such as, when comprising the inverter circuit switching state of p NMOS N-channel MOS N (PMOS) and n NMOS N-channel MOS N (NMOS) transistor, PMOS and nmos pass transistor be conduction current within the short duration all.When export be supply voltage only about half of time, result in a large amount of short circuit DC electric current flowing through PMOS and nmos pass transistor while this electric current.During short circuit DC electric current, switch-capacitor load is not contributed, and short-circuit power can be caused to dissipate.
Various inverter circuit has been designed to reduce short-circuit power consumption.Fig. 1 is the schematic circuit diagram of this traditional inverter circuit 100.Inverter circuit 100 comprises the first transistor 102 and transistor seconds 104, first electric capacity 106 and the second electric capacity 108, first diode 110 and the second diode 112 and the first resistor 114 and the second resistor 116.
The first terminal of the first resistor 114 and the second resistor 116 receives input voltage V
in.The first terminal of the first resistor 114 is connected to the first terminal of the first diode 110, and the second terminal of the first resistor 114 is connected to the second terminal of the first diode 110.The first terminal of the second resistor 116 is connected to the second terminal of the second diode 112, and the second terminal of the second resistor 116 is connected to the first terminal of the second diode 112.Second terminal of the first resistor 114 and the second resistor 116 is connected respectively to the first terminal of the first capacitor 106 and the second capacitor 108, and the second connecting terminals of the first capacitor 106 and the second capacitor 108 receives ground.
The source electrode of the first transistor 102 is connected to supply voltage V
dd, the grid of the first transistor 102 is connected to the first terminal of the first capacitor 106.The source ground of transistor seconds 104, the grid of transistor seconds 104 is connected to the first terminal of the second capacitor 108, and the drain electrode of transistor seconds 104 is connected to the drain electrode of the first transistor 102.
The input terminal that first diode 110 and the first resistor 114 are connected in parallel in inverter circuit 110 (provides V
innode) and the grid of the first transistor 102 between, and the second diode 112 and the second resistor 116 are connected in parallel between the input terminal of inverter circuit 110 and the grid of transistor seconds 104.First resistor 114 and the second resistor 116 have high resistance.Therefore, when in the first diode 110 and the second diode 112, any one is reverse biased, the equivalent resistance of the first resistor 114 and the second resistor 116 reduces.And then, when diode reverse biased, the input terminal of inverter circuit 100 and and the grid of the first transistor 102 and transistor seconds 104 between the conductance of conduction path increase.But when in the first diode 110 and the second diode 112 during any one forward bias, low resistance and the high conductance of the conduction path between the input terminal and the grid of the first transistor 102 and transistor seconds 104 of inverter circuit 100 keep interference-free.Higher equivalent resistance when any one is reverse biased in the first diode 110 and the second diode 112 slow down the charging and discharging of the grid of the first transistor 102 and transistor seconds 104, this reduces short circuit current and short-circuit power dissipation.
Although inverter circuit 100 reduces short circuit current and power dissipation, the value flowing through the dynamic current of inverter circuit 100 is very high, and the entirety which results in Dynamic power dissipation increases.In addition, the slowing down of charging and discharging of the grid of the first transistor 102 and transistor seconds 104 causes switch speed slack-off, which increases the delay of transistor and makes performance degradation.In addition, additional resistor and diode (namely the first resistor 114 and the second resistor 116, and the first diode 110 and the second diode 112) add area on sheet, which increase the holistic cost of IC.
Therefore, it is favourable for having a kind of like this inverter circuit, and described inverter circuit has low short-circuit power consumption and switches fast, little area occupied, and overcomes the above-mentioned limitation of traditional inverter circuit.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, the following detailed description to the preferred embodiments of the present invention will be understood better.The present invention be adopt citing mode be described, be not limited to accompanying drawing, Reference numeral representation class identical in accompanying drawing with element.
Fig. 1 is the schematic circuit of traditional inverter circuit; And
Fig. 2 is the schematic circuit of the inverter circuit according to the embodiment of the present invention.
Embodiment
Be intended to as the description to current the preferred embodiments of the present invention to the detailed description of accompanying drawing, do not wish to represent the unique forms that the present invention can implement.It being understood that function that is identical or that be equal to can be realized by different embodiment, within these embodiments wish to be comprised in the spirit and scope of the invention.
In an embodiment of the present invention, a kind of inverter circuit is provided.This inverter circuit comprises: the first transistor, has the source terminal for receiving supply voltage, and is shorted to the gate terminal on ground; Transistor seconds, has the source terminal for receiving supply voltage, and is connected to the drain terminal of drain terminal of the first transistor; First inverter, is connected to the drain terminal of the first transistor and transistor seconds, for receiving input signal, and at lead-out terminal place generating output signal; Third transistor, has the drain terminal being connected to the first inverter, is shorted to the source terminal on ground, and for receiving the gate terminal of supply voltage; 4th transistor, has the drain terminal of the drain terminal being connected to third transistor, and is shorted to the source terminal on ground; And second inverter, there is the lead-out terminal that is connected to the first inverter and input terminal for receiving output signal, and be connected to the lead-out terminal of gate terminal of transistor seconds and the 4th transistor.
In another embodiment of the present invention, a kind of inverter circuit is provided.This inverter circuit comprises: the first transistor, has the source terminal for receiving supply voltage, and is shorted to the gate terminal on ground; Transistor seconds, has the source terminal for receiving supply voltage, and is connected to the drain terminal of drain terminal of the first transistor; And first inverter.First inverter comprises: third transistor, has the source terminal of the drain terminal being connected to the first transistor and transistor seconds, for receiving the gate terminal of input signal; And the 4th transistor, there is the drain terminal of the drain terminal being connected to third transistor, and be connected to the gate terminal of third transistor and the gate terminal for receiving input signal.At the drain terminal place generating output signal of third transistor and the 4th transistor.Inverter circuit also comprises: the 5th transistor, has the drain terminal of the source terminal being connected to the 4th transistor, is shorted to the source terminal on ground, for receiving the gate terminal of supply voltage; 6th transistor, has the drain terminal of the drain terminal of source terminal and the 5th transistor being connected respectively to the 4th transistor, is shorted to the source terminal on ground; And second inverter.Second inverter comprises: the 7th transistor, has the source terminal for receiving supply voltage, is connected to the drain terminal of third transistor and the 4th transistor and the gate terminal for receiving output signal; And the 8th transistor, there is the drain terminal that is connected to the 7th transistor and be connected to the drain terminal of the gate terminal of transistor seconds and the 6th transistor, be connected to the gate terminal of the 7th transistor and the gate terminal for receiving output signal, and be shorted to the source terminal on ground.
Various embodiment of the present invention provides the inverter circuit with low power consumption.This inverter circuit is included in the first transistor and the transistor seconds that its gate terminal receives input signal.By its source terminal, the first transistor and transistor seconds are connected to third transistor and the 4th transistor.Third transistor and the 4th transistor keep continuous conducting, and are connected with the 5th transistor and the 6th coupled in parallel respectively, and the 5th transistor and the 6th transistor have low threshold voltage (SVT), therefore have low resistance.Third transistor and the 4th transistor have high threshold voltage (HVT), therefore have high resistance.When input signal is in stable state, when being namely in logical zero or logical one, based on being the first transistor or transistor seconds conducting, third transistor or the 4th transistor are switched on.Such as, when the first transistor conducting, the 5th transistor (being connected in parallel with third transistor) conducting.The conducting of the 5th transistor makes the high resistance of third transistor in parallel with the low resistance of the 5th transistor, thus low resistance conduction path is formed when input signal is in stable state, make electric current flow into the first transistor by this low resistance conduction path, thus reduce the dynamic power consumption of inverter circuit.
When input signal is from a kind of state-transition to another kind of state, one period of blink of the first transistor and transistor seconds conducting simultaneously, generate short circuit current thus.During this period of time, the 5th transistor and the 6th transistor are controlled such that to be limited to the flowing of the short circuit current in the high resistance path of the 4th transistor by comprising the first transistor.Comprise the first transistor and have to the high resistance path of the 4th transistor the high resistance be arranged in series, this reduces the size of short circuit current to a great extent, and decreases short-circuit power and dissipate.Because the 5th transistor and the 6th transistor are SVT transistors, so there is no the delay increasing inverter circuit.In addition, utilize the 7th transistor and the 8th transistor to control the 5th transistor and the 6th transistor, the W/L ratio that the 7th transistor and the 8th transistor have is about 0.12 times of the first transistor and transistor seconds.Therefore, the 7th transistor and the 8th transistor, for area on sheet and the overall power consumption for inverter circuit, affect very little.
With reference now to Fig. 2, show the schematic circuit of the inverter circuit 200 according to the embodiment of the present invention.Inverter circuit 200 comprises the first transistor to the 8th transistor 202-216.
The first transistor 202 has and is connected to supply voltage (V
dd) source terminal, and the gate terminal of ground connection.Transistor seconds 204 has and is connected to supply voltage V equally
ddsource terminal, and be connected to the drain terminal of drain terminal of the first transistor 202.Third transistor 206 has the source terminal of the drain terminal being connected to the first transistor 202 and transistor seconds 204, and receives the gate terminal of input signal INP.4th transistor 208 has the drain terminal of the drain terminal being connected to third transistor 206, and is connected to the gate terminal of third transistor 106 and the gate terminal for receiving input signal INP.At drain terminal place generating output signal (OUT) of third transistor 206 and the 4th transistor 208.
5th transistor 210 has the drain terminal of the source terminal being connected to the 4th transistor 208, is connected to supply voltage V
ddgate terminal, and the source terminal of ground connection.6th transistor 212 has the drain terminal of the source terminal being connected to the 4th transistor 208, is connected to the gate terminal of the gate terminal of transistor seconds 204, and the source terminal of ground connection.
7th transistor 214 has and is connected to supply voltage V
ddsource terminal, and be connected to third transistor 206 and the 4th transistor 208 drain terminal and for receive output signal OUT gate terminal.8th transistor 216 has the drain terminal of the drain terminal being connected to the 7th transistor 214, and is connected to the gate terminal of the 7th transistor 214 and the gate terminal for receiving output signal OUT.The drain terminal of the 7th transistor 214 and the 8th transistor 216 is also connected to the gate terminal of transistor seconds 204 and the 6th transistor 212.
In an embodiment of the present invention, the first transistor 202, transistor seconds 204, third transistor 206 and the 7th transistor 214 are p NMOS N-channel MOS N (PMOS) transistors, and the 4th transistor 208, the 5th transistor 210, the 6th transistor 212 and the 8th transistor 216 are n NMOS N-channel MOS N (NMOS) transistors.In a preferred embodiment of the invention, the first transistor 202, the 5th transistor 210, the 7th transistor 214 and the 8th transistor 216 are high threshold voltage transistors (HVT), and transistor seconds 204, third transistor 206, the 4th transistor 208 and the 6th transistor 212 are low threshold voltage transistor (SVT).And, in a preferred embodiment of the invention, the W/L ratio that the first transistor 202, transistor seconds 204, the 5th transistor 210 and the 6th transistor 212 have is about 0.5 times of third transistor 206 and the 4th transistor 208, and the W/L ratio that the 7th transistor and the 8th transistor have is about 0.12 times of third transistor 206 and the 4th transistor 208.
In the example of the work of inverter circuit 200, input signal INP is in logical one, and output signal OUT is in logical zero.As a result, third transistor 206 is ended, the 4th transistor 208 conducting.Grid due to the first transistor 202 is shorted to ground, and the grid of the 5th transistor 210 is connected to supply voltage V
dd, therefore the first transistor 202 and the 5th transistor 210 are conducting.In addition, because output signal OUT is in logical zero, therefore the 7th transistor 214 conducting, the 8th transistor 216 ends.The voltage at transistor seconds 204 and the 6th transistor 212 grid place drawn high by 7th transistor 214 of conducting, and this makes transistor seconds 204 end and the 6th transistor 212 conducting.The high resistance of the 5th transistor 210 of conducting is parallel to the low resistance of the 6th transistor 212 by the conducting of the 6th transistor 212, this reduces the equivalent resistance of the current conductive path formed to ground from the source electrode of the 4th transistor 208 (conducting).This reduction of the resistance of current conductive path reduces the dynamic power consumption of the 4th transistor 208.
When input signal INP starts to change logical zero into from logical one, third transistor 206 becomes conducting, and the 4th transistor 208 is conducting.Within blink, namely when input signal INP changes, third transistor 206 and the 4th transistor 208 all conduction currents.
In addition, the transformation of input signal INP causes the transformation of output signal OUT from logical zero to logical one.As a result, the 7th transistor 214 becomes cut-off and the 8th transistor becomes conducting, and then causes the grid place voltage of transistor seconds 204 and the 6th transistor 212 to be dragged down.This causes that transistor seconds 204 becomes conducting and the 6th transistor 212 becomes cut-off.Therefore, when input signal INP is converted to logical zero from logical one, transistor seconds 204 and the 6th transistor 212 also experienced by transformation.As a result, define from supply voltage V
ddto the high-resistance conduction path on ground, comprise and there is high-resistance the first transistor 202 and the 5th transistor 210, and there is low-resistance third transistor 206 and the 4th transistor 208.The high-resistance conduction path formed between the tour of input signal INP causes the short circuit current that produces in this stage very low, dissipates to make reducing short-circuit power compared with inverter 100.
Although illustrate and described various embodiment of the present invention, be noted that the present invention is not limited only to these embodiments.When not departing from the spirit and scope of the invention as described in claims, a large amount of amendments, change, modification, replacement and equivalent invention are apparent to those skilled in the art.
Claims (12)
1. an inverter circuit, comprising:
The first transistor, has the source terminal for receiving supply voltage, and is shorted to the gate terminal on ground;
Transistor seconds, has the source terminal for receiving supply voltage, and is connected to the drain terminal of drain terminal of the first transistor;
First inverter, is connected to the drain terminal of the first transistor and transistor seconds, for receiving input signal, and at lead-out terminal place generating output signal;
Third transistor, has the drain terminal being connected to the first inverter, is shorted to the source terminal on ground, and for receiving the gate terminal of supply voltage;
4th transistor, has the drain terminal of the drain terminal being connected to third transistor, and is shorted to the source terminal on ground; And
Second inverter, has the lead-out terminal that is connected to the first inverter and input terminal for receiving output signal, and is connected to the lead-out terminal of gate terminal of transistor seconds and the 4th transistor.
2. inverter circuit as claimed in claim 1, wherein said first inverter comprises:
5th transistor, has the source terminal of the drain terminal being connected to the first transistor and transistor seconds, and for receiving the gate terminal of input signal; And
6th transistor, has: the drain terminal being connected to the drain terminal of the 5th transistor; Be connected to the gate terminal of the 5th transistor and the gate terminal for receiving input signal, wherein at the drain terminal place generating output signal of the 5th transistor and the 6th transistor; And be connected to the source terminal of drain terminal of third transistor and the 4th transistor.
3. inverter circuit as claimed in claim 2, wherein said second inverter comprises:
7th transistor, has the source terminal for receiving supply voltage, and is connected to the drain terminal of the 5th transistor and the 6th transistor and the gate terminal for receiving output signal; And
8th transistor, there is the drain terminal that is connected to the 7th transistor and be connected to the drain terminal of the gate terminal of transistor seconds and the 4th transistor, be connected to the gate terminal of the 7th transistor and the gate terminal for receiving output signal, and be shorted to the source terminal on ground.
4. inverter circuit as claimed in claim 3, wherein third transistor, the 4th transistor, the 6th transistor and the 8th transistor are n NMOS N-channel MOS N (NMOS) transistors.
5. inverter circuit as claimed in claim 3, wherein the first transistor, transistor seconds, the 5th transistor and the 7th transistor are p NMOS N-channel MOS N (PMOS) transistors.
6. inverter circuit as claimed in claim 3, wherein the first transistor, third transistor, the 7th transistor and the 8th transistor are high threshold voltage transistors.
7. inverter circuit as claimed in claim 3, wherein transistor seconds, the 4th transistor, the 5th transistor and the 6th transistor are Low threshold transistors.
8. an inverter circuit, comprising:
The first transistor, has the source terminal for receiving supply voltage, and is shorted to the gate terminal on ground;
Transistor seconds, has the source terminal for receiving supply voltage, and is connected to the drain terminal of drain terminal of the first transistor;
First inverter, comprising:
Third transistor, has the source terminal of the drain terminal being connected to the first transistor and transistor seconds, and for receiving the gate terminal of input signal; And
4th transistor, there is the drain terminal of the drain terminal being connected to third transistor, and be connected to the gate terminal of third transistor and the gate terminal for receiving input signal, wherein at the drain terminal place generating output signal of third transistor and the 4th transistor;
5th transistor, has the drain terminal of the source terminal being connected to the 4th transistor, is shorted to the source terminal on ground, and for receiving the gate terminal of supply voltage;
6th transistor, has the drain terminal of the drain terminal of source terminal and the 5th transistor being connected respectively to the 4th transistor, and is shorted to the source terminal on ground; And
Second inverter, comprising:
7th transistor, has the source terminal for receiving supply voltage, is connected to the drain terminal of third transistor and the 4th transistor and the gate terminal for receiving output signal; And
8th transistor, there is the drain terminal that is connected to the 7th transistor and be connected to the drain terminal of the gate terminal of transistor seconds and the 6th transistor, be connected to the gate terminal of the 7th transistor and the gate terminal for receiving output signal, and be shorted to the source terminal on ground.
9. inverter circuit as claimed in claim 8, wherein the 4th transistor, the 5th transistor, the 6th transistor and the 8th transistor are n NMOS N-channel MOS N (NMOS) transistors.
10. inverter circuit as claimed in claim 8, wherein the first transistor, transistor seconds, third transistor and the 7th transistor are p NMOS N-channel MOS N (PMOS) transistors.
11. inverter circuits as claimed in claim 8, wherein the first transistor, the 5th transistor, the 7th transistor and the 8th transistor are high threshold voltage transistors.
12. inverter circuits as claimed in claim 8, wherein transistor seconds, third transistor, the 4th transistor and the 6th transistor are Low threshold transistors.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310666639.9A CN104579306A (en) | 2013-10-10 | 2013-10-10 | Low-power phase inverter circuit |
| US14/463,673 US9166585B2 (en) | 2013-10-10 | 2014-08-20 | Low power inverter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310666639.9A CN104579306A (en) | 2013-10-10 | 2013-10-10 | Low-power phase inverter circuit |
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| Publication Number | Publication Date |
|---|---|
| CN104579306A true CN104579306A (en) | 2015-04-29 |
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ID=52809167
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310666639.9A Pending CN104579306A (en) | 2013-10-10 | 2013-10-10 | Low-power phase inverter circuit |
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| Country | Link |
|---|---|
| US (1) | US9166585B2 (en) |
| CN (1) | CN104579306A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330174A (en) * | 2016-08-16 | 2017-01-11 | 深圳市华星光电技术有限公司 | CMOS (Complementary Metal Oxide Semiconductor) phase inverter, and electronic device applying the CMOS phase inverter |
| CN107453749A (en) * | 2016-05-31 | 2017-12-08 | 展讯通信（上海）有限公司 | A kind of domain of logic gates |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9935636B1 (en) * | 2017-03-10 | 2018-04-03 | Plsense Ltd. | CMOS input buffer with low supply current and voltage down shifting |
| TWI654842B (en) * | 2017-10-20 | 2019-03-21 | 立積電子股份有限公司 | Inverter |
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| US5760620A (en) * | 1996-04-22 | 1998-06-02 | Quantum Effect Design, Inc. | CMOS limited-voltage-swing clock driver for reduced power driving high-frequency clocks |
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| CN107453749A (en) * | 2016-05-31 | 2017-12-08 | 展讯通信（上海）有限公司 | A kind of domain of logic gates |
| CN107453749B (en) * | 2016-05-31 | 2020-09-01 | 展讯通信（上海）有限公司 | Layout of logic gate circuit |
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| CN106330174B (en) * | 2016-08-16 | 2019-02-12 | 深圳市华星光电技术有限公司 | The electronic device of CMOS inverter and the application CMOS inverter |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150102839A1 (en) | 2015-04-16 |
| US9166585B2 (en) | 2015-10-20 |
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