CN106257654B - 半导体封装件及其制造方法 - Google Patents
半导体封装件及其制造方法 Download PDFInfo
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- CN106257654B CN106257654B CN201610423538.2A CN201610423538A CN106257654B CN 106257654 B CN106257654 B CN 106257654B CN 201610423538 A CN201610423538 A CN 201610423538A CN 106257654 B CN106257654 B CN 106257654B
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- 238000000034 method Methods 0.000 claims description 18
- 239000011810 insulating material Substances 0.000 claims description 14
- 239000000919 ceramic Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
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- 229910052802 copper Inorganic materials 0.000 claims description 9
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- 230000001681 protective effect Effects 0.000 description 1
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Abstract
公开了一种半导体封装件及其制造方法。所述半导体封装件包括:第一基板,包括第一型腔;腔模,被构造为插入到所述第一型腔中并且包括第二型腔;电子组件,插入到所述第二型腔中;第二基板,形成在所述第一基板的表面、所述腔模的表面和所述电子组件的表面上。
Description
本申请要求于2015年6月18日在韩国知识产权局提交的第10-2015-0086885号韩国专利申请的权益,所述韩国专利申请的全部公开内容出于所有目的通过引用包含于此。
技术领域
以下描述涉及一种半导体封装件和制造该半导体封装件的方法。
背景技术
半导体技术的快速进步已在半导体封装领域显示出积极发展,诸如,以系统级封装(SIP)、芯片级封装(CSP)和倒装芯片封装(FCP)为例,其中,诸如半导体器件的电子组件被预安装在印刷电路板中并被构造为封装件。
随着电子组件变得越来越小以及更加集成化,输入和输出的数量已增加,因此,安装有电子组件的封装件板的焊盘的数量也增加。因此,封装件板需要具有精细的间距,从而增加了封装件板的制造成本。为了应对封装件板的精细的间距,在电子组件与封装件板之间通常形成有插入件。
本说明书的现有技术已在专利号为US 6,861,288的美国专利中公开。本公开引用的包括公开文件、专利申请和专利的全部文件可在每个被引用的文件被分开且特定地包含或被全部包含时按照与之相同的方式通过引用全部包含于此。
发明内容
提供本发明内容,以按照简化的形式来介绍选择的构思,所述选择的构思将在以下的具体实施方式中被进一步描述。本发明内容并非意在确定要求保护的主题的关键特征或必要特征,也并非意在用于帮助确定要求保护的主题的范围。
在一个总的方面中,提供一种可省略其中的再分配层或插入件的封装件板和制造封装件板的方法。
在另一总的方面中,提供一种具有高整合性和高密度的电路层的封装件板和制造封装件件板的方法。
在另一总的方面中,提供一种半导体封装件,所述半导体封装件包括:第一基板,包括第一型腔;腔模,被构造为插入到所述第一型腔中并且包括第二型腔;电子组件,插入到所述第二型腔中;第二基板,形成在所述第一基板的表面、所述腔模的表面和所述电子组件的表面上。
可在所述第二基板上方设置多个电子组件。
所述腔模可包括被构造为容纳所述多个电子组件的多个第二型腔。
所述腔模可由绝缘材料制成。
所述腔模可由半固化片制成。
所述腔模可由半固化片、金属或陶瓷中的至少一种制成。
所述腔模的另一表面与所述电子组件的另一表面可置于同一平面上。
所述第二基板可包括绝缘层和电路层,且所述绝缘层可由光敏绝缘材料制成。
所述第一基板可包括绝缘层和电路层。
所述腔模可被构造为防止所述绝缘层流到所述电子组件中。
腔模的使所述电子组件插入的表面可以是平坦的。
在另一总的方面中,提供一种制造半导体封装件的方法,所述方法包括:制备包括形成了第一型腔的第一基板,制备包括第二型腔的腔模,在所述第二型腔中插入电子组件,在所述第一型腔中插入所述腔模,在所述第一基板的表面、所述腔模的表面和所述电子组件的表面上形成第二基板。
所述腔模可由绝缘材料制成。
所述腔模可由半固化片制成。
所述腔模可由金属或陶瓷制成。
所述腔模可包括形成在其上的多个第二型腔。
所述电子组件的插入可包括在所述多个第二型腔中插入多个电子组件。
所述腔模的另一表面和所述电子组件的另一表面可置于同一平面上。
所述第二基板可包括绝缘层和电路层,且所述绝缘层可由光敏绝缘材料制成。
其他特征和方面将通过以下的具体实施方式、附图和权利要求而明显。
附图说明
图1是示出半导体封装件的示例的示图。
图2是示出半导体封装件的示例的示图。
图3是示出形成封装件板的方法的示例的示图。
图4至图12是示出形成半导体封装件的方法的示例的示图。
在整个附图和具体实施方式中,相同的标号指示相同的元件。附图可不按照比例绘制,为了清楚、说明和方便起见,可夸大附图中元件的相对尺寸、比例和描绘。
具体实施方式
提供以下详细描述来帮助读者获得对这里描述的方法、设备和/或系统的全面理解。然而,这里描述的方法、设备和/或系统的各种变化、修改和等同物对于本领域普通技术人员将是明显的。这里描述的操作的顺序仅是示例,并不局限于在此阐述的操作顺序,而是除了必须以特定顺序发生的操作外,可如本领域普通技术人员将理解的那样改变。此外,为了更加清楚和简洁,可省去本领域普通技术人员所公知的功能和结构的描述。
这里描述的特征可按照不同的形式实现,并且不应被解释为局限于这里描述的示例。更确切地说,已提供这里描述的示例使得本公开将是彻底的和完整的,并将本公开的全部范围传达给本领域的普通技术人员。
相同或相对应的元件不管图号都将被赋予相同的标号,并且将不重复对相同或相对应的元件的多余描述。贯穿本公开的说明书,当描述一种特定的相关传统技术被确定为避开了本公开的要点时,将省略相关的详细描述。诸如“第一”和“第二”的术语可被用于描述各种元件,但以上元件不应受限于以上术语。以上术语只用于使一个元件与其他元件区分开。在附图中,一些元件可被夸大、省略或简要示出,并且元件的尺寸不一定反映这些元件的实际尺寸。
图1示出了根据第一实施例的半导体封装件的示例。
参照图1,半导体封装件100包括第一基板110、腔模120、电子组件130和第二基板140。
第一基板110包括第一绝缘层111和第一电路层112中的至少一层。
第一绝缘层111由通常用作层间绝缘材料的聚合物树脂的复合物制成。例如,第一绝缘层111由诸如(例如)半固化片、ABF(ajinomoto build-up film)、FR-4(flameretardant 4)或BT(bismaleimide triazine)的环氧树脂制成。
第一电路层112由导电材料制成。例如,第一电路层112由铜制成。然而,用于第一电路层112的材料不仅限于铜,第一电路层112可以由电路板领域中已知的任意的形成电路的导电材料制成。
第一型腔115形成在第一基板110中。第一型腔115形成在第一基板110的一个表面上。在此示例中,第一基板110的形成有第一型腔115的表面与第二基板140接触或电连接。
第一型腔115的尺寸和形状使得当腔模120插入在第一型腔115中时适于将腔模120固定到第一基板110。
腔模120插入到第一基板110的第一型腔115中并固定到第一基板110的第一型腔115。第二型腔125形成在腔模120中。第二型腔125形成在腔模120的一个表面上。在此示例中,腔模120的形成有第二型腔125的表面与第二基板140接触。
第二型腔125的尺寸和形状使得当电子组件130插入在第二型腔125中时适于将电子组件130固定到腔模120。
腔模120由绝缘材料制成。例如,腔模120由半固化片制成。在另一示例中,腔模120由金属或陶瓷制成。通过使腔模120由金属或陶瓷制成,电子组件130产生的热可向外传递。因此,半导体封装件100的散热性能可通过使用金属或陶瓷形成腔模120而得到改进。
腔模120可在腔模120插入第一基板110中时或在形成第二基板140时保护电子组件130。腔模120用作保护壁使得第一基板110的第一绝缘层111不流向电子组件130。由于腔模120阻止第一绝缘层111流动,因此可形成精密地设计的半导体封装件100。
电子组件130插入在腔模120的第二型腔125中。当电子组件130布置在第二基板140上方时,电子组件130保持插入在腔模120中。此外,可使电子组件130与第一基板110电连接。
在此示例中,电子组件130可以是能够安装在半导体封装件100中的任何类型的组件。
在此示例中,腔模120和电子组件130可被布置为这样的方式:腔模120的一个表面与电子组件130的一个表面处于同一平面上。
由于腔模120插入且固定在第一基板110的第一型腔115中,因此可防止电子组件130倾斜。因此,电子组件130可附着在其预定的位置。因此,第一基板110、电子组件130与第二基板140之间可具有高整合性。
在示例中,第二基板140包括第二绝缘层141和第二电路层142中的至少一层。第二绝缘层141由电路板领域中常用的层间绝缘材料中的光敏材料制成。
第二电路层142由导电材料制成。例如,第二电路层142由铜制成。然而,用于第二电路层142的材料不仅限于铜,第二电路层142可由电路板领域中已知的任意的形成电路的导电材料制成。
在示例中,由于第二基板140具有形成在光敏绝缘材料上的电路层,因此可在第二电路层142中实现精细的间距(fine pitch)。因此,可以省略额外的再分配层和插入件。
图2示出了半导体封装件的另一示例。参照图2,半导体封装件200包括第一基板110、腔模220、电子组件130和第二基板140。
图2中示出的第一基板110和第二基板140与第一基板110(如图1所示)和第二基板140(如图1所示)相同。上面对图1的描述也适用于图2,并通过引述包含于此。因此,可不必在此重复以上描述。
图2中示出的腔模220和电子组件130与(腔模120(如图1所示)和电子组件130(如图1所示)相同。上面对图1的描述也适用于图2,并通过引述包含于此。因此,可不必在此重复以上描述。但是,将在此描述图2的腔模220和电子组件130与图1的腔模120和电子组件130之间的一些差异。
如图2所示,在腔模220中形成多个第二型腔225。在此示例中,多个电子组件130设置在该多个第二型腔225中。多个第二型腔225均形成为具有足以使电子组件130插入并固定到第二型腔225的尺寸和形状。
如图2所示,多个电子组件130分别插入并固定到相应的第二型腔225中。因此,多个电子组件130的一个表面与腔模220的一个表面可在同一平面上对齐。可防止多个电子组件130倾斜。因此,第一基板110、多个电子组件130与第二基板140之间可具有高整合性。
多个电子组件130插入其中的腔模220插入在第一基板110的第一型腔115中。第二基板140置于第一基板110、腔模220和多个电子组件130的下方。
图3是示出形成封装件板的方法的示例的示图。图4至图12示出了形成半导体封装件的方法的示例。将参照图4至图12描述图3中示出的方法。图3中的操作可按照示出的顺序和方式执行,但在不脱离描述的示例性示例的精神和范围的情况下可改变一些操作的顺序或者可省略所述操作中的一些操作。图3中示出的操作中的多个操作可并行或同步地执行。上面对图1、图2的描述也适用于图3,并通过引述包含于此。因此,可不必在此重复以上描述。
在S110中,参照图4,制备在其中形成有第一型腔115的第一基板110。第一基板110包括第一绝缘层111和第一电路层112中的至少一层。
如上所述,第一绝缘层111由通常用作层间绝缘材料的聚合物树脂的复合物制成。例如,第一绝缘层111由例如半固化片、ABF(ajinomoto build-up film)、FR-4(flameretardant 4)、BT(bismaleimide triazine)的环氧树脂制成。
第一电路层112由导电材料制成。例如,第一电路层112由铜制成。然而,用于第一电路层112的材料不仅限于铜,第一电路层112可由电路板领域中已知的任意的形成电路的导电材料制成。
第一型腔115形成在第一基板110中。第一型腔115形成在第一基板110的一个表面上。在此示例中,第一基板110的形成有第一型腔115的表面与第二基板140接触或电连接。
第一型腔115具有当腔模120插入在第一型腔115中时适于将腔模120固定到第一基板110的尺寸和形状。
在此示例中,可采用在电路板领域中已知的形成绝缘层、电路层和型腔的任意方法形成第一基板110。
在S120中,参照图5和图6,制备其中形成有第二型腔125的腔模120。
图5示出了根据图1中公开的示例的腔模120的示例,图6示出了根据图2中公开的示例的腔模120的示例。
如图5和图6中所示的腔模120由绝缘材料制成。例如,腔模120由半固化片120制成。可选地,腔模120由金属或陶瓷制成。通过使腔模120由金属或陶瓷制成,之后被安装的电子组件(未示出)产生的热量可被向外传递。因此,半导体封装件的散热性能可通过用金属或陶瓷形成腔模120而得到改进。
在示例中,如图5所示,腔模120可具有第二型腔125。在另一示例中,如图6所示,腔模220可具有第二型腔225。第二型腔125和225可分别形成在腔模120和220的一个表面上。
参照图5,腔模120具有形成在其中的一个第二型腔125。在此示例中,第二型腔125形成为具有足以使一个电子组件(未示出)插入且固定到第二型腔125的尺寸和形状。
参照图6,根据第二实施例的腔模220具有形成在其中的多个第二型腔225。
在S130中,参照图7和图8,在腔模120的第二型腔125和腔模220的第二型腔225中分别插入电子组件130。
参照图7,在腔模120中插入电子组件130。如图7所示,在腔模120的第二型腔125中插入单个电子组件130。由于第二型腔125具有与电子组件130的尺寸和形状相同的尺寸和形状,因此电子组件130被固定在腔模120中。
如图7中所示,当电子组件130插入在腔模120中时,腔模120的一个表面与电子组件130的一个表面置于同一平面上。因此,腔模120的插入了电子组件130的一个表面是平坦的。
参照图8,在腔模220中插入多个电子组件130。如图8所示,3个电子组件130插入到腔模220的三个第二型腔225中。在此示例中,由于三个第二型腔225均具有与插入其中的电子组件130的尺寸和形状相同的尺寸和形状,因此所述3个电子组件130被固定在腔模220中。
如图8所示,当多个电子组件130插入在腔模220中时,腔模220的一个表面与多个电子组件130的一个表面置于同一平面上。因此,腔模120的插入了多个电子组件130的一个表面是平坦的。
由于电子组件130插入并固定在腔模120和220中,因此防止电子组件130倾斜。因此,当布置电子组件130时,防止电子组件130滑出或脱离。
在S140中,参照图9和图10,将其中插入有电子组件130的腔模120、220插入到第一基板110的第一型腔115中。
如图9和图10所示,腔模120插入在第一基板110的第一型腔115中。在此示例中,由于第一型腔115具有与腔模120的尺寸和形状相同的尺寸和形状,因此腔模120在插入第一基板110中时被固定。
如图9和图10所示,当腔模120和220插入在第一基板110中时,第一基板110的一个表面和腔模110和220的一个表面置于同一平面上。因此,在其中嵌有腔模120和220的第一基板110的一个表面是平坦的。
如图9和图10所示,当腔模110和220插入在第一基板110中时,腔模120和220防止第一绝缘层111流向电子组件130。由于腔模110和220防止了第一绝缘层111流动,因此可以按照设计精细地形成和设置第一基板110、腔模120和220、电子组件130和将在稍后形成第二基板(未示出)。
在S150中,参照图11和图12,在使腔模120和220插入在其中的第一基板110上形成第二基板140。
根据示例,第二基板140形成在第一基板110的表面、腔模120和220的表面以及电子组件130的表面上。第二基板140包括第二绝缘层141和第二电路层142中的至少一层。
第二绝缘层141由电路板领域中常用的层间绝缘材料中的光敏材料制成。
第二电路层142由诸如以铜为例的导电材料制成。然而,第二电路层142的材料不仅限于铜,第二电路层142可由电路板领域中已知的任意的形成电路的导电材料制成。
根据示例,第一基板110的一个表面、腔模120和220的一个表面和电子组件130的一个表面置于同一平面上。因此,第一基板110、腔模120和220以及电子组件130具有一个共同的平坦的表面。第二基板140形成在这个共同的平坦的表面上。在保持电子组件130固定到腔模120和220的状态下形成第二基板140。因此,第二基板140与电子组件130之间以及第二基板140与第一基板110之间可具有高整合性。由于第二基板140包括由光敏材料制成的第二绝缘层141,因此可以实现具有精细的间距的第二基板140。随着实现高整合性和精细的间距,第二基板140可用作再分配层或者插入件。换言之,半导体封装件100和200可省略再分配层或插入件。此外,由于可省略再分配层或插入件,因此可以减小半导体封装件100和200的厚度。
虽然本公开包括具体的示例,但对于本领域的普通技术人员将显而易见的是,在不脱离权利要求和其等同物的精神和范围的情况下,可对这些示例做出形式和细节上的各种改变。这里所描述的示例仅仅将被理解为描述性的含义,并非用于限制的目的。每个示例中的方面或特征的描述将被理解为适用于其他示例中的相似的方面和特征。如果以不同的顺序执行所描述的技术,和/或如果以不同的方式组合所描述的系统、架构、装置或者电路中的组件,和/或由其他元件或者其等同物替换或补充所述元件,则可获得合适的结果。因此,本公开的范围不由具体实施方式所限定,而是由权利要求和其等同物所限定,并且在权利要求和其等同物的范围内的所有变型将解释为包含在本公开内。
Claims (21)
1.一种半导体封装件,包括:
第一基板,包括第一型腔;
腔模,被构造为插入到所述第一型腔中并且包括第二型腔;
电子组件,插入在所述第二型腔中;
第二基板,形成在所述第一基板的表面、所述腔模的表面和所述电子组件的表面上,
其中,所述电子组件与所述第二型腔的底表面直接接触,
其中,所述腔模利用半固化片、金属以及陶瓷中的至少一种制成。
2.根据权利要求1所述的半导体封装件,其中,多个电子组件设置在所述第二基板之上。
3.根据权利要求2所述的半导体封装件,其中,所述腔模包括被构造为容纳所述多个电子组件的多个第二型腔。
4.根据权利要求1所述的半导体封装件,其中,所述腔模具有U型截面。
5.根据权利要求1所述的半导体封装件,其中,所述第一基板包括绝缘层和电路层,所述绝缘层利用环氧树脂制成。
6.根据权利要求5所述的半导体封装件,其中,所述电路层利用铜制成。
7.根据权利要求1所述的半导体封装件,其中,所述腔模的所述表面与所述电子组件的所述表面置于同一平面上。
8.根据权利要求1所述的半导体封装件,其中,所述腔模的所述表面、所述电子组件的所述表面与所述第一基板的所述表面置于同一平面上。
9.根据权利要求1所述的半导体封装件,其中,所述第二基板包括绝缘层和电路层,且所述绝缘层由光敏绝缘材料制成。
10.根据权利要求1所述的半导体封装件,其中,所述第一基板包括绝缘层和电路层。
11.根据权利要求10所述的半导体封装件,其中,所述腔模被构造为防止所述绝缘层流到所述电子组件中。
12.根据权利要求1所述的半导体封装件,其中,腔模的使所述电子组件插入的表面是平坦的。
13.一种制造半导体封装件的方法,包括:
制备包括形成了第一型腔的第一基板;
制备包括第二型腔的腔模;
在所述第二型腔中插入电子组件;
在所述第一型腔中插入包括所述电子组件的腔模;
在所述第一基板的表面、所述腔模的表面和所述电子组件的表面上形成第二基板。
14.根据权利要求13所述的方法,其中,所述腔模由绝缘材料制成。
15.根据权利要求14所述的方法,其中,所述腔模由半固化片制成。
16.根据权利要求13所述的方法,其中,所述腔模由金属或陶瓷制成。
17.根据权利要求13所述的方法,其中,所述腔模包括形成在所述腔模上的多个第二型腔。
18.根据权利要求17所述的方法,其中,所述电子组件的插入包括在所述多个第二型腔中插入多个电子组件。
19.根据权利要求14所述的方法,其中,所述腔模的所述表面与所述电子组件的所述表面置于同一平面上。
20.根据权利要求13所述的方法,其中,所述腔模的所述表面、所述电子组件的所述表面与所述第一基板的所述表面置于同一平面上。
21.根据权利要求14所述的方法,其中,所述第二基板包括绝缘层和电路层,且所述绝缘层由光敏绝缘材料制成。
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