CN106257642A - 在例如在soi衬底上尤其是fdsoi衬底上制造的集成电路的有源区上制造接触的方法以及对应的集成电路 - Google Patents

在例如在soi衬底上尤其是fdsoi衬底上制造的集成电路的有源区上制造接触的方法以及对应的集成电路 Download PDF

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CN106257642A
CN106257642A CN201510860310.5A CN201510860310A CN106257642A CN 106257642 A CN106257642 A CN 106257642A CN 201510860310 A CN201510860310 A CN 201510860310A CN 106257642 A CN106257642 A CN 106257642A
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insulating barrier
active area
cavity
dielectric layer
insulating
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CN106257642B (zh
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E·佩蒂特普瑞兹
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
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Abstract

本发明的各个实施例涉及：在例如在SOI衬底上(尤其是FDSOI衬底上)制造的集成电路的有源区上制造接触的方法；以及对应的集成电路。集成电路包括有源区，该有源区位于半导体衬底之上。空腔与有源区接界，并且在绝缘区中尽可能远地延伸到半导体区域的附近。提供绝缘多层，并且导电接触在该绝缘多层内延伸以存在于有源区上并且进入到空腔内。绝缘多层包括第一绝缘层，该第一绝缘层覆盖了在接触外部的有源区并且衬覆空腔的壁。附加绝缘层覆盖了第一绝缘层的衬覆空腔的壁的部分。接触到达在空腔中的附加绝缘层。绝缘区域位于由围绕接触的绝缘材料制成的附加绝缘层和第一绝缘层之上。

Description

在例如在SOI衬底上尤其是FDSOI衬底上 制造的集成电路的有源区上制造接触的方法 以及对应的集成电路
相关申请的交叉引用
本申请要求2015年6月18日提交的法国专利申请1555588号的优先权，其公开内容以引用的方式并入本文。
技术领域
本发明涉及集成电路，并且更加具体地，涉及在集成电路的有源区上，例如晶体管漏极或者源极区上，制造伸出到与这些有源区接界的绝缘区之上的接触。
背景技术
在其上制造有集成电路的衬底可以是绝缘体上硅(SOI)衬底，并且更加具体地，可以是全耗尽型绝缘体上硅(FDSOI)衬底，但该示例并非限制性的。
绝缘体上硅衬底包括半导体膜，该半导体膜例如由硅或者硅合金制成，例如硅锗合金，位于通常称为“BOX”(即，“埋入式氧化物”)的埋入式绝缘层之上，埋入式绝缘层自身则位于载体衬底例如半导体阱之上。
在FDSOI技术中，半导体膜是全耗尽的，即，其由本征半导体材料组成。其厚度一般大约为几纳米。而且，埋入式绝缘层自身的厚度一般是薄的，大约为十纳米。
考虑到半导体膜的小厚度，晶体管的源极和漏极包括相对于半导体膜凸起的区段，以便在这些区域与晶体管的沟道区域之间确保足够的电连接。
这种凸起的源极和漏极区域(RSD)通常通过外延来获得。
为了使得能够通过外延制造凸起的源极和漏极区，例如，使用脱氧工艺提前清洁硅的表面，这导致在相邻的绝缘区中形成空腔。
而且，在常见的集成工艺中，当希望在位于与多晶硅线相距小的精确控制的距离(例如，位于两条多晶硅线之间)的有源区上制造接触时，使用光刻掩膜限定出接触的几何形状会引起制造了伸出到所述绝缘空腔之上的接触。
此外，在这种情况下，接触的常规制造工艺引起空腔被穿透，从而导致在接触的金属端部与相邻的这部分载体衬底之间的短路。
避免该穿透的一种方式由以下步骤组成：使用两个光刻掩膜来限定出接触的几何形状，从而使得后者不从有源区突出。
然而，这种方法实施起来很昂贵。
发明内容
根据一种实施方法，提出了一种用于在集成电路的有源区上，例如晶体管的源极或者漏极区上，制造伸出到与该有源区接界的空腔上的接触的方法，使得能够在优选地仅仅使用单个光刻掩膜限定出接触的几何形状的同时，消除在接触的端部与相邻半导体区域之间(例如，SOI衬底的载体衬底的部分)形成短路的风险。
根据一个方面，提供了一种用于在集成电路的有源区上制造接触的方法，该有源区位于半导体衬底之上，该半导体衬底可以是，例如，包括由埋入式绝缘层(BOX)承载的半导体膜的SOI衬底，该埋入式绝缘层自身又由载体衬底承载。
根据本方面的方法包括：在所述有源区之上、和在与有源区接界并且在绝缘区中尽可能远地延伸到半导体区域的附近的空腔之中和之上，形成例如载体衬底的部分、绝缘多层。
该绝缘多层的形成包括：形成第一绝缘层，例如，蚀刻阻挡层，即，被本领域的技术人员通常称为的接触蚀刻阻挡层(CESL)的层，该第一绝缘层覆盖有源区并且衬覆空腔的壁；以及在第一绝缘层之上形成绝缘区域，该区域通常是被本领域的技术人员称为预金属电介质(PMD)的区域，例如包括顶上覆盖有TEOS(正硅酸乙酯)氧化物的二氧化硅。
该方法还包括如下操作：对绝缘多层的部分进行蚀刻，以便限定出开口到有源区上并且进入到空腔中的孔口，并且用导电填充材料例如铜、钨或者铝填充该孔口。
根据本方面的一个一般性特征，所述绝缘区域的形成包括：在已经形成第一绝缘层之后，形成附加绝缘层，该附加绝缘层配置为在所述蚀刻操作期间防止穿透衬覆空腔的壁并且位于接近半导体区域的第一绝缘层的区段。
根据一个变型，绝缘区域的形成包括：用覆盖第一绝缘层的衬覆空腔的壁的部分的第一绝缘材料填充空腔，例如，二氧化硅；形成覆盖第一绝缘层和第一绝缘材料的附加绝缘层；以及在附加绝缘层上形成由例如TEOS氧化物制成的第二绝缘层。
根据适用于该变型的一种实施方法，蚀刻操作包括对第二绝缘层进行第一蚀刻，该第一蚀刻停止在附加绝缘层上，然后第二蚀刻，该第二蚀刻配置为：一方面，对附加绝缘层和在底下的第一绝缘层蚀刻以便使有源区暴露出来，并且另一方面，对附加绝缘层和第一绝缘材料的位于空腔中的底下部分进行蚀刻，而不穿透第一绝缘层的所述区段。
由此，在空腔之上存在该附加绝缘层使得能够使第一蚀刻停止在该附加绝缘层上，从而保留用第一绝缘材料填充的空腔，并且因此可以在与空腔的底部相隔一定距离处停止第二蚀刻，从而可以不穿透第一绝缘层。
附加绝缘层的材料可以与第一绝缘层的材料相同，并且例如，可以包括氮化硅。
有利地选择附加绝缘层的厚度，从而使得该附加绝缘层足够厚以起到蚀刻阻挡层的作用，并且足够薄以不破坏蚀刻，使得能够打开附加绝缘层和第一层以便使有源区的顶部暴露出来。
本领域的技术人员能够调节该厚度，尤其取决于所使用的材料和蚀刻的类型。
因而，将包括在5nm与20nm之间的厚度考虑为可接受的厚度。
根据另一个变型，绝缘区域的形成包括：形成附加绝缘层，从而使得该附加绝缘层覆盖第一绝缘层的衬覆空腔的壁的部分，该附加绝缘层配置为可相对于第一绝缘层选择性蚀刻；用覆盖附加绝缘层的第一绝缘材料填充空腔，例如，二氧化硅；以及在第一绝缘材料上形成第二绝缘层，例如，TEOS型氧化物层。
由此，根据适用于该其他变型的一种实施方法，蚀刻操作包括：对第二绝缘层进行第一蚀刻，该第一蚀刻停止在第一绝缘层的位于有源区之上的部分上和在附加绝缘层上，然后第二选择性蚀刻，该第二选择性蚀刻配置为对第一绝缘层的位于有源区之上的部分进行蚀刻，以便使有源区暴露出来，而不对衬覆空腔的壁的附加绝缘层蚀刻。
通过非限制性示例的方式，第一绝缘层可以包括氮化硅，并且附加绝缘层可以包括高介电常数氧化物(高k氧化物)，典型具有高于或者等于15的介电常数k。
例如，该电介质可以选自由HfO2、ZrO2、Al2O3、AlN、TiN和TiO2形成的组。
根据另一方面，提供了一种集成电路，该集成电路包括：至少一个有源区，该至少一个有源区位于半导体衬底之上；空腔，该空腔与有源区接界并且在绝缘区中尽可能远地延伸到半导体区域的附近；绝缘多层和导电接触，该导电接触在出现在有源区上并且进入到空腔中的绝缘多层内。
根据该其他方面的一个一般性特征，绝缘多层包括：第一绝缘层，该第一绝缘层覆盖在所述接触外部的有源区，至少部分地衬覆空腔的壁，并且具有位于所述接触与所述半导体区域之间的区段；以及绝缘区域，绝缘区域在第一绝缘层的包括围绕所述接触的至少一种绝缘材料之上；以及附加绝缘层，该附加绝缘层位于为具有覆盖在接触外部的第一绝缘层的第一部分和位于接触外部的第二部分，在所述至少一种绝缘材料内，并且与至少部分地衬覆空腔的壁的第一绝缘层的部分相隔一定距离。
根据一个实施例，附加绝缘层的材料可以与第一绝缘层的材料相同，并且例如，可以包括氮化硅。
该附加绝缘层的厚度可以包括在5nm与20nm之间。
作为变型，提供了一种集成电路，该集成电路的绝缘多层包括：第一绝缘层，该第一绝缘层覆盖在所述接触外部的有源区并且衬覆空腔的壁；附加绝缘层，该附加绝缘层覆盖衬覆所述空腔的壁的第一绝缘层的部分，接触到达在所述空腔中的该附加绝缘层；以及绝缘区域，该绝缘区域在第一绝缘层的顶部和附加绝缘层之上，包括围绕所述接触的至少一种绝缘材料。
根据适用于该变型的一个实施例，第一绝缘层包括氮化硅，并且附加绝缘层包括高介电常数氧化物。
无论是什么变型，半导体衬底可以是SOI衬底，即，包括由载体衬底自身承载的埋入式绝缘层(BOX)承载的半导体膜的衬底。在这种情况下，所述埋入式绝缘层包括所述绝缘区的至少一部分，并且所述半导体区域可以是载体衬底的部分。
附图说明
在审查对本发明的完全非限制性的实施方法和实施例以及对应附图的详细说明时，本发明的其他优点和特征将变得显而易见，其中：
图1至图35示意性地图示了实施方法和实施例。
具体实施方式
图1示意性地图示了集成电路IC的一部分的顶视图，包括此处在有源区ZA，有源区ZA两侧有两条多晶硅线LP。
有源区ZA可以是晶体管的源极或者漏极区，晶体管的多晶硅线LP(位于图1的左侧)从而形成栅极区域。在这种情况下，在多晶硅线LP的另一侧将存在另一有源区，并且该另一有源区将形成晶体管的漏极或源极区域。
因而，一般而言，有源区ZA可以是任何有源区，例如使得能够制作用于偏置在下方的衬底的接触的区。
在此处描述的示例中，集成电路IC包括多条平行的多晶硅线，在图1右侧的两条线搁置在绝缘区DS上、并且用作协助对栅极区域进行光刻的图案。
而且，接触CTC与多晶硅线LP平行延伸。其实现了与有源区ZA接触，并且在与多晶硅线LP平行的方向上从该有源区伸出以便与绝缘空腔CV0重叠。
在现在将描述的示例中，集成电路制造在SOI衬底上，虽然本发明并不限于这种类型的衬底。
而且，在以下附图中，偶数附图是沿着在图1中的线AA的示意性截面图，而奇数附图是沿着在图1中的线BB的示意性截面图。
现在将更加具体地参照图2至图19对用于制造接触CTC的方法的第一变型进行详细描述。
在图2和图3中，在接触的集成工艺的常规第一阶段之后获得的结构STR包括如上面所描述的SOI衬底，该SOI衬底包括：在埋入式绝缘层2(BOX)上的半导体膜3，埋入式绝缘层2(BOX)自身又由下方的半导体载体衬底1承载。
在此处描述的示例中，区4是沟槽隔离区，例如，浅沟槽隔离(STI)区。
有源区ZA通过硅50在两条多晶硅线LP之间外延而得到。
该外延的准备要求清洁处理，一般是基于氢氟酸(HF)的湿法处理，这种湿处理在晶片的所有暴露表面上，并且特别是在绝缘区4中，在两条多晶硅线LP之间，消耗一定量的氧化硅，从而导致形成空腔CV0、CV1、CV2。
而且，外延区域50和多晶硅线LP已经经历了硅化处理，有源区由此包括区51，该区51包括金属硅化物，例如硅化镍(NiSi)。
可以在图3中看出，空腔CV0的与有源区ZA接界的底部，与载体衬底1的部分相邻。
如图4和图5所示，将第一绝缘层6，该第一绝缘层6通常是由氮化硅制成的蚀刻阻挡层(该层通常被本领域技术人员设计为接触蚀刻阻挡层(CESL))，沉积在图2和图3中的结构STR上。
接下来，如图6和图7所示，将第一绝缘材料7，例如二氧化硅，沉积在该层6上。
接下来，进行化学机械抛光(图8和图9)。
在接下来的步骤中，如在图10和图11中图示的，将附加绝缘层8沉积在第一绝缘层6上并且沉积在第一绝缘材料7上，后者特别地填充了空腔CV0。
该附加绝缘层8还可以是氮化硅层。如在下面更加详细看出的，其还将用作蚀刻阻挡层。
接下来，如图12和图13所示，沉积第二绝缘材料9，例如，TEOS氧化物。
接下来，按照已知的常规方式，在掩膜10中制造限定出将来的接触CTC的几何形状的孔口100。
接下来，如图14和图15所示，通过孔口100，对第二绝缘材料9进行第一蚀刻GV1，以便限定出开口到附加绝缘层8上的第一孔口101。
该第一蚀刻GV1在层8上停止。举例说明，可以使用利用氟碳化学组成的反应离子蚀刻(RIE)。
在该阶段中，考虑到在空腔CV0之上存在附加绝缘层8，蚀刻GV1尚未蚀刻到存在于空腔CV0中的第一绝缘材料7；倘若该层8不存在，则会蚀刻到存在于空腔CV0中的第一绝缘材料7。
接下来，如图16和图17所示，进行第二蚀刻GV2，使得能够对层8和层6的部分进行蚀刻以便使有源区ZA的硅化区51暴露出来。而且，该蚀刻GV2还对位于空腔CV0之上的层8进行蚀刻并且消耗第一绝缘材料7的部分。因而，在该蚀刻GV2之后，在衬覆空腔CV0的第一绝缘层6的底部之上的第一绝缘材料7余留有高度h，例如，40nm。
该蚀刻GV2也是已知的常规蚀刻，例如，利用含有气体诸如CHxFy的化学组成的反应离子蚀刻。
附加绝缘层8有利地足够厚以能够用作针对蚀刻GV1的蚀刻阻挡层，并且足够薄以不干扰蚀刻GV2并且使硅化区51有效地暴露出来。包括在5nm与20nm之间的厚度是可接受的厚度。在实践中，附加绝缘层8具有大约10nm的厚度。
接下来，如图18和图19所示，用导电填充材料，例如铜、钨或者铝，填充在蚀刻GV2之后获得的孔口102。按照常规方式通过沉积进行该填充，之后进行化学机械抛光。
如可以在图18和图19中看出，此处的集成电路包括有源区ZA，该有源区ZA位于半导体衬底3之上。空腔CV0与有源区ZA接界，并且在绝缘区2(并且可能地，绝缘区4)中尽可能远地延伸到此处由载体衬底1的部分形成的半导体区域的附近。导电接触CTC位于绝缘多层内，并且存在于有源区ZA上，并且进入到空腔中。
此处的该绝缘多层包括第一绝缘层6，该第一绝缘层6覆盖了在接触CTC外部的有源区，至少部分地衬覆空腔CV0的壁，并且具有位于接触CTC与半导体区域1之间的区段60。
绝缘多层还包括绝缘区域，该绝缘区域在第一绝缘层6之上。该绝缘区域包括：围绕接触CTC的第一绝缘材料7和第二绝缘材料9、以及附加绝缘层8。该附加绝缘层8具有：覆盖了在接触CTC外部的第一绝缘层6的第一部分80；以及此处位于绝缘材料7与材料9之间并且与衬覆空腔CV0的壁的这部分第一绝缘层6相隔一定距离的第二部分81。
为了图示本发明的一个变型，更加具体地参照图20至图35。
根据本变型的方法也从在图2至图5中图示的步骤开始。
然后，如图20和图21所示，将覆盖第一绝缘层6的附加绝缘层12沉积在图4和图5中图示的结构上。
该附加绝缘层12形成势垒层，并且其相对于第一绝缘层6可以选择性地蚀刻。换言之，附加绝缘层12配置为在对第一绝缘层6蚀刻期间不被蚀刻或者几乎不被蚀刻。
通过指示的方式，第一绝缘层6可以包括氮化硅，而附加绝缘层12可以包括高介电常数k(通常高于15)的介电材料。这种电介质可以是，例如，AlO2、HfO2、AlN、TiN或者TiO2，并且不限于这些示例。
接下来，如图22和图23所示，将第一绝缘材料7沉积在该附加绝缘层12上。在该沉积之后，进行化学机械抛光，使得能够获得在图24和图25中图示的结构。更加精确地说，附加绝缘层12余留在空腔中，但是在第一绝缘层6的其他部分之上，尤其是在有源区ZA之上，已经被去除。
在这方面，附加绝缘层12有利地足够厚以用作蚀刻阻挡层，并且足够薄以不破坏化学机械抛光。
包括在2nm与15nm之间的厚度是可接受的厚度。通常，附加绝缘层12的厚度是大约6nm。
接下来，如图26和图27所示，沉积第二绝缘材料9，通常是TEOS氧化物。接下来，按照与上面描述的方式类似的方式，在掩膜10中形成使得能够限定出接触CTC的几何形状的孔口100(图28和图29)。
接下来，进行例如与蚀刻GV1相同的蚀刻GV4。一方面，该蚀刻GV4在有源区ZA之上的第一绝缘层6上停止，并且另一方面，该蚀刻GV4在空腔CV0的底部中的附加绝缘层12上停止。
由此形成孔口103(图30和图31)。
接下来，进行蚀刻GV5，这使得能够选择性地蚀刻附加绝缘层6，而不蚀刻或者近乎不蚀刻附加绝缘层12。
该蚀刻GV5是，例如，利用含有气体诸如CHxFy的化学组成的反应离子蚀刻。
然后，获得开口到有源区ZA的硅化区51上并且开口到在空腔CV0的底部中的附加绝缘层12上的孔口104。(图32和图33)。
接下来，按照与上面描述的方式类似的方式，填充孔口104以便形成导电接触CTC(图34和图35)。
在空腔CV0的底部中存在附加绝缘层12由此可以避免穿透第一绝缘层6，并且因此避免在接触CTC的端部与载体衬底1的相邻部分之间的短路。
如可以在图34和图35中看出，此时的绝缘多层包括：第一绝缘层6，该第一绝缘层6覆盖在接触CTC外部的有源区ZA并且衬覆空腔CV0的壁；以及附加绝缘层12，该附加绝缘层12覆盖第一绝缘层6的衬覆空腔的壁的部分。在空腔CV0中，接触CTC已经到达该附加绝缘层12。
而且，按照与上面描述的方式类似的方式，绝缘多层还包括绝缘区域，该绝缘区域位于第一绝缘层6和附加绝缘层12之上、并且包括围绕接触CTC的第一绝缘材料7和第二绝缘材料9。
本发明不限于刚刚描述的实施方法和实施例，而是囊括任何变型。
衬底也可以是支承了凸起有源区域的块体衬底。
本发明可以应用于任何类型的晶体管，尤其是平面MOS晶体管，但是也可以应用于FinFET MOS晶体管。

Claims (17)

1.一种用于在集成电路的有源区上制造接触的方法，所述有源区位于半导体衬底之上，包括：
在所述有源区之上、并且在空腔之中和之上，形成绝缘多层，所述空腔与所述有源区接界、并且在绝缘区中延伸到半导体区域的附近，其中所述形成包括：
形成覆盖所述有源区并且衬覆所述空腔的壁的第一绝缘层；以及
在所述第一绝缘层之上，形成绝缘区域；
蚀刻所述绝缘多层的部分，以便限定出开口到所述有源区上并且进入到所述空腔中的孔口；以及
用导电填充材料填充所述孔口；
其中形成所述绝缘区域包括：在已经形成所述第一绝缘层之后：
形成附加绝缘层，所述附加绝缘层被配置为在所述蚀刻操作期间防止穿透所述第一绝缘层的衬覆所述空腔的所述壁并且定位接近所述半导体区域的区段。
2.根据权利要求1所述的方法，其中形成所述绝缘区域包括：
用覆盖所述第一绝缘层的衬覆所述空腔的所述壁的所述部分的第一绝缘材料，来填充所述空腔，
形成覆盖所述第一绝缘层和所述第一绝缘材料的所述附加绝缘层；以及
在所述附加绝缘层上，形成第二绝缘层。
3.根据权利要求2所述的方法，其中蚀刻包括：
对所述第二绝缘层进行第一蚀刻，所述第一蚀刻在所述附加绝缘层上停止，以及
然后进行第二蚀刻，所述第二蚀刻被配置为：
蚀刻所述附加绝缘层、以及下方的所述第一绝缘层，以便使所述有源区暴露出来，以及
蚀刻所述附加绝缘层、以及下方的定位在所述空腔中的这部分所述第一绝缘材料，而不穿透所述第一绝缘层的所述区段。
4.根据权利要求2所述的方法，其中所述附加绝缘层的材料与所述第一绝缘层的材料相同。
5.根据权利要求1所述的方法，其中所述附加绝缘层的厚度在5纳米与20纳米之间。
6.根据权利要求1所述的方法，其中形成所述绝缘区域包括：
形成所述附加绝缘层，以覆盖所述第一绝缘层的衬覆所述空腔的所述壁的所述部分，所述附加绝缘层被配置为相对于所述第一绝缘层可以被选择性蚀刻，
用覆盖所述附加绝缘层的第一绝缘材料，来填充所述空腔；以及
在所述第一绝缘材料上，形成第二绝缘层。
7.根据权利要求6所述的方法，其中蚀刻包括：
对所述第二绝缘层进行第一蚀刻，所述第一蚀刻在所述第一绝缘层的位于所述有源区之上的所述部分上以及在所述附加绝缘层上停止，以及
然后进行第二选择性蚀刻，所述第二选择性蚀刻被配置为对所述第一绝缘层的位于所述有源区之上的所述部分进行蚀刻，以便使所述有源区暴露出来，而不蚀刻所述附加绝缘层。
8.根据权利要求6所述的方法，其中所述第一绝缘层包括氮化硅，并且所述附加绝缘层包括高介电常数氧化物。
9.根据权利要求1所述的方法，其中所述半导体衬底是由埋入式绝缘层承载的半导体膜，所述埋入式绝缘层自身又由载体衬底承载，所述埋入式绝缘层包括所述绝缘区的至少一部分，所述半导体区域是所述载体衬底的部分。
10.一种集成电路，包括：
至少一个有源区，所述至少一个有源区位于半导体衬底之上，
空腔，所述空腔与有源区接界，并且在绝缘区中延伸到半导体区域的附近，
绝缘多层；以及
导电接触，所述导电接触在所述绝缘多层内、存在于所述有源区上并且进入到所述空腔中，
其中所述绝缘多层包括：
第一绝缘层，所述第一绝缘层覆盖了在所述接触外部的所述有源区，至少部分地衬覆所述空腔的所述壁，并且具有定位在所述接触与所述半导体区域之间的区段，
绝缘区域，所述绝缘区域在所述第一绝缘层之上，包括围绕所述接触的至少一种绝缘材料，以及
附加绝缘层，所述附加绝缘层具有：第一部分，覆盖了在所述接触外部的所述第一绝缘层；以及第二部分，定位在所述接触外部，在所述至少一种绝缘材料内，并且与所述第一绝缘层的至少部分地衬覆所述空腔的所述壁的所述部分相隔一定距离。
11.根据权利要求10所述的集成电路，其中所述附加绝缘层的材料与所述第一绝缘层的材料相同。
12.根据权利要求11所述的集成电路，其中所述附加绝缘层和所述第一绝缘层包括氮化硅。
13.根据权利要求10所述的集成电路，其中所述附加绝缘层的厚度在5纳米与20纳米之间。
14.根据权利要求10所述的集成电路，其中所述半导体衬底是由埋入式绝缘层承载的半导体膜，所述埋入式绝缘层自身又由载体衬底承载，所述埋入式绝缘层包括所述绝缘区的至少一部分，所述半导体区域是所述载体衬底的部分。
15.一种集成电路，包括：
至少一个有源区，所述至少一个有源区位于半导体衬底之上，
空腔，所述空腔与有源区接界，并且在绝缘区中延伸到半导体区域的附近，
绝缘多层；以及
导电接触，所述导电接触在所述绝缘多层内、存在于所述有源区上并且进入到所述空腔中，
其中所述绝缘多层包括：
第一绝缘层，所述第一绝缘层覆盖了在所述接触外部的所述有源区，并且衬覆所述空腔的所述壁，
附加绝缘层，所述附加绝缘层覆盖所述第一绝缘层的衬覆所述空腔的所述壁的所述部分，所述接触在所述空腔中到达该附加绝缘层，以及
绝缘区域，所述绝缘区域在所述第一绝缘层和所述附加绝缘层之上，包括围绕所述接触的至少一种绝缘材料。
16.根据权利要求15所述的集成电路，其中所述第一绝缘层包括氮化硅，并且所述附加绝缘层包括高介电常数氧化物。
17.根据权利要求15所述的集成电路，其中所述半导体衬底是由埋入式绝缘层承载的半导体膜，所述埋入式绝缘层自身又由载体衬底承载，所述埋入式绝缘层包括所述绝缘区的至少一部分，所述半导体区域是所述载体衬底的部分。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130026570A1 (en) * 2011-07-27 2013-01-31 International Business Machines Corporation Borderless contact for ultra-thin body devices
US20140315379A1 (en) * 2013-04-18 2014-10-23 International Business Machines Corporation Contact structure employing a self-aligned gate cap
CN104517902A (zh) * 2013-10-07 2015-04-15 格罗方德半导体公司 简化的先栅极hkmg制造流程
CN205282459U (zh) * 2015-06-18 2016-06-01 意法半导体(克洛尔2)公司 集成电路

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US20140051239A1 (en) * 2012-08-14 2014-02-20 International Business Machines Corporation Disposable carbon-based template layer for formation of borderless contact structures
US8987070B2 (en) * 2012-09-12 2015-03-24 International Business Machines Corporation SOI device with embedded liner in box layer to limit STI recess

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130026570A1 (en) * 2011-07-27 2013-01-31 International Business Machines Corporation Borderless contact for ultra-thin body devices
US20140315379A1 (en) * 2013-04-18 2014-10-23 International Business Machines Corporation Contact structure employing a self-aligned gate cap
CN104517902A (zh) * 2013-10-07 2015-04-15 格罗方德半导体公司 简化的先栅极hkmg制造流程
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