CN106253852A - 包括隆起焊块的谐振电路 - Google Patents

包括隆起焊块的谐振电路 Download PDF

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Publication number
CN106253852A
CN106253852A CN201610395780.3A CN201610395780A CN106253852A CN 106253852 A CN106253852 A CN 106253852A CN 201610395780 A CN201610395780 A CN 201610395780A CN 106253852 A CN106253852 A CN 106253852A
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China
Prior art keywords
nude film
capacity cell
protuberance
welding block
nude
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CN201610395780.3A
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CN106253852B (zh
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C·张
J·A·切萨
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Analog Devices Inc
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Analog Devices Inc
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    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
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    • H03B5/12Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1203Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier being a single transistor
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Abstract

本发明涉及包括隆起焊块的谐振电路。本公开的方面涉及第一裸片,所述第一裸片包括LC谐振电路,LC谐振电路包括诸如电容器或变容二极管的第一电容元件以及电感元件。LC谐振电路构造为产生具有振荡频率的信号。第一裸片包括与所述第一电容元件的两端电耦合的隆起焊块。第二裸片可以是安装在所述第一裸片上的翻转芯片。隆起能够将第二裸片的第二电容元件与第一裸片的第一电容元件并联地电连接。这能够提高LC谐振电路的Q因数。

Description

包括隆起焊块的谐振电路
技术领域
本公开的实施方案涉及到电子系统,并且更特别地涉及到谐振器电路。
背景技术
电子设备能够制作在裸片上。一些电子设备可以包括谐振器。谐振器能够用于各种应用,包括振荡器。实施例的振荡器包括Colpitts电压控制型振荡器(VCO)、ColpittsVCO的推-推版本以及Clapp VCO。谐振器可由品质因数(“Q因数”)来表征。谐振器中的损耗会影响Q因数。通过增大裸片上诸如电容器的一些部件的尺寸,能够减小损耗以及能够增加Q因数。然而,减小部件的尺寸可能是不期望的。
发明内容
本公开的一个方面是包括第一裸片和第二裸片的系统。第一裸片包括LC谐振电路,该LC谐振电路包括第一电容元件和电感元件,所述第一电容元件具有第一端和第二端。第一裸片还包括第一隆起焊块和第二隆起焊块,该第一隆起焊块与第一电容元件的第一端电耦合,第二隆起焊块与第一电容元件的第二端电耦合。第二裸片叠置在第一裸片上,并且第二裸片包含具有第一端和第二端的第二电容元件,与第二电源元件的第一端电耦合的第三隆起焊块,以及与第二电容元件的第二端电耦合的第四隆起焊块。第一隆起将第一隆起焊块和第三隆起焊块电耦合,第二隆起将第三隆起焊块与第四隆起焊块电耦合,使得第一隆起和第二隆起将第一电容元件与第二电容元件并联地电连接。
电容元件可包括第一变容二极管或第一电容器。隆起可包括铜柱、焊球或焊接接缝。电感器可以是阻流电感器,并且电感器能够通过微带线与第一电容元件耦合。第一裸片可以包括电压控制振荡器(VCO),其包括LC谐振电路。VCO可以具有基于由VCO接收到的调谐电压的谐振频率。第一裸片可以包括多个有源电路。
在系统中,第二裸片上的第二电路可以是第一裸片上的第一电路的翻转的镜像,并且第一电路可包括第一电容元件。第二电路可包括微带线和隆起焊块。第一电路可包括至少一个电容器和至少一个变容二极管。
该系统可以包括封装第一裸片和第二裸片的封装件、布置在第一裸片与第二裸片之间的绝缘体以及将第一裸片与封装件的引脚耦合的焊线。
本公开的另一方面是包括LC谐振电路的裸片,该LC谐振电路配置为产生以谐振频率振荡的信号。LC谐振电路包括具有第一端和第二端的电容元件以及与电容元件电耦合的电感元件。裸片还包括与电容元件的第一端电耦合的第一隆起焊块以及与电容元件的第二端电耦合的第二隆起焊块。
电容元件可以包括变容二极管或电容器中的至少一个。电感器可构造为阻流电感器,并且电感器可以通过微带线与电容元件耦合。
LC谐振电路可包括第二电容元件,并且裸片可包括与第二电容元件连接的第三隆起焊块。裸片可包括电压控制振荡器,并且VCO可以包括LC谐振电路。第一隆起焊块可布置在第一微带上,并且第二隆起焊块可布置在第二微带上。
本公开的另一方面涉及到制造电子设备的方法。该方法包括将来自第一裸片上的第一电容元件的第一端的第一隆起与第二裸片上的第二电容元件的第一端电耦合。第一电容元件包含在第一裸片的LC谐振电路中。该方法还包括:将来自第一裸片上的第一电容元件的第二端的第二隆起与第二裸片上的第二电容元件的第二端电耦合,使得第二电容元件与第一电容元件并联地电连接。
第一隆起可以是铜柱、焊球或焊接接缝中的至少一个。
该方法还可以包括:将第二裸片安装到第一裸片上,使得第一裸片的隆起焊块与第二裸片的对应的隆起焊块对准。该方法还可以包括:用绝缘材料填充第一裸片与第二裸片之间的空间,以及将第一裸片和第二裸片包封在封装材料中。
为了概述本公开,本文已经描述了本发明的一些方面、优点和新颖的特征。应当理解,不一定根据本发明的任何特定实施方案都能够实现所有这些优点。因此,本发明能够以实现或优化如本文所教导的一个优点或一组优点而不一定实现本文可以教导或暗示的其它优点的方式来具体体现或实施。
附图说明
图1是根据实施方案的第一裸片上的实施例的电压控制振荡器(VCO)系统的示意图。
图2是根据实施方案的第二裸片上的实施例的电路的示意图。
图3是根据实施方案的在第一裸片上的微带线上方镜像的第二裸片上的对应的微带线的立体图示。
图4是在各噪声频率下将一个实施方案的相位噪声与传统VCO的相位噪声进行比较的曲线图。
图5是根据实施方案的两个芯片的封装件的示意图。
图6是根据实施方案的封装件内的两个叠置的裸片的示意性剖面侧视图。
图7是根据实施方案的用于制造电子设备的方法的流程图。
具体实施方式
一些实施方案的以下详细说明呈现了具体实施方案的各个说明。然而,本文描述的创新能够以多种不同的方式来具体体现,例如,如权利要求中限定和覆盖的。在该说明书中,参考了附图,在附图中相似的附图标记可以指代相同或功能上相似的元件。将理解的是,图总所示的元件不一定是按比例绘制的。而且,将理解的是,一些实施方案可以包括比附图中图示的更多的元件和/或特定图中的图示的元件的子集。此外,实施方案可以包含来自两个以上图的任何适合的特征组合。
如上文所论述的,谐振器能够由品质因数(“Q因数”)来表征。谐振器可包括电感器和电容元件。电容元件可以是提供电容的任何部件,诸如变容二极管或电容器。本文论述的电容元件是显式电容元件,而不仅仅是寄生电容。
谐振器具有多种应用。谐振器能够用于例如滤波器、放大器、调谐器、混合器以及各种其它电路。谐振器还能够用作振荡器的部分,包括电压控制振荡器(VCO)。与本文论述的LC谐振电路相关联的原理和优点能够与VCO、固定振荡器、滤波器、或者任何其它适合的受益于较低损耗的具有LC谐振电路的电路相结合地实现。
在一些应用中,相对高的Q因数是期望的。较高的Q因数能够通过使得谐振器部件损耗较少来实现。在谐振器中,电容元件会显著地贡献于谐振器的损耗。微带线也会贡献于损耗。虽然增大部件尺寸(例如,增加电容器的电容)可以减少损耗,但是增加部件尺寸不总是可取。较大的部件尺寸会减小芯片产量,为裸片上的其它电路部件留下较少的空间,产生更多的热,消耗更多的功率,导致更大的封装,等等。
为了增加Q因数,第二裸片可以是安装到包括LC谐振电路的第一裸片上的翻转芯片。当不同裸片中的一些部件耦合在仪器时,Q因数会增加,而不会增加第一裸片上的谐振器的印迹。第二裸片上的电容电路元件与第一裸片上的具有近似相同的电容的电容元件并联,相对于仅第一裸片的电容元件而言能够使得电容几乎加倍,同时降低损耗。利用翻转芯片安装的第二裸片使得电容加倍能够使得Q因数近似加倍。作为一个实施例,Q因数可以从用于第一裸片的谐振器的大约25加倍到实现实施方案的谐振器的大约50。通过隆起将第一裸片的第一微带线与第二裸片的第二微带线电连接能够降低与谐振器相关联的损耗。;
图1是第一裸片上的实施例的VCO系统100的示意图。VCO系统100可以包括谐振电路101、第一有源电路103、第二有源电路105、输入节点107和输出节点109。谐振电路101可以包括阻流电感器111a至111c、电容器113a和113b、变容二极管115a和115b、微带线117a至117g以及隆起焊块119a至119g。图示的微带线117a至117g中的每一个能够以第一裸片的任何适合的金属层例如金属0、金属1或金属2来实现。微带线117a至117g中的一个或多个能够以不同于其它微带线117a至117g中的一个或多个的金属层来实现。
VCO系统100能够在输入节点107处接收输入电压信号,并且在输出节点109处生成输出信号。输出信号的频率能够通过输入电压信号的电压电平来控制。在图1所示的实施方案中,VCO是推-推式单端VCO,其包括作为有源电路103和105的Colpitts型负电阻器核心。
第一裸片的微带线将电路元件电耦合在仪器。电容器113a耦合在微带线117a与117b之间。阻流电感器111a一端耦合到地,阻流电感器111a的另一端耦合到微带线117b和117c。变容二极管115a耦合在微带线117c与117d之间。电感器111b一端耦合到输入节点107和电容器113c,并且电感器111b另一端耦合到微带线117d。电容器113c一端耦合到输入节点107和电感器111b,电容器113c另一端耦合到地121c。变容二极管115b耦合在微带线117d与117e之间。阻流电感器111c一端耦合到地121b,阻流电感器111c另一端耦合到微带线117e和117f。虽然在图1中示出了一对变容二极管,在其它一些实施方案中能够实现多个变容二极管和/或变容二极管对。电容器113b耦合在微带线117f与117g之间。
在一些实现中能够组合图示的一些微带线。例如,微带线117b和117c能够实现为单个微带线作为单个连续微带线的不同部分。相同适用于微带线117e和117f。虽然示出了一个谐振电路设计,本文论述的原理和优点能够应用于任何其它适合的LC谐振电路。
隆起焊块119a至119g能够分别与微带线117a至117g耦合。在第一裸片上,在电容元件的不同侧的两个微带线可具有使得第一裸片的电容元件能够与第二裸片上的另一电容元件并联地耦合的隆起焊块。例如,在电容器113a的相对侧上的隆起焊块119a和119b使得电容器113a能够通过隆起与叠置在第一裸片上的第二裸片上的电容元件电耦合。作为另一实施例,在变容二极管115b的相对侧上的隆起焊块119d和119e使得变容二极管115b能够通过隆起而电性地成为叠置在第一裸片上的第二裸片上的电容元件。
图2是在第二裸片上的实施例电路200的示意图。电路200包括由对应于谐振电路101的类似部分的类似附图标记和单引号(’)标示的电路元件。如图所示,实施例的电路200包括微带线117a’至117g’、隆起焊块119a’至119g’、电容器113a’和113b’以及变容二极管115a’和115b’。
在第二裸片上的电路200能够制成使得第二裸片上的电路元件具有与第一裸片上的对应的部分基本上相同的位置、尺寸和布局,除了第二裸片的有源侧面上的电路元件相对于第一裸片的有源侧面翻转之外。因此,当第二裸片叠置在第一裸片上时,来自不同裸片的对应的电路元件能够相对于彼此对准。第二裸片能够翻转芯片安装到第一裸片之上且隆起能够将与第二裸片的对应的隆起焊块对准的第一裸片的隆起焊块电连接。
将第二裸片翻转芯片安装到第一裸片上可以包括将第一裸片的隆起焊块119a至119g与第二裸片的对应的隆起焊块119a’至119g’电耦合。这能够利用任何适合类型的隆起来完成。隆起可通过例如铜柱、焊球、焊接接缝或其它适合的导电结构来实现。隆起能够通过相对低损耗的金属来实现。为隆起使用相对低损耗的金属能够相对于具有较高损耗的材料改善谐振器的Q因数。通过铜柱实现的隆起能够提供相对低的损耗以及相对高的导电率。
当第二裸片安装到第一裸片上时,第二裸片的电路200的电路元件能够与第一裸片的谐振电路101的对应部分对准。第一裸片的谐振电路101的一些或全部的电容元件能够镜像到第二裸片的电路200中。隆起能够将第一裸片的各电路元件与第二裸片的对应的电路元件并联地电耦合。例如,隆起能够将第一裸片的电容器113b与第二裸片的电容器113b’并联地电连接。作为另一实施例,隆起能够将第一裸片的变容二极管115b与第二裸片的变容二极管115b’并联地电连接。彼此并联地耦合的电容元件可以具有增加的有效电容,较低的损耗,并且会导致谐振器的Q因数增加。彼此并联地耦合的不同裸片上的微带线会比一个裸片上的单个微带损耗少。微带线还能够贡献于增加谐振器的Q因数。
如图2所示,第二裸片的电路200不包括对应于第一裸片的电感器111a至111c的电感器或者对应的接地连接。因此,仅第一裸片的LC谐振电路的电容元件可包含在如图2所示的第二裸片上。在一些其它的实施方案中,第二裸片可以包括对应于第一裸片的谐振电路的电感器的电感器。如图2所示,在一些实施方案中,第二裸片的电路200不包括对应于图1的电容器113c的电容器。
虽然图2示出了在第二裸片上的多个电容元件,在一些实施方案中第二裸片可仅包含在两端与隆起焊块耦合以减少归因于第一裸片上的对应的电容元件的损耗的单个电容元件。例如,在一个实施方案中,第二裸片可以包括电容器113a’、微带线117a’和117b’以及隆起焊块119a’和119b’。在另一实施方案中,第二裸片可包括变容二极管115b’、微带线117d’和117e’,以及微带线117d’和117e’以及隆起焊块119d’和119e’。在一些其它的实施方案中,第二裸片可包括独立的谐振器的全部的电路元件。
图3是在第一裸片301上的微带线315上方镜像的第二裸片307上的对应的微带线317的立体图示300。图3示出了微带线315和317、铜柱319以及隆起焊块119’。
第一裸片301具有背面303和有源侧面305。微带线315可以在第一裸片301的有源侧面305上。微带线315可以对应于例如图1中所示的任意微带。
第二裸片307位于第一裸片301上方的空间313中。第二裸片307具有有源侧面309和背面311。对应的微带线317可以在第二裸片307的有源侧面309上。微带线317可以对应于例如图2中的任何图示的微带。因为第二裸片307已经翻转芯片安装到第一裸片303的上方,所以第二裸片307的有源侧面朝下朝向第一裸片303。为清晰图示,第二裸片307图示为透明的。
隆起将第二裸片307的微带线317上的隆起焊块119’与第一裸片301的对应的微带线315上的隆起焊块119电耦合。在图3中,隆起被描绘为多个铜柱319,微带线317的隆起焊块被描绘为多个隆起焊块119’,并且铜柱319下方的将铜柱319与第一裸片301的微带线315耦合的隆起焊块从该视角不可见。因此,在电容元件的每个相对侧的隆起焊块能够各自由一个或多个隆起焊块来实现。类似地,一个或多个隆起能够将第一裸片的电容电路元件的每端与第二裸片上的对应的电容元件电连接。具有并联的两个以上的隆起能够减小与电源元件之间相对于单个隆起的电连接相关联电阻。在各个实施方案中,隆起、隆起焊块和微带线可以各自具有用于特定应用的任何适合的尺寸。隆起、隆起焊块和/或微带线可以在一些实现中具有相对于彼此不同的尺寸。
微带线315可以是例如在谐振电路101中的任何微带线117[a-g]。微带线317可以是谐振电路201中的任何对应的微带线117[a’-g’]。例如,在一个实施方案中,微带线315可以是117c,并且微带线317可以是117c’。
第一裸片301与第二裸片307之间的空间313可以填充有任何适合的非导电封装材料,诸如围绕铜柱319的塑料、绝缘体、介电物等。
虽然图3仅描绘了镜像的微带线,应当理解,第二裸片307定位在第一裸片301上以及所描述的其它原理能够应用于第一裸片的谐振电路100的其余部分的一些或全部以及第二裸片的对应的电路元件。
图4是示出相比于根据实施方案的VCO,传统VCO的相位噪声关于噪声频率的关系的曲线图400。x轴表示在对数标度上范围从1,000赫兹到1,000,000的VCO噪声频率。y轴表示VCO所生成的从-140dBc/Hz至-70dBc/Hz的相位噪声。
曲线405表示在传统VCO的噪声频率范围内生成的相位噪声。第二曲线407表示在包括具有谐振电路的第一裸片以及翻转芯片安装到第一裸片上的第二裸片的VCO系统的一个实施方案的噪声频率范围内生成的相位噪声。显然,翻转芯片VCO实施方案相比于传统VCO在所描绘的频率范围内产生了较少的相位噪声。例如,相对于传统VCO,包括翻转芯片安装到第一裸片上的第二裸片的VCO系统,在10KHz处有近似10dBc/Hz的改进。
图5是用于两个裸片301和307的封装件501的示意图。示意图包括四方扁平无引线(QFN)封装件501,其包括裸片焊盘503、第一裸片301、翻转芯片安装到第一裸片301上的第二裸片307、通过焊线507a至507d与各个I/O封装触头509a至509d耦合的多个线焊块505a至505d。虽然示出了四个焊线507a至507d,但是应当理解,焊线能够将32个I/O封装触头或者其任何适合的子集中的每一个电连接。一些实施方案可以包括如下的裸片:在裸片上具有与I/O封装触头耦合的复杂电路系统和相对大量的I/O焊块,从而发送或接收电信号用于各种不同的目的。在一些实现中,封装件可以是5mm乘5mm。在这些实现中的一些实现中,相邻的I/O封装触头的中心能够间隔开大约0.5mm。
多个隆起和隆起焊块(统一标记为511)将第一裸片301上的电路元件与第二裸片307上的对应的电路元件耦合。虽然在图5中示出了隆起和隆起焊块511,但是应当理解,它们在不透明的第二裸片307的下面并且可能不能从图示的视角可见。
在一些实施方案中,第一裸片301包括作为来自图1的VCO系统100的部分的谐振电路101。图1的输入节点107能够与线韩焊块505a耦合,线韩焊块505a可以通过焊线507a与封装I/O触头509a电连接。图1的VCO系统100输出节点109能够与线韩焊块505c耦合,线韩焊块505c能够通过焊线507c与封装I/O触头509c电连接。
在一些实施方案中,第一裸片301包括谐振电路。封装I/O触头509a能够通过焊线507a与线焊焊块505a电连接,线焊焊块505a能够与谐振电路的输入耦合。谐振电路的输出节点能够与线焊焊块505c耦合,线焊焊块505c能够通过焊线507c与封装I/O触头509c电连接。
在一些实施方案中,第一裸片301包括包含了谐振电路的滤波器。封装I/O触头509a可以线焊507a到线焊焊块505a,线焊焊块505a能够与滤波器的输入耦合,用于接收输入信号。滤波器的输出节点能够与线焊焊块505c耦合,线焊焊块505c可以线焊507c到封装I/O触头509c,从而输出滤波信号。
在一些实施方案中,封装I/O触头509b能够通过焊线507b与线焊焊块505b电连接,线焊焊块505b能够与第一裸片301上的功率输入节点耦合。接地节点能够与线焊焊块505d耦合,线焊焊块505d能够通过焊线507d与封装I/O触头509d电连接。在一些实施方案中,线焊焊块505d能够与地平面耦合。
图6是在封装件501内的两个叠置的裸片301,307的示意性剖面侧视图。图6的剖面侧视图可对应于图5的封装件。封装件501包括I/O引脚509a和509c、焊线507a和507c、线焊焊块505a和505c、裸片焊盘503、铜柱319和填充材料613。
第二裸片307翻转芯片安装到第一裸片301上。第一裸片301的电容元件通过铜柱319与第二裸片307的电容元件并联地耦合。
填充材料613填充第一裸片301与第二裸片307之间的空间。填充材料可以是例如塑料、介电物、绝缘体或任何其它适合的填充材料。在一些实施方案中,填充材料可以是空气。在一些其它的实施方案中,填充材料613可以起到防止空气或潮气进入第一裸片301与第二裸片307之间的作用。在一些实施方案中,除了由铜柱319提供的结构支撑之外,填充材料提供了使得第二裸片307抵靠在第一裸片301之上的结构支撑。
封装件501可以是QFN或任何其它适合类型的IC封装件。封装件501可以由塑料、电绝缘体、热导体或任何其它适合类型的封装材料。封装件501具有封装I/O触头509a,其可以是如图所示的I/O引脚。焊线507a能够将封装I/O触头与第一裸片301上的线焊焊块505a电连接。第一裸片301还具有线焊焊块605b,该线焊焊块605b通过线焊507c与封装I/O触头509c电耦合。第一裸片301上的线焊焊块505a和505c能够提供到第一裸片301上的电路的电连接。
在一些实施方案中,第一裸片301可以包括VCO系统100,并且VCO系统100配置为接收具有输入电压的信号。输入信号能够通过封装I/O触头509a、焊线507a和焊线焊块505a传输到VCO的输入节点107。具有受输入信号的电压控制的振荡频率的输出信号能够通过VCO的输出节点109、焊块505c、焊线507c以及通过封装I/O触头509c来传输。
在一些实施方案中,I/O触头(例如,I/O引脚)能够用于不同的目的或者连接到相同或不同的电路的不同部分。例如,它们能够连接到谐振器、振荡器、滤波器等的部分。第二裸片307可以包括在之前所述的各种应用中的谐振器的电容电路元件,并且附加的电路系统能够以不同的方式使用谐振器。谐振器能够生成在裸片内内部使用的输出信号,并且裸片可以具有通过封装I/O触头509c传输的不同的输出信号。
图7是制造电子设备的示例性的方法700的流程图。在框710,在诸如第一裸片301的第一裸片上制作第一LC电路。在制作后,第一裸片可被切块。第一裸片可以包括本文所述的第一裸片的特征的任意组合。第一裸片包括LC谐振电路,LC谐振电路包括电容电路元件。在框720,第二电路制作在第二裸片上,例如第二裸片307。第二裸片可以包括本文所述的第二裸片的特征的任意组合。第二裸片包括至少电容电路元件。在第二电路安装到第一裸片上之后,第二电路可以与第一电路的部分镜像和/或对准。第二电路可以是第一电路的翻转版本。
在框730,可以形成隆起。在一些实施方案中,隆起可以形成在第二裸片上。在一些其它的实施方案中,隆起可以形成在第一裸片上。隆起可以形成在隆起焊块上。
在一些实施方案中,第二裸片可以在第二电路制作在第二裸片上之后以及第二裸片被切块之前进行切块。在一些其它的实施方案中,第二裸片可以在第二裸片上形成隆起之后进行切块。
在框740,第二裸片翻转且安装到第一裸片上。在该方法中,第二裸片翻转而使得第二裸片的有源侧面相对第一裸片的有源侧面。当第二裸片叠置在第一裸片上时,来自裸片的对应的电路元件能够对准。因此,在框740中的翻转和安装能够使得空气将第二裸片上的电容元件与第一裸片上的电容元件并联地电耦合。
在一些实施方案中,在第二裸片翻转且安装到第一裸片上之前,第一裸片可以通过环氧处理或以其它方式紧固到裸片焊盘上。在第二裸片翻转且安装到第一裸片上之后,隆起可以被反流。
第一裸片可包括LC谐振电路。LC谐振电路可以包括电容元件,诸如电容器或变容二极管;电感元件,诸如电感器;以及输出节点。LC谐振电路可以包括微带线以及多个电容元件。以谐振频率谐振的输出信号可以是输出节点处的输出。隆起可以包括铜柱、焊球、焊接接缝、其它焊料形式或各种形状的其它金属或导电隆起。在一些实施方案中,第一裸片包括作为VCO的部分的LC谐振电路。VCO能够在输出节点处生成以输出频率振荡的输出信号,该输出频率由输入节点处接收到的输入信号的电压来控制。
第二裸片可包括诸如电容元件的LC谐振电路的部分。在一些实施方案中,第二裸片上的电路可以是独立LC谐振电路。第二裸片上的电路可以包括多个电容元件以及多个微带线。
在框750,第一裸片和第二裸片可以封装在仪器。第一裸片与第二裸片之间的空间可以由绝缘材料来填充。封装件的引脚能够例如通过线焊接与第一裸片电连接。第一裸片和第二裸片能够包封在封装材料中。在一个实施方案中,第一裸片中的输出节点例如通过线焊与封装件输出引脚耦合,并且第一裸片中的输入节点例如通过线焊与封装件输入引脚耦合。可以对第一和第二裸片应用二次成型。
在一个实施方案中,第一裸片上的有源电路的输出例如通过线焊与封装件输出引脚耦合。有源电路可以是不同于LC谐振电路且不同于VCO的电路。有源电路能够接收来自LC谐振电路或VCO的输出信号作为输入。
本文所论述的方法的行为能够按照任何顺序适当地执行。而且,本文论述的方法的行为能够适当地串行或者并行地执行。
各个实施方案能够应用制作不同类型的电子设备的不同技术。一个实施方案应用于单片微波集成电路(MMIC)的制作。
在上述的实施方案中,结合特定实施方案描述了用于在第一裸片和翻转芯片安装到第一裸片上的第二裸片上的谐振电路的装置、系统和方法。然而,将理解的是,实施方案的原理和优点能够用于任何其他的对于谐振器有需要的系统、装置或方法。虽然参考实施例的LC谐振器电路描述了一些实施方案,将理解的是本文所描述的原理和优点能够应用于其他谐振器所产生且用于各种应用的信号。虽然所公开的一些实施方案可参考表征负电阻器核心的Colpitts类型为有源电路的推-推式单端VCO来描述,但是本文论述的原理和优点能够应用于其他类型的VCO和有源电路、固定振荡器、滤波器或其他包括LC谐振电路的适合的电路。虽然公开的实施方案可参考一些引脚和/或封装布局来描述,本文论述的原理和优点能够应用于其他类型的引脚和封装布局。而且,虽然一些电路示意图是为了示例的目的而提供,其他等价电路能够替选地实施以实现本文所描述的功能。
在上文描述的实施方案中,第二裸片翻转芯片安装到第一裸片上。本文论述的原理和优点能够应用于竖直堆叠的三个以上的裸片。在竖直堆叠中有三个以上裸片的情况下,用于将各个裸片上的电路并联地彼此电耦合的贯通一个或多个中间裸片的通孔或其他技术能够得以实施。例如,延伸贯通裸片的通孔能够将裸片相对侧上的隆起焊块电连接,并且这些隆起焊块能够通过隆起与堆叠中的其他裸片电连接。替选地或者另外地,本文论述的原理和优点能够应用于两个以上的不同裸片翻转芯片安装到其上的第一裸片,其中两个以上的不同裸片不叠置在彼此之上。
本申请中使用的术语微带线无需一定是微小等级的、带形的或线形的。例如,图3描绘了改变方向的微带线的部分。微带线不包括焊线的位于裸片之外的部分。如本申请中使用的术语镜像无需是指完全的实际反映,因为制作公差是不完美的,可针对取路径或制作规则来调节电路元件。此外,应当指出,一些对称的电路可视为翻转的。如在该申请中使用的术语隆起焊块无需一定是物理隆起或形状类似焊块。例如,有时隆起焊块是指在裸片表面处露出的开口。如本申请中使用的术语引脚无需一定具有带尖的端。
本文所描述的原理和优点能够实施在各种装置中。该装置的实施例可包括但不限于,消费电子产品、消费电子产品的零件、电子测试装备等。消费电子产品的零件的实施例可以包括时钟电路、模数转换器、放大器、整流器、可编程滤波器、衰减器、可变频率电路等。电子设备的实施例还可以包括存储器芯片、存储器模块、光学网络电路或其他通信网络电路、诸如基站的蜂窝通信基础结构以及磁盘驱动器电路。消费电子产品可包括但不限于,无线设备、移动电话(例如,智能手机)、健康监测设备、车辆电子系统如汽车电子系统、电话、电视、计算机监视器、计算机、手持式计算机、平板式计算机、膝上型计算机、个人数字助理(PDA)、微波、冰箱、立体声系统、盒式记录仪或播放器、DVD播放器、CD播放器、数字视频记录仪(DVR)、VCR、MP3播放器、无线电、摄像录像机、照相机、数字照相机、便携式存储器芯片、洗衣机、干燥机、洗衣机/干燥机、复印机、传真机、扫描仪、多功能外围设备、腕式手表、时钟等。此外,装置可包括非成品。
除非上下文明确要求,否则在说明书和权利要求书中,用语“包括”、“包括有”、“包含”、“包含有”等应以包含的含义进行解释,与排除性或穷尽的含义相反;也即,在“包含,但不限于”的意义上。如本文通常使用的术语“耦合”或“连接”是指能够直接连接或者通过一个或多个中间元件连接的两个以上的元件。另外,用语“本文中”、“上方”、“下方”以及类似含义的用语当在该申请中使用时应当整体指代该申请,而不是指代该申请的任何特定部分。在上下文允许的情况下,使用单数或复数的详细说明中的用语还可以分别包括复数或单数。在提到两个以上项的列表时的用语“或者”意在涵盖该用语的所有以下解释:列表中的任意项,列表中的全部项,以及列表中的项的任意组合。在本文提供的全部数值意在包含测量误差内的类似值。
而且,除非具体陈述或者在所使用的上下文内理解,否则本文所使用的诸如“能够”、“可以”、“可能”、“会”、“例如”、“诸如”等以及其他的条件语言一般意在传达一些实施方案包含一些特征、元件和/或状态,而其他实施方案不包含一些特征、元件和/或状态。
本文提供的发明的教导能够应用于其他系统,而不一定是上述的系统。上述的各实施方案的元件和行为能够组合以提供进一步的实施方案。
虽然已经描述了本发明的一些实施方案,这些实施方案仅通过实施例的方式提供,而不意在限制本公开的范围。事实上,本文所描述的新颖的方法和系统可以多种其他形式来具体体现。此外,本文所描述的方法和系统的形式上的各种省略、替代和变化可以被做出,而不偏离本公开的精神。随附的权利要求及其等同布置意在涵盖落入本公开的范围和精神内的这样的形式或修改。因此,本发明的范围是参考权利要求而被限定的。

Claims (20)

1.一种系统,包括:
第一裸片,包括:
LC谐振电路,其包括第一电容元件和电感元件,所述第一电容元件具有第一端和第二端;
第一隆起焊块,其与所述第一电容元件的第一端电耦合;以及
第二隆起焊块,其与所述第一电容元件的第二端电耦合;
第二裸片,其叠置在所述第一裸片上,所述第二裸片包括:
第二电容元件,其具有第一端和第二端;
第三隆起焊块,其与所述第二电容元件的第一端电耦合;以及
第四隆起焊块,其与所述第二电容元件的第二端电耦合;
第一隆起,其将所述第一隆起焊块与所述第三隆起焊块电耦合;以及
第二隆起,其将所述第三隆起焊块与所述第四隆起焊块电耦合,使得所述第一隆起和第二隆起将所述第一电容元件与所述第二电容元件并联地电连接。
2.如权利要求1所述的系统,其中所述第一电容元件包括第一变容二极管或第一电容器中的至少一个。
3.如权利要求1所述的系统,其中所述第一隆起包括铜柱、焊球或焊接接缝中的至少一个。
4.如权利要求1所述的系统,其中所述第二裸片上的第二电路是所述第一裸片上的第一电路的翻转的镜像,并且其中所述第一电路包括所述第一电容元件。
5.如权利要求4所述的系统,其中所述第二电路包括微带线和隆起焊块。
6.如权利要求4所述的系统,其中所述第一电路包括至少一个电容器和至少一个变容二极管。
7.如权利要求1所述的系统,进一步包括:
封装所述第一裸片和所述第二裸片的封装件;
布置在所述第一裸片与所述第二裸片之间的绝缘体;以及
将所述第一裸片与所述封装件的引脚耦合的焊线。
8.如权利要求1所述的系统,其中所述绝缘体构造为阻流电感器,并且其中所述电感器通过微带线与所述第一电容元件耦合。
9.如权利要求1所述的系统,其中所述第一裸片包括电压控制振荡器(VCO)、包括LC谐振电路的VCO,其中所述VCO具有基于由所述VCO接收的调谐电压的谐振频率。
10.如权利要求9所述的系统,进一步包括在所述第一裸片上的多个有源电路。
11.一种裸片,包括:
LC谐振电路,其构造为产生以谐振频率振荡的信号,所述LC谐振电路包括:
具有第一端和第二端的电容元件;以及
与所述电容元件电耦合的电感元件;
第一隆起焊块,其与所述电容元件的第一端电耦合;以及
第二隆起焊块,其与所述电容元件的第二端电耦合。
12.如权利要求11所述的裸片,其中所述电容元件包括变容二极管或电容器中的至少一个。
13.如权利要求11所述的裸片,其中所述电感器构造为阻流电感器,并且其中所述电感器通过微带线与所述电容元件耦合。
14.如权利要求11所述的裸片,其中所述LC谐振电路包括第二电容元件,并且其中所述裸片包括与所述第二电容元件连接的第三隆起焊块。
15.如权利要求11所述的裸片,其中所述裸片包括电压控制振荡器,其中所述电压控制振荡器包括所述LC谐振电路。
16.如权利要求11所述的裸片,其中所述第一隆起焊块布置在第一微带上,并且所述第二隆起焊块布置在第二微带上。
17.制造电子设备的方法,所述方法包括:
将来自所述第一裸片上的第一电容元件的第一端的第一隆起与所述第二裸片上的第二电容元件的第一端电耦合,其中所述第一电容元件包含在所述第一裸片的LC谐振电路中;以及
将来自所述第一裸片上的所述第一电容元件的第二端的第二隆起与所述第二裸片上的所述第二电容元件的第二端电耦合,使得所述第二电容元件与所述第一电容元件并联地电连接。
18.如权利要求17所述的方法,其中所述第一隆起包括铜柱、焊球或焊接接缝中的至少一个。
19.如权利要求17所述的方法,进一步包括将所述第二裸片安装在所述第一裸片上,使得所述第一裸片的隆起焊块与所述第二裸片的对应的隆起焊块对准。
20.如权利要求17所述的方法,进一步包括:
用绝缘材料填充所述第一裸片与所述第二裸片之间的空间;以及
将所述第一裸片和第二裸片包封在封装材料中。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10461799B2 (en) 2012-11-08 2019-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated transmitter and receiver front end module, transceiver, and related method
US10305015B1 (en) 2017-11-30 2019-05-28 International Business Machines Corporation Low loss architecture for superconducting qubit circuits
US10263170B1 (en) 2017-11-30 2019-04-16 International Business Machines Corporation Bumped resonator structure
US11302611B2 (en) * 2018-11-28 2022-04-12 Texas Instruments Incorporated Semiconductor package with top circuit and an IC with a gap over the IC
FR3127632A1 (fr) * 2021-09-28 2023-03-31 Commissariat A L'energie Atomique Et Aux Energies Alternatives Circuit intégré à puces superposées et connexion capacitive
US20230198468A1 (en) * 2021-12-21 2023-06-22 Vinayak Honkote Resonant rotary clocking for synchronized clock signals
CN116886046B (zh) * 2023-09-07 2023-11-17 南京米乐为微电子科技有限公司 一种压控振荡电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1671037A (zh) * 2004-08-04 2005-09-21 威盛电子股份有限公司 对称化压控振荡器系统
CN101399543A (zh) * 2008-09-19 2009-04-01 广州逸锋电子科技有限公司 高频电压控制振荡器
US20120049334A1 (en) * 2010-08-27 2012-03-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
US20130157594A1 (en) * 2011-12-16 2013-06-20 Skyworks Solutions, Inc. Circuits and methods for increasing output frequency of an lc oscillator
TW201427269A (zh) * 2012-12-28 2014-07-01 Ind Tech Res Inst 壓控振盪電路結構
US8941247B1 (en) * 2006-06-15 2015-01-27 Sitime Corporation Stacked die package for MEMS resonator system

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2600215B1 (fr) * 1986-06-13 1988-08-19 Thomson Csf Oscillateur doubleur de frequence, fonctionnant en hyperfrequences
US5087896A (en) 1991-01-16 1992-02-11 Hughes Aircraft Company Flip-chip MMIC oscillator assembly with off-chip coplanar waveguide resonant inductor
US5153600A (en) 1991-07-01 1992-10-06 Ball Corporation Multiple-frequency stacked microstrip antenna
US5291061A (en) 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5942950A (en) 1997-05-12 1999-08-24 Ail Systems, Inc. Varactor tuned strip line resonator and VCO using same
US6191933B1 (en) * 1998-01-07 2001-02-20 Tdk Corporation Ceramic capacitor
US6778041B2 (en) 1998-06-02 2004-08-17 Matsushita Electric Industrial Co., Ltd. Millimeter wave module and radio apparatus
KR100313952B1 (ko) 1998-08-20 2002-11-23 엘지.필립스 엘시디 주식회사 멀티도메인 액정표시소자
US6550664B2 (en) 2000-12-09 2003-04-22 Agilent Technologies, Inc. Mounting film bulk acoustic resonators in microwave packages using flip chip bonding technology
US6466099B2 (en) 2001-01-03 2002-10-15 Motorola, Inc. Voltage controlled oscillator (VCO) in colpitts configuration
US6472747B2 (en) 2001-03-02 2002-10-29 Qualcomm Incorporated Mixed analog and digital integrated circuits
US6906596B2 (en) * 2002-09-25 2005-06-14 Renesas Technology Corp. Oscillation circuit and a communication semiconductor integrated circuit
DE102004037818B4 (de) 2004-08-04 2022-02-17 Snaptrack, Inc. Filteranordnung mit zwei Volumenwellenresonatoren
DE102004063541A1 (de) 2004-12-30 2006-07-13 Robert Bosch Gmbh Antennenanordnung für einen Radar-Transceiver
DE102005042789B4 (de) * 2005-09-08 2008-04-03 Infineon Technologies Ag Schwingkreis und Oszillator mit Schwingkreis
US20070132520A1 (en) * 2005-12-08 2007-06-14 Sirific Wireless Corporation Method for voltage controlled oscillator yield enhancement
KR100715119B1 (ko) * 2006-02-08 2007-05-10 연세대학교 산학협력단 차동신호를 얻기 위한 푸쉬-푸쉬 전압조정발진기
US8058934B2 (en) * 2009-06-03 2011-11-15 Qualcomm Incorporated Apparatus and method for frequency generation
GB2476692A (en) 2009-12-31 2011-07-06 Samsung Electro Mech A compact duplexer comprising a pair of stacked flip-chip bonded acoustic wave filters
JP5494214B2 (ja) * 2010-05-14 2014-05-14 ルネサスエレクトロニクス株式会社 半導体装置
JP2013102356A (ja) 2011-11-08 2013-05-23 Panasonic Corp 無線装置およびその製造方法
US8866291B2 (en) 2012-02-10 2014-10-21 Raytheon Company Flip-chip mounted microstrip monolithic microwave integrated circuits (MMICs)
US9337138B1 (en) * 2012-03-09 2016-05-10 Xilinx, Inc. Capacitors within an interposer coupled to supply and ground planes of a substrate
US8957738B1 (en) * 2012-10-18 2015-02-17 Hittite Microwave Corporation Voltage controlled oscillator
EP2974012A4 (en) * 2013-03-15 2016-11-23 Wispry Inc DIVIDING SYSTEMS, DEVICES AND METHOD
CN104218279B (zh) 2014-09-02 2017-04-19 电子科技大学 基于ltcc的新型双模带通滤波器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1671037A (zh) * 2004-08-04 2005-09-21 威盛电子股份有限公司 对称化压控振荡器系统
US8941247B1 (en) * 2006-06-15 2015-01-27 Sitime Corporation Stacked die package for MEMS resonator system
CN101399543A (zh) * 2008-09-19 2009-04-01 广州逸锋电子科技有限公司 高频电压控制振荡器
US20120049334A1 (en) * 2010-08-27 2012-03-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
US20130157594A1 (en) * 2011-12-16 2013-06-20 Skyworks Solutions, Inc. Circuits and methods for increasing output frequency of an lc oscillator
TW201427269A (zh) * 2012-12-28 2014-07-01 Ind Tech Res Inst 壓控振盪電路結構

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