CN106252316A - 连接结构及其制造方法 - Google Patents
连接结构及其制造方法 Download PDFInfo
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- CN106252316A CN106252316A CN201510607154.1A CN201510607154A CN106252316A CN 106252316 A CN106252316 A CN 106252316A CN 201510607154 A CN201510607154 A CN 201510607154A CN 106252316 A CN106252316 A CN 106252316A
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- attachment structure
- passivation layer
- opening
- metal level
- conductive structure
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Abstract
本发明公开了一种连接结构及其制造方法。该连接结构包含半导体基板、金属层、钝化层以及导电结构。金属层位于半导体基板的上方。钝化层位于金属层的上方,且包含一个开口。导电结构具有图案化表面结构,图案化表面结构通过钝化层的开口与金属层接触。借此,本发明的连接结构及其制造方法,其中连接结构的图案化表面结构,可改善在回焊期间的晶片翘曲,以避免晶片破裂并增加可靠性,还降低整体的翘曲级。
Description
技术领域
本发明涉及一种半导体结构及其制造方法,特别是涉及一种连接结构及其制造方法。
背景技术
凸块(Bump)为覆晶封装(Flip Chip Package)结构中用于连接基板与晶片的重要元件。覆晶封装结构通常使用凸块作为媒介,以机械性或导电性的连接基板与晶片。由于凸块是基板与晶片之间连接的关键,因此凸块的可靠性会影响整体覆晶封装结构的操作。封装的目的是为了保护经过多道工艺的晶片,并使封装晶片附着至印刷电路板上。无论如何决不允许封装工艺对晶片所产生的任何损坏。
回焊(Reflow)工艺为连接表面安装元件至电路板及/或金属衬垫的最常规方法。为了较好的可靠性及连接至金属衬垫,可借由回焊工艺来处理凸块。在回焊工艺中,电路板与凸块全部的组装(assembly)在热处理下进行,例如借由退火(annealing)。热处理可借由将所述组装通过回焊炉(Reflow oven)或在红外线灯泡下以完成。据此,改善凸块在封装工艺中的可靠度是必要的。
发明内容
本发明的目的在于提供一种连接结构及其制造方法,其具有图案化表面结构,可改善在回焊期间的晶片翘曲,以避免晶片破裂并增加可靠性,还降低整体的翘曲级。
本发明提供一种连接结构。该连接结构包含半导体基板、金属层、钝化层以及导电结构。金属层位于半导体基板的上方。钝化层位于金属层的上方,且包含一个开口。导电结构具有图案化表面结构,图案化表面结构通过钝化层的开口与金属层接触。
在本发明各种实施方式中,导电结构包含凸块(bump)或焊球(solderingball)。
在本发明各种实施方式中,导电结构的图案化表面结构包含金属部分及支撑部分。
在本发明各种实施方式中,连接结构还包含凸块下方金属(under-bumpmetallurgy,UBM)层,其设置于金属层及导电结构之间。
在本发明各种实施方式中,图案化表面结构的支撑部分为网状结构、多个规则排列柱子或同心圆柱。
在本发明各种实施方式中,所述柱子具有一个剖面包含多边形、圆形或椭圆形。
在本发明各种实施方式中,图案化表面结构的支撑部分的材料包含至少一种无机材料、至少一种有机材料或其组合;而无机材料为二氧化硅(silicondioxide)、氮化硅(silicon nitride)、二氧化钛(titanium dioxide)或氧化铝(aluminumoxide),有机材料为聚亚酰胺(polyimide)或聚苯恶唑(polybenzoxazole,PBO)。
在本发明各种实施方式中,图案化表面结构的金属部分的材料包含锡(Sn)、银(Ag)、铜(Cu)、金(Au)、合金或其组合。
在本发明各种实施方式中,凸块下方金属层的材料包含氮化钛(TiN)、钛(Ti)、氮化钨(WN)、锡(Sn)、银(Ag)、铜(Cu)、金(Au)、镍(Ni)、合金或其组合。
在本发明各种实施方式中,钝化层的开口具有一种形状,该形状包含多边形、圆形或椭圆形。
本发明提供一种制造连接结构的方法,且其方法包含下列步骤。在半导体基板的上方形成金属层。在金属层的上方形成钝化层。凹槽化钝化层以形成开口。形成导电结构,且其具有图案化表面结构,而图案化表面结构通过钝化层的开口与金属层接触。
在本发明各种实施方式中,凹槽化钝化层以形成开口的工艺包含下列步骤。使用光阻至钝化层上。在钝化层进行微影(lithography)及蚀刻(etching)以形成开口,且开口中具有钝化层的剩余部分以作为开口中的支撑部分。
在本发明各种实施方式中,形成导电结构的工艺包含下列步骤。将金属填入开口。所述金属进行回焊(reflow)以形成导电结构。
在本发明各种实施方式中,在凹槽化钝化层之后,以及形成导电结构之前,所述方法还包含形成支撑部分于开口中。
在本发明各种实施方式中,形成导电结构的工艺包含下列步骤。将金属填入开口。所述金属进行回焊以形成导电结构。
在本发明各种实施方式中,形成导电结构的工艺包含下列步骤。形成导电结构,且其具有图案化表面结构,而图案化表面结构具有金属部分及支撑部分。借由钝化层的开口,以连接导电结构的图案化表面结构与金属层。
在本发明各种实施方式中,在凹槽化该钝化层之后,以及形成该导电结构之前,所述方法还包含在金属层与导电结构之间形成凸块下方金属层。
在本发明各种实施方式中,支撑部分的材料包含至少一种无机材料、至少一种有机材料或其组合;而无机材料为二氧化硅(silicon dioxide)、氮化硅(silicon nitride)、二氧化钛(titanium dioxide)或氧化铝(aluminum oxide),有机材料为聚亚酰胺(polyimide)或聚苯恶唑(polybenzoxazole,PBO)。
在本发明各种实施方式中,图案化表面结构的金属部分的材料包含锡(Sn)、银(Ag)、铜(Cu)、金(Au)、合金或其组合。
在本发明各种实施方式中,凸块下方金属层的材料包含氮化钛(TiN)、钛(Ti)、氮化钨(WN)、锡(Sn)、银(Ag)、铜(Cu)、金(Au)、镍(Ni)、合金或其组合。
与现有技术相比,本发明具有如下有益效果:本发明的连接结构及其制造方法,其具有图案化表面结构,可改善在回焊期间的晶片翘曲,以避免晶片破裂并增加可靠性,还降低整体的翘曲级。
参照以下的说明以及权利要求,可更加理解本发明的特征、实施例以及优点。
应当理解的是,以上的一般叙述以及以下的详细叙述是实例,并旨在对所要求保护发明提供进一步的解释。
附图说明
本发明内容的实施方式可从下面的详细描述并结合参阅附图得到最佳的理解。要强调的是,按照在业界的标准实务做法,各种特征不一定是按比例绘制。事实上,为了清楚的讨论各种特征的尺寸可任意放大或缩小。
图1是绘示依据本发明多个实施方式的一种连接结构的剖面图;
图2A至图2C是绘示依据本发明多个实施方式的沿着图1中的A至A’线的仰视图;
图3是绘示依据本发明多个实施方式的一种连接结构的剖面图;
图4A至图4C是绘示依据本发明多个实施方式的一种连接结构制造过程中的中间阶段剖面图;
图5A至图5D是绘示依据本发明多个实施方式的一种连接结构制造过程中的中间阶段剖面图;
图6A至图6D是绘示依据本发明多个实施方式的一种连接结构制造过程中的中间阶段剖面图;以及
图7A至图7D是绘示依据本发明多个实施方式的一种连接结构制造过程中的中间阶段剖面图。
具体实施方式
之后将以示例图式以详细描述本发明的各种实施方式,且在图式和说明书中使用相同的元件符号以指代相同或相似的部分。
以下将以图式公开本发明的多个实施方式,为明确说明起见,许多实务上的细节将在以下叙述中一并说明。然而,应了解到,这些实务上的细节不应用以限制本发明。也就是说,在本发明部分实施方式中,这些实务上的细节是非必要的。此外,为简化图式起见,一些现有惯用的结构与元件在图式中将以简单示意的方式绘示。
由于前述的问题,凸块成为基板与晶片之间连接的关键,因此凸块的可靠性会影响整体覆晶封装结构的操作。为了较好的可靠性及连接至金属衬垫,可借由回焊工艺来处理凸块。然而,在回焊期间,凸块时常引起晶片翘曲。据此,极需一种改善的连接结构及其制造方法。
本发明提供一种连接结构及其制造方法。该连接结构具有图案化表面结构,其可改善在回焊期间的晶片翘曲。因此,借由本发明所提供的连接结构可避免晶片破裂(crack)且增加可靠性,还降低整体的翘曲级(warpage level)。
请参照图1。根据本发明多个实施方式,图1为一种连接结构的剖面图。如图1所示,连接结构100包含半导体基板110、金属层120、钝化层130及导电结构140。半导体基板110上方具有金属层120位于其上。具有开口的钝化层130位于金属层120的上方。而导电结构140具有图案化表面结构142,导电结构140的图案化表面结构142经由钝化层130的开口与金属层120接触。导电结构140的图案化表面结构142包含金属部分142a与支撑部分142b。在一些实施方式中,值得注意的是,图案化表面结构142的支撑部分142b可能来自钝化层130的剩余部份、来自新加入到钝化层130开口中的材料、或借由直接形成于导电结构140中的方式。关于上述得到支撑部分的选择将于之后再详细说明(在图4A至图6D的介绍中)。
在一些实施方式中,导电结构140包含凸块(bump)或焊球(soldering ball)。根据一些实施方式,钝化层的开口具有一种形状,该形状包含多边形、圆形或椭圆形。当开口的形状为多边形时,所述多边形的实例包含,但不限于,三角形、矩形、梯形、平行四边形、菱形、五边形或六边形。在一些实施方式中,导电结构140的支撑部分142b的材料包含,但不限于,至少一种无机材料如二氧化硅(silicon dioxide)、氮化硅(silicon nitride)、二氧化钛(titaniumdioxide)、氧化铝(aluminum oxide),或至少一种有机材料如聚亚酰胺(polyimide)、聚苯恶唑(polybenzoxazole,PBO),或其组合。在一些实施方式中,图案化表面结构142的金属部分142a的材料为锡(Sn)、银(Ag)、铜(Cu)、金(Au)、合金(alloy)或其组合。在一些实施方式中,钝化层130的材料为至少一种无机材料如二氧化硅(silicon dioxide)、氮化硅(silicon nitride)、二氧化钛(titanium dioxide)、氧化铝(aluminum oxide),或至少一种有机材料如聚亚酰胺(polyimide)、聚苯恶唑(polybenzoxazole,PBO),或其组合。
本发明提供一种连接结构100具有导电结构140,其经由图案化表面结构142与金属层120接触。进一步地,图案化表面结构142的支撑部分142b可于回焊工艺中减少应力(stress)以改善晶片翘曲。因此,连接结构100中的导电结构140的图案化表面结构142可避免晶片破裂且提升可靠性,还降低整体的翘曲级(warpage level)。
根据本发明多个实施方式,图2A至图2C为沿着图1中的A至A’线的仰视图。参照图2A,在一实施方式中,图案化表面结构142的支撑部分142b为网状结构。根据另一实施方式,图2B绘示出图案化表面结构142的支撑部分142b为多个规则排列柱子。举例而言,所述柱子具有剖面,该剖面包含多边形、圆形或椭圆形。此外,举例来说多边形包含,但不限于三角形、矩形、梯形、平行四边形、菱形、五角形或六角形。图2B绘示出具有圆形剖面的柱子。在一些实施方式中,图案化表面结构142的支撑部分142b为一个或多个同心圆柱。图2C绘示出图案化表面结构142的支撑部分142b为两个同心圆柱。
请参照图3。根据本发明多个实施方式,图3为一种连接结构的剖面图。如图3所示,连接结构200包含半导体基板210、金属层220、钝化层230、导电结构240及凸块下方金属(under-bump metallurgy,UBM)层250。半导体基板210上方具有金属层220位于其上。具有开口的钝化层230位于金属层220的上方。而导电结构240具有图案化表面结构242,导电结构240的图案化表面结构242经由钝化层230的开口与金属层220接触。导电结构240的图案化表面结构242包含金属部分242a与支撑部分242b。凸块下方金属层250设置于金属层220与导电结构240之间,且凸块下方金属层250的材料例如包含,但不限于氮化钛(TiN)、钛(Ti)、氮化钨(WN)、锡(Sn)、银(Ag)、铜(Cu)、金(Au)、镍(Ni)、合金或其组合。然而,图3绘示出的实施例是对应于图1所示的实施例,所以其详细说明便不在此重复。因此,根据一些实施方式,可利用如前述图1的说明所提及的相似的材料及任何细节。
请参照图4A至图4C。根据本发明多个实施方式,图4A至图4C为一种连接结构制造过程中的中间阶段剖面图。
本发明一些实施方式提供一种制造如图4C所示的连接结构300的方法。首先参照图4A,金属层320在半导体基板310的上方形成,而后钝化层330在金属层320的上方形成。接着,如图4B所示,凹槽化钝化层330以形成开口332。详细说明如下,使用光阻(未显示)至钝化层330上。在钝化层330进行微影(lithography)与蚀刻(etching)以形成开口332,且开口332中具有钝化层330的剩余部分以作为开口332中的支撑部份334。继续参照图4C,将金属填入图4B所示的开口332中,而后回焊金属以形成具有图案化表面结构342的导电结构340。图案化表面结构342包含金属部分342a与支撑部份334,且其会通过图4B所示的钝化层330的开口332与金属层320接触。详细描述如下,举例而言,将金属填入图4B所示的开口332中的方法包含,但不限于电镀(plating)、热蒸镀(thermal evaporation)或溅镀(sputtering)。在一些实施方式中,借由通过回焊炉(reflow oven)或在红外线灯泡下进行退火(annealing)以回焊金属。
继续参照图4A至图4C。在一些实施方式中,支撑部份334的材料与钝化层330相同,其为至少一种无机材料如二氧化硅(silicon dioxide)、氮化硅(silicon nitride)、二氧化钛(titanium dioxide)、氧化铝(aluminum oxide),或至少一种有机材料如聚亚酰胺(polyimide)、聚苯恶唑(polybenzoxazole,PBO),或其组合。根据一些实施方式,图案化表面结构342的金属部分342a包含,但不限于锡(Sn)、银(Ag)、铜(Cu)、金(Au)、合金(alloy)或其组合。
请参照图5A至图5D。根据本发明多个实施方式,图5A至图5D为一种连接结构制造过程中的中间阶段剖面图。
本发明一些实施方式提供一种制造如图5D所示的连接结构400的方法。首先参照图5A,金属层420在半导体基板410的上方形成,而后钝化层430在金属层420的上方形成。接着,如图5B所示,凹槽化钝化层430以形成开口432。详细说明如下,使用光阻(未显示)至钝化层430上。在钝化层430进行微影(lithography)与蚀刻(etching)以形成开口432。现在参照图5C,支撑部分440在图5B所示的开口432中形成。根据一些实施方式,支撑部分440是以介电材料所制成,举例而言,介电材料如二氧化硅(silicon dioxide)、氮化硅(silicon nitride)、二氧化钛(titanium dioxide)或其组合。接着参照图5D,将金属填入图5B所示的开口432中,而后回焊金属以形成具有图案化表面结构452的导电结构450。图案化表面结构452包含金属部分452a与支撑部份440,且其会通过图5B所示的钝化层430的开口432与金属层420接触。详细描述如下,举例而言,将金属填入图5B所示的开口432中的方法包含,但不限于电镀(plating)、热蒸镀(thermal evaporation)或溅镀(sputtering)。在一些实施方式中,借由通过回焊炉(reflow oven)或在红外线灯泡下进行退火(annealing)以回焊金属。此外,根据一些实施方式,可利用如前述图4A至图4C的说明所提及的相似的材料。
请参照图6A至图6D。根据本发明多个实施方式,图6A至图6D为一种连接结构制造过程中的中间阶段剖面图。
本发明一些实施方式提供一种制造如图6D所示的连接结构500的方法。首先参照图6A,金属层520在半导体基板510的上方形成,而后钝化层530在金属层520的上方形成。接着,如图6B所示,凹槽化钝化层530以形成开口532。详细说明如下,使用光阻(未显示)至钝化层530上。在钝化层530进行微影(lithography)与蚀刻(etching)以形成开口532。参照图6C,单独形成的导电结构540具有包含金属部分542a与支撑部分542b的图案化表面结构542。接着参照图6D,导电结构540的图案化表面结构542通过图6B所示的钝化层530的开口532与金属层520接触。此外,根据一些实施方式,可利用如前述图4A至图4C的说明所提及的相似的材料。
根据一些实施方式,在凹槽化钝化层之后,以及形成导电结构之前,所述方法还包含在金属层及导电结构之间形成凸块下方金属(under-bumpmetallurgy,UBM)层。举例而言,形成凸块下方金属层的方法包含,但不限于图7A至图7D所示的工艺。
请参照图7A至图7D。根据本发明多个实施方式,图7A至图7D为一种连接结构制造过程中的中间阶段剖面图。
本发明一些实施方式提供一种制造如图7D所示的连接结构600的方法。首先参照图7A,金属层620在半导体基板610的上方形成,而后钝化层630在金属层620的上方形成。接着,如图6B所示,凹槽化钝化层630以形成开口632。详细说明如下,使用光阻(未显示)至钝化层630上。在钝化层630进行微影(lithography)与蚀刻(etching)以形成开口632,且开口632中具有钝化层630的剩余部分以作为开口632中的支撑部份634。具有支撑部分634的开口632,其具有一个上表面。接着参照图7C,凸块下方金属层640保形地在开口632的上表面上形成。随后参照图7D,将金属填入图7B所示的开口632中,而后回焊金属以形成具有图案化表面结构652的导电结构650。图案化表面结构652包含金属部分652a与支撑部份634,且其会通过图7B所示的钝化层630的开口632与金属层620接触。详细描述如下,举例而言,将金属填入图7B所示的开口632中的方法包含,但不限于电镀(plating)、热蒸镀(thermalevaporation)或溅镀(sputtering)。在一些实施方式中,借由通过回焊炉(reflowoven)或在红外线灯泡下进行退火(annealing)以回焊金属。此外,根据一些实施方式,可利用如前述图4A至图4C的说明所提及的相似的材料。
由上述本发明实施方式可知,本发明优于现有的连接结构与其工艺,并总结此些优点如下。凸块在回焊期间时常引起晶片翘曲。替代地,本发明提供一种改善的连接结构及其制造方法。所述连接结构的导电结构可通过图案化表面结构与金属层接触。此外,图案化表面结构包含金属部分与支撑部分。支撑部分在回焊期间可降低应力(stress),进而改善晶片翘曲的问题。总结前述重点,在连接结构中的导电结构的图案化表面结构在回焊期间可改善晶片翘曲,以避免晶片破裂(crack),并增加其可靠性,还降低整体的翘曲级(warpagelevel)。
本发明已经相当详细地描述某些实施方式,但其他的实施方式也为可能的。因此,权利要求的精神和范筹不应限于本文所描述的实施方式。
虽然本发明已经以实施方式公开如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作各种变动与润饰,因此本发明的保护范围当视权利要求所界定者为准。
Claims (20)
1.一种连接结构,其特征在于,所述连接结构包含:
半导体基板;
金属层,其在所述半导体基板的上方;
钝化层,其在所述金属层的上方,且所述钝化层包含开口;以及
导电结构,其具有图案化表面结构,所述图案化表面结构通过所述钝化层的所述开口与所述金属层接触。
2.如权利要求1所述的连接结构,其特征在于,所述导电结构包含凸块或焊球。
3.如权利要求1所述的连接结构,其特征在于,所述导电结构的所述图案化表面结构包含金属部分及支撑部分。
4.如权利要求1所述的连接结构,其特征在于,所述连接结构还包含凸块下方金属层,其设置于所述金属层及所述导电结构之间。
5.如权利要求3所述的连接结构,其特征在于,所述图案化表面结构的所述支撑部分为网状结构、多个规则排列柱子或同心圆柱。
6.如权利要求5所述的连接结构,其特征在于,所述柱子具有剖面,所述剖面包含多边形、圆形或椭圆形。
7.如权利要求3所述的连接结构,其特征在于,所述图案化表面结构的所述支撑部分的材料包含至少一种无机材料、至少一种有机材料或其组合;而所述无机材料为二氧化硅、氮化硅、二氧化钛或氧化铝,所述有机材料为聚亚酰胺或聚苯恶唑。
8.如权利要求3所述的连接结构,其特征在于,所述图案化表面结构的所述金属部分的材料包含锡、银、铜、金、合金或其组合。
9.如权利要求4所述的连接结构,其特征在于,所述凸块下方金属层的材料包含氮化钛、钛、氮化钨、锡、银、铜、金、镍、合金或其组合。
10.如权利要求1所述的连接结构,其特征在于,所述钝化层的所述开口具有形状,所述形状包含多边形、圆形或椭圆形。
11.一种制造连接结构的方法,其特征在于,所述制造连接结构的方法包含:
在半导体基板的上方形成金属层;
在所述金属层的上方形成钝化层:
凹槽化所述钝化层以形成开口;以及
形成导电结构,且所述导电结构具有图案化表面结构,而所述图案化表面结构通过所述钝化层的所述开口与所述金属层接触。
12.如权利要求11所述的制造连接结构的方法,其特征在于,凹槽化所述钝化层以形成所述开口的工艺步骤,包含:
使用光阻至所述钝化层上;以及
进行微影及蚀刻所述钝化层以形成所述开口,且所述开口中具有所述钝化层的剩余部分以作为所述开口中的支撑部分。
13.如权利要求12所述的制造连接结构的方法,其特征在于,形成所述导电结构的工艺步骤,包含:
将金属填入所述开口;以及
回焊所述金属以形成所述导电结构。
14.如权利要求11所述的制造连接结构的方法,其特征在于,在凹槽化所述钝化层之后与形成所述导电结构之前,所述制造连接结构的方法还包含:
形成支撑部分于所述开口中。
15.如权利要求14所述的制造连接结构的方法,其特征在于,形成所述导电结构,包含:
将金属填入所述开口;以及
回焊所述金属以形成所述导电结构。
16.如权利要求11所述的制造连接结构的方法,其特征在于,形成所述导电结构的工艺步骤,包含:
形成所述导电结构,且所述导电结构具有所述图案化表面结构,而所述图案化表面结构具有金属部分及支撑部分;以及
借由所述钝化层的所述开口,以连接所述导电结构的所述图案化表面结构与所述金属层。
17.如权利要求11所述的制造连接结构的方法,其特征在于,在凹槽化所述钝化层之后与形成所述导电结构之前,所述制造连接结构的方法还包含:
在所述金属层与所述导电结构之间形成凸块下方金属层。
18.如权利要求14所述的制造连接结构的方法,其特征在于,所述支撑部分的材料包含至少一种无机材料、至少一种有机材料或其组合;而所述无机材料为二氧化硅、氮化硅、二氧化钛或氧化铝,所述有机材料为聚亚酰胺或聚苯恶唑。
19.如权利要求16所述的制造连接结构的方法,其特征在于,所述图案化表面结构的所述金属部分的材料包含锡、银、铜、金、合金或其组合。
20.如权利要求17所述的制造连接结构的方法,其特征在于,所述凸块下方金属层的材料包含氮化钛、钛、氮化钨、锡、银、铜、金、镍、合金或其组合。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108321137A (zh) * | 2017-01-17 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制作方法、电子装置 |
WO2020192347A1 (zh) * | 2019-03-27 | 2020-10-01 | 京东方科技集团股份有限公司 | 驱动背板、其制作方法及显示面板 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10008461B2 (en) | 2015-06-05 | 2018-06-26 | Micron Technology, Inc. | Semiconductor structure having a patterned surface structure and semiconductor chips including such structures |
KR102658923B1 (ko) | 2016-09-12 | 2024-04-18 | 삼성전자주식회사 | 반도체 장치 및 반도체 패키지 |
JP2020031081A (ja) * | 2018-08-20 | 2020-02-27 | 新日本無線株式会社 | 半導体装置 |
CN111128770B (zh) * | 2019-12-16 | 2021-08-24 | 华虹半导体(无锡)有限公司 | 铝垫的形成方法以及包含铝垫的器件 |
WO2024116844A1 (ja) * | 2022-12-02 | 2024-06-06 | パナソニックIpマネジメント株式会社 | 半導体装置及びその製造方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1416165A (zh) * | 2001-10-31 | 2003-05-07 | 夏普公司 | 半导体器件及其制作工艺和检测方法 |
US20070075423A1 (en) * | 2005-09-30 | 2007-04-05 | Siliconware Precision Industries Co., Ltd. | Semiconductor element with conductive bumps and fabrication method thereof |
US20090079070A1 (en) * | 2007-09-20 | 2009-03-26 | Stats Chippac, Ltd. | Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps |
US20090283903A1 (en) * | 2005-12-02 | 2009-11-19 | Nepes Corporation | Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same |
US20100013094A1 (en) * | 2008-07-15 | 2010-01-21 | Samsung Electronics Co., Ltd | Semiconductor package and methods of manufacturing the same |
US20110266670A1 (en) * | 2010-04-30 | 2011-11-03 | Luke England | Wafer level chip scale package with annular reinforcement structure |
CN102969344A (zh) * | 2012-11-08 | 2013-03-13 | 南通富士通微电子股份有限公司 | 半导体器件 |
CN103474402A (zh) * | 2013-09-29 | 2013-12-25 | 南通富士通微电子股份有限公司 | 半导体封装结构 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6417087B1 (en) | 1999-12-16 | 2002-07-09 | Agere Systems Guardian Corp. | Process for forming a dual damascene bond pad structure over active circuitry |
US7096581B2 (en) * | 2002-03-06 | 2006-08-29 | Stmicroelectronics, Inc. | Method for providing a redistribution metal layer in an integrated circuit |
TWI223359B (en) | 2003-12-25 | 2004-11-01 | Advanced Semiconductor Eng | Package structure with enhanced solder bump and the process thereof |
US7364998B2 (en) * | 2005-07-21 | 2008-04-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming high reliability bump structure |
CN1917196A (zh) | 2005-08-19 | 2007-02-21 | 南茂科技股份有限公司 | 柱格阵列封装构造及其电子装置 |
KR101288790B1 (ko) * | 2005-09-27 | 2013-07-29 | 에이저 시스템즈 엘엘시 | 플립 칩 반도체 디바이스들을 위한 솔더 범프 구조 및 이의제조 방법 |
US7952206B2 (en) * | 2005-09-27 | 2011-05-31 | Agere Systems Inc. | Solder bump structure for flip chip semiconductor devices and method of manufacture therefore |
US7727876B2 (en) * | 2006-12-21 | 2010-06-01 | Stats Chippac, Ltd. | Semiconductor device and method of protecting passivation layer in a solder bump process |
TW200836275A (en) * | 2007-02-16 | 2008-09-01 | Chipmos Technologies Inc | Packaging conductive structure and method for manufacturing the same |
US8723325B2 (en) * | 2009-05-06 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of forming a pad structure having enhanced reliability |
US8853853B2 (en) | 2011-07-27 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures |
US8912668B2 (en) * | 2012-03-01 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connections for chip scale packaging |
TWI463621B (zh) | 2011-11-04 | 2014-12-01 | 矽品精密工業股份有限公司 | 封裝基板結構及其製法 |
TWI502691B (zh) * | 2011-11-18 | 2015-10-01 | Chipmos Technologies Inc | 導電結構及其形成方法 |
US9385076B2 (en) * | 2011-12-07 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with bump structure on an interconncet structure |
US9761549B2 (en) * | 2012-11-08 | 2017-09-12 | Tongfu Microelectronics Co., Ltd. | Semiconductor device and fabrication method |
US10008461B2 (en) * | 2015-06-05 | 2018-06-26 | Micron Technology, Inc. | Semiconductor structure having a patterned surface structure and semiconductor chips including such structures |
-
2015
- 2015-06-05 US US14/731,426 patent/US10008461B2/en active Active
- 2015-09-18 TW TW104130982A patent/TWI645529B/zh active
- 2015-09-22 CN CN202010908335.9A patent/CN111916417A/zh active Pending
- 2015-09-22 CN CN201510607154.1A patent/CN106252316A/zh active Pending
-
2018
- 2018-04-30 US US15/966,447 patent/US10354966B2/en active Active
-
2019
- 2019-05-16 US US16/414,440 patent/US10950564B2/en active Active
-
2021
- 2021-03-11 US US17/198,447 patent/US11640948B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1416165A (zh) * | 2001-10-31 | 2003-05-07 | 夏普公司 | 半导体器件及其制作工艺和检测方法 |
US20070075423A1 (en) * | 2005-09-30 | 2007-04-05 | Siliconware Precision Industries Co., Ltd. | Semiconductor element with conductive bumps and fabrication method thereof |
US20090283903A1 (en) * | 2005-12-02 | 2009-11-19 | Nepes Corporation | Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same |
US20090079070A1 (en) * | 2007-09-20 | 2009-03-26 | Stats Chippac, Ltd. | Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps |
US20100013094A1 (en) * | 2008-07-15 | 2010-01-21 | Samsung Electronics Co., Ltd | Semiconductor package and methods of manufacturing the same |
US20110266670A1 (en) * | 2010-04-30 | 2011-11-03 | Luke England | Wafer level chip scale package with annular reinforcement structure |
CN102969344A (zh) * | 2012-11-08 | 2013-03-13 | 南通富士通微电子股份有限公司 | 半导体器件 |
CN103474402A (zh) * | 2013-09-29 | 2013-12-25 | 南通富士通微电子股份有限公司 | 半导体封装结构 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108321137A (zh) * | 2017-01-17 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制作方法、电子装置 |
WO2020192347A1 (zh) * | 2019-03-27 | 2020-10-01 | 京东方科技集团股份有限公司 | 驱动背板、其制作方法及显示面板 |
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US20190273058A1 (en) | 2019-09-05 |
US10950564B2 (en) | 2021-03-16 |
US10008461B2 (en) | 2018-06-26 |
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