TWI645529B - 具有圖案化表面結構的半導體結構及包括該等結構的半導體晶片 - Google Patents

具有圖案化表面結構的半導體結構及包括該等結構的半導體晶片 Download PDF

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TWI645529B
TWI645529B TW104130982A TW104130982A TWI645529B TW I645529 B TWI645529 B TW I645529B TW 104130982 A TW104130982 A TW 104130982A TW 104130982 A TW104130982 A TW 104130982A TW I645529 B TWI645529 B TW I645529B
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Taiwan
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patterned surface
passivation layer
surface structure
opening
semiconductor
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TW104130982A
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TW201644028A (zh
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施信益
吳鐵將
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美商美光科技公司
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Abstract

本發明提供一種連接結構及其製造方法。所述連接結構包含半導體基板、金屬層、鈍化層以及導電結構。金屬層位於半導體基板之上方。鈍化層位於金屬層之上方，且包含一個開口。導電結構具有圖案化表面結構，圖案化表面結構透過鈍化層之開口與金屬層接觸。

Description

具有圖案化表面結構的半導體結構及包括該等結 構的半導體晶片
本發明是關於一種半導體結構及其製造方法，特別是有關於一種連接結構及其製造方法。
凸塊(Bump)為覆晶封裝(Flip Chip Package)結構中用於連接基板與晶片的重要元件。覆晶封裝結構通常使用凸塊作為媒介，以機械性或導電性的連接基板與晶片。由於凸塊是基板與晶片之間連接的關鍵，因此凸塊的可靠性會影響整體覆晶封裝結構的操作。封裝的目的係為了保護經過多道製程的晶片，並使封裝晶片附著至印刷電路板上。無論如何決不允許封裝製程對晶片所產生的任何損壞。
回焊(Reflow)製程為連接表面安裝元件至電路板及/或金屬襯墊的最常規方法。為了較好的可靠性及連接至金屬襯墊，可藉由回焊製程來處理凸塊。在回焊製程中，電路板與凸塊全部的組裝(assembly)在熱處理下進行，例如藉由退火(annealing)。熱處理可藉由將所述組裝通過回焊爐(Reflow oven)或在紅外線燈泡下以完成。據此，改善凸塊在封裝製程中之可靠度是必要的。
本發明提供一種連接結構。所述連接結構包含半導體基板、金屬層、鈍化層以及導電結構。金屬層位於半導體基板之上方。鈍化層位於金屬層之上方，且包含一個開口。導電結構具有圖案化表面結構，圖案化表面結構透過鈍化層之開口與金屬層接觸。
在本發明各種實施方式中，導電結構包含凸塊(bump)或焊球(soldering ball)。
在本發明各種實施方式中，導電結構之圖案化表面結構包含金屬部分及支撐部分。
在本發明各種實施方式中，連接結構更包含凸塊下方金屬(under-bump metallurgy，UBM)層，其設置於金屬層及導電結構之間。
在本發明各種實施方式中，圖案化表面結構之支撐部分為網狀結構、複數個規則排列柱子或同心圓柱。
在本發明各種實施方式中，所述柱子具有一個剖面包含多邊形、圓形或橢圓形。
在本發明各種實施方式中，圖案化表面結構之支撐部分之材料包含至少一種無機材料、至少一種有機材料或其組合；而無機材料為二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、二氧化鈦(titanium dioxide)或氧化鋁(aluminum oxide)，有機材料為聚亞醯胺(polyimide)或聚苯噁唑(polybenzoxazole，PBO)。
在本發明各種實施方式中，圖案化表面結構之金屬部分之材料包含錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、合金或其組合。
在本發明各種實施方式中，凸塊下方金屬層之材料包含氮化鈦(TiN)、鈦(Ti)、氮化鎢(WN)、錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、 鎳(Ni)、合金或其組合。
在本發明各種實施方式中，鈍化層之開口具有一種形狀包含多邊形、圓形或橢圓形。
本發明提供一種製造連接結構之方法，且其方法包含下列步驟。金屬層形成於半導體基板之上方。鈍化層形成於金屬層之上方。凹槽化鈍化層以形成開口。形成導電結構，且其具有圖案化表面結構，而圖案化表面結構透過鈍化層之開口與金屬層接觸。
在本發明各種實施方式中，凹槽化鈍化層以形成開口之製程包含下列步驟。使用光阻至鈍化層上。於鈍化層進行微影(lithography)及蝕刻(etching)以形成開口，且開口中具有鈍化層之剩餘部分以作為開口中之支撐部分。
在本發明各種實施方式中，形成導電結構之製程包含下列步驟。將金屬填入開口。所述金屬進行回焊(reflow)以形成導電結構。
在本發明各種實施方式中，在凹槽化鈍化層之後，以及形成導電結構之前，所述方法更包含形成支撐部分於開口中。
在本發明各種實施方式中，形成導電結構之製程包含下列步驟。將金屬填入開口。所述金屬進行回焊以形成導電結構。
在本發明各種實施方式中，形成導電結構之製程包含下列步驟。形成導電結構，且其具有圖案化表面結構，而圖案化表面結構具有金屬部分及支撐部分。藉由鈍化層之開口，以連接導電結構之圖案化表面結構與金屬層。
在本發明各種實施方式中，於凹槽化該鈍化層之後，以及形成該導電結構之前，所述方法更包含形成凸塊下方金屬層於金屬層與導電結構之間。
在本發明各種實施方式中，支撐部分之材料包含至少一種無機材料、至少一種有機材料或其組合；而無機材料為二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、二氧化鈦(titanium dioxide)或氧化鋁(aluminum oxide)，有機材料為聚亞醯胺(polyimide)或聚苯噁唑(polybenzoxazole，PBO)。
在本發明各種實施方式中，圖案化表面結構之金屬部分之材料包含錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、合金或其組合。
在本發明各種實施方式中，凸塊下方金屬層之材料包含氮化鈦(TiN)、鈦(Ti)、氮化鎢(WN)、錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、鎳(Ni)、合金或其組合。
參照以下之說明以及所附之申請專利範圍，可更加理解本揭露之特徵、態樣以及優點。
應當理解的是，以上之一般敘述以及以下之詳細敘述係實例，並旨在對所要求保護發明提供進一步的解釋。
100‧‧‧連接結構
110‧‧‧半導體基板
120‧‧‧金屬層
130‧‧‧鈍化層
140‧‧‧導電結構
142‧‧‧圖案化表面結構
142a‧‧‧金屬部分
142b‧‧‧支撐部分
200‧‧‧連接結構
210‧‧‧半導體基板
220‧‧‧金屬層
230‧‧‧鈍化層
240‧‧‧導電結構
242‧‧‧圖案化表面結構
242a‧‧‧金屬部分
242b‧‧‧支撐部分
250‧‧‧凸塊下方金屬(under-bump metallurgy，UBM)層
300‧‧‧連接結構
310‧‧‧半導體基板
320‧‧‧金屬層
330‧‧‧鈍化層
332‧‧‧開口
334‧‧‧支撐部分
340‧‧‧導電結構
342‧‧‧圖案化表面結構
342a‧‧‧金屬部分
400‧‧‧連接結構
410‧‧‧半導體基板
420‧‧‧金屬層
430‧‧‧鈍化層
432‧‧‧開口
440‧‧‧支撐部分
450‧‧‧導電結構
452‧‧‧圖案化表面結構
452a‧‧‧金屬部分
500‧‧‧連接結構
510‧‧‧半導體基板
520‧‧‧金屬層
530‧‧‧鈍化層
532‧‧‧開口
540‧‧‧導電結構
542‧‧‧圖案化表面結構
542a‧‧‧金屬部分
542b‧‧‧支撐部分
600‧‧‧連接結構
610‧‧‧半導體基板
620‧‧‧金屬層
630‧‧‧鈍化層
632‧‧‧開口
634‧‧‧支撐部分
640‧‧‧凸塊下方金屬(under-bump metallurgy，UBM)層
650‧‧‧導電結構
652‧‧‧圖案化表面結構
652a‧‧‧金屬部分
A-A’‧‧‧剖線
本發明內容的實施方式可從下面的詳細描述並結合參閱附圖得到最佳的理解。要強調的是，按照在業界的標準實務做法，各種特徵不一定是按比例繪製。事實上，為了清楚的討論各種特徵的尺寸可任意放大或縮小。
根據本發明多個實施方式，第1圖為一種連接結構之剖面圖；根據本發明多個實施方式，第2A-2C圖為沿著第1圖中之A-A’線之仰視圖；根據本發明多個實施方式，第3圖為一種連接結構之剖面圖； 根據本發明多個實施方式，第4A-4C圖為一種連接結構製造過程中之中間階段剖面圖；根據本發明多個實施方式，第5A-5D圖為一種連接結構製造過程中之中間階段剖面圖；根據本發明多個實施方式，第6A-6D圖為一種連接結構製造過程中之中間階段剖面圖；以及根據本發明多個實施方式，第7A-7D圖為一種連接結構製造過程中之中間階段剖面圖。
之後將以示例圖式以詳細描述本發明的各種實施方式，且在圖式和說明書中使用相同的元件符號以指代相同或相似的部分。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
由於前述之問題，凸塊成為基板與晶片之間連接的關鍵，因此凸塊的可靠性會影響整體覆晶封裝結構的操作。為了較好的可靠性及連接至金屬襯墊，可藉由回焊製程來處理凸塊。然而，在回焊期間，凸塊時常引起晶片翹曲。據此，極需一種改善的連接結構及其製造方法。
本發明提供一種連接結構及其製造方法。所述連接結構具有圖案化表面結構，其可改善在回焊期間的晶片翹曲。因此，藉由本發明所提供之連接結構可避免晶片破裂(crack)且增加可靠性，更降低整體的翹曲級(warpage level)。
請參照第1圖。根據本發明多個實施方式，第1圖為一種連接結構之剖面圖。如第1圖所示，連接結構100包含半導體基板110、金屬層120、鈍化層130及導電結構140。半導體基板110上方具有金屬層120位於其上。具有一開口之鈍化層130位於金屬層120之上方。而導電結構140具有圖案化表面結構142，導電結構140之圖案化表面結構142經由鈍化層130之開口與金屬層120接觸。導電結構140之圖案化表面結構142包含金屬部分142a與支撐部分142b。在一些實施方式中，值得注意的是，圖案化表面結構142之支撐部分142b可能來自鈍化層130的剩餘部份、來自新加入到鈍化層130開口中之材料、或藉由直接形成於導電結構140中的方式。關於上述得到支撐部分的選擇將於之後再詳細說明(在第4A-6D圖的介紹中)。
在一些實施方式中，導電結構140包含凸塊(bump)或焊球(soldering ball)。根據一些實施方式，鈍化層之開口具有一種形狀，其包含多邊形、圓形或橢圓形。當開口的形狀為多邊形時，所述多邊形之實例包含，但不限於，三角形、矩形、梯形、平行四邊形、菱形、五邊形或六邊形。在一些實施方式中，導電結構140之支撐部分142b的材料包含，但不限於，至少一種無機材料如二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、二氧化鈦(titanium dioxide)、氧化鋁(aluminum oxide)，或至少一種有機材料如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole，PBO)，或其組合。在一些實施方式中，圖案化 表面結構142之金屬部分142a的材料為錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、合金(alloy)或其組合。在一些實施方式中，鈍化層130之材料為至少一種無機材料如二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、二氧化鈦(titanium dioxide)、氧化鋁(aluminum oxide)，或至少一種有機材料如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole，PBO)，或其組合。
本發明提供一種連接結構100具有導電結構140，其經由圖案化表面結構142與金屬層120接觸。進一步地，圖案化表面結構142之支撐部分142b可於回焊製程中減少應力(stress)以改善晶片翹曲。因此，連接結構100中之導電結構140的圖案化表面結構142可避免晶片破裂且提升可靠性，更降低整體的翹曲級(warpage level)。
根據本發明多個實施方式，第2A-2C圖為沿著第1圖中之A-A’線之仰視圖。參照第2A圖，在一實施方式中，圖案化表面結構142之支撐部分142b為網狀結構。根據另一實施方式，第2B圖繪示出圖案化表面結構142之支撐部分142b為複數個規則排列柱子。舉例而言，所述柱子具有一剖面包含多邊形、圓形或橢圓形。此外，舉例來說多邊形包含，但不限於三角形、矩形、梯形、平行四邊形、菱形、五角形或六角形。第2B圖繪示出具有圓形剖面之柱子。在一些實施方式中，圖案化表面結構142之支撐部分142b為一或多個同心圓柱。第2C圖繪示出圖案化表面結構142之支撐部分142b為兩個同心圓柱。
請參照第3圖。根據本發明多個實施方式，第3圖為一種連接結構之剖面圖。如第3圖所示，連接結構200包含半導體基板210、金屬層220、鈍化層230、導電結構240及凸塊下方金屬(under-bump metallurgy，UBM)層250。半導體基板210上方具有金屬層220位於其 上。具有一開口之鈍化層230位於金屬層220之上方。而導電結構240具有圖案化表面結構242，導電結構240之圖案化表面結構242經由鈍化層230之開口與金屬層220接觸。導電結構240之圖案化表面結構242包含金屬部分242a與支撐部分242b。凸塊下方金屬層250設置於金屬層220與導電結構240之間，且凸塊下方金屬層250之材料例如包含，但不限於氮化鈦(TiN)、鈦(Ti)、氮化鎢(WN)、錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、鎳(Ni)、合金或其組合。然而，第3圖繪示出之實施例係對應於第1圖所示之實施例，所以其詳細說明便不在此重複。因此，根據一些實施方式，可利用如前述第1圖之說明所提及之相似的材料及任何細節。
請參照第4A-4C圖。根據本發明多個實施方式，第4A-4C圖為一種連接結構製造過程中之中間階段剖面圖。
本發明一些實施方式提供一種製造如第4C圖所示之連接結構300之方法。首先參照第4A圖，金屬層320形成於半導體基板310之上方，而後鈍化層330形成於金屬層320之上方。接著，如第4B圖所示，凹槽化鈍化層330以形成開口332。詳細說明如下，使用光阻(未顯示)至鈍化層330上。於鈍化層330進行微影(lithography)與蝕刻(etching)以形成開口332，且開口332中具有鈍化層330之剩餘部分以作為開口332中之支撐部份334。繼續參照第4C圖，將金屬填入第4B圖所示之開口332中，而後回焊金屬以形成具有圖案化表面結構342之導電結構340。圖案化表面結構342包含金屬部分342a與支撐部份334，且其會透過第4B圖所示之鈍化層330的開口332與金屬層320接觸。詳細描述如下，舉例而言，將金屬填入第4B圖所示之開口332中的方法包含，但不限於電鍍(plating)、熱蒸鍍(thermal evaporation)或濺鍍(sputtering)。 在一些實施方式中，藉由通過回焊爐(reflow oven)或在紅外線燈泡下進行退火(annealing)以回焊金屬。
繼續參照第4A-4C圖。在一些實施方式中，支撐部份334之材料與鈍化層330相同，其為至少一種無機材料如二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、二氧化鈦(titanium dioxide)、氧化鋁(aluminum oxide)，或至少一種有機材料如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole，PBO)，或其組合。根據一些實施方式，圖案化表面結構342之金屬部分342a包含，但不限於錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、合金(alloy)或其組合。
請參照第5A-5D圖。根據本發明多個實施方式，第5A-5D圖為一種連接結構製造過程中之中間階段剖面圖。
本發明一些實施方式提供一種製造如第5D圖所示之連接結構400之方法。首先參照第5A圖，金屬層420形成於半導體基板410之上方，而後鈍化層430形成於金屬層420之上方。接著，如第5B圖所示，凹槽化鈍化層430以形成開口432。詳細說明如下，使用光阻(未顯示)至鈍化層430上。於鈍化層430進行微影(lithography)與蝕刻(etching)以形成開口432。現在參照第5C圖，支撐部分440形成於第5B圖所示之開口432中。根據一些實施方式，支撐部分440係以介電材料所製成，舉例而言，介電材料如二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、二氧化鈦(titanium dioxide)或其組合。接著參照第5D圖，將金屬填入第5B圖所示之開口432中，而後回焊金屬以形成具有圖案化表面結構452之導電結構450。圖案化表面結構452包含金屬部分452a與支撐部份440，且其會透過第5B圖所示之鈍化層430的開口432與金屬層420接觸。詳細描述如下，舉例而言，將金屬填入第5B圖所示之開口 432中的方法包含，但不限於電鍍(plating)、熱蒸鍍(thermal evaporation)或濺鍍(sputtering)。在一些實施方式中，藉由通過回焊爐(reflow oven)或在紅外線燈泡下進行退火(annealing)以回焊金屬。此外，根據一些實施方式，可利用如前述第4A-4C圖之說明所提及之相似的材料。
請參照第6A-6D圖。根據本發明多個實施方式，第6A-6D圖為一種連接結構製造過程中之中間階段剖面圖。
本發明一些實施方式提供一種製造如第6D圖所示之連接結構500之方法。首先參照第6A圖，金屬層520形成於半導體基板510之上方，而後鈍化層530形成於金屬層520之上方。接著，如第6B圖所示，凹槽化鈍化層530以形成開口532。詳細說明如下，使用光阻(未顯示)至鈍化層530上。於鈍化層530進行微影(lithography)與蝕刻(etching)以形成開口532。參照第6C圖，單獨形成的導電結構540具有包含金屬部分542a與支撐部分542b之圖案化表面結構542。接著參照第6D圖，導電結構540之圖案化表面結構542透過第6B圖所示之鈍化層530的開口532與金屬層520接觸。此外，根據一些實施方式，可利用如前述第4A-4C圖之說明所提及之相似的材料。
根據一些實施方式，在凹槽化鈍化層之後，以及形成導電結構之前，所述方法更包含形成凸塊下方金屬(under-bump metallurgy，UBM)層於金屬層及導電結構之間。舉例而言，形成凸塊下方金屬層之方法包含，但不限於第7A-7D圖所示之製程。
請參照第7A-7D圖。根據本發明多個實施方式，第7A-7D圖為一種連接結構製造過程中之中間階段剖面圖。
本發明一些實施方式提供一種製造如第7D圖所示之連接結構600之方法。首先參照第7A圖，金屬層620形成於半導體基板610 之上方，而後鈍化層630形成於金屬層620之上方。接著，如第6B圖所示，凹槽化鈍化層630以形成開口632。詳細說明如下，使用光阻(未顯示)至鈍化層630上。於鈍化層630進行微影(lithography)與蝕刻(etching)以形成開口632，且開口632中具有鈍化層630之剩餘部分以作為開口632中之支撐部份634。具有支撐部分634之開口632，其具有一個上表面。接著參照第7C圖，凸塊下方金屬層640保形地形成於開口632之上表面上。隨後參照第7D圖，將金屬填入第7B圖所示之開口632中，而後回焊金屬以形成具有圖案化表面結構652之導電結構650。圖案化表面結構652包含金屬部分652a與支撐部份634，且其會透過第7B圖所示之鈍化層630的開口632與金屬層620接觸。詳細描述如下，舉例而言，將金屬填入第7B圖所示之開口632中的方法包含，但不限於電鍍(plating)、熱蒸鍍(thermal evaporation)或濺鍍(sputtering)。在一些實施方式中，藉由通過回焊爐(reflow oven)或在紅外線燈泡下進行退火(annealing)以回焊金屬。此外，根據一些實施方式，可利用如前述第4A-4C圖之說明所提及之相似的材料。
由上述本發明實施方式可知，本發明優於習知的連接結構與其製程，並總結此些優點如下。凸塊於回焊期間時常引起晶片翹曲。替代地，本發明提供一種改善的連接結構及其製造方法。所述連接結構之導電結構可透過圖案化表面結構與金屬層接觸。此外，圖案化表面結構包含金屬部分與支撐部分。支撐部分於回焊期間可降低應力(stress)，進而改善晶片翹曲的問題。總結前述重點，在連接結構中之導電結構的圖案化表面結構於回焊期間可改善晶片翹曲，以避免晶片破裂(crack)，並增加其可靠性，更降低整體的翹曲級(warpage level)。
本發明已經相當詳細地描述某些實施方式，但其他的實施方式亦為可能的。因此，所附請求項的精神和範籌不應限於本文所描述的實施方式。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (14)

  1. 一種半導體結構，包含：一半導體基板；一金屬層於該半導體基板之上方；一鈍化層於該金屬層之上方，該鈍化層包含至少一開口；一圖案化表面結構，其包含該鈍化層之若干部分，該鈍化層之該等部分位於該鈍化層之該至少一開口中且包含一支撐部分；以及一導電結構，其包含一焊接材料，該焊接材料位於該圖案化表面結構上方且經由該鈍化層之該至少一開口直接接觸該金屬層，其中該導電結構之若干部分至少部分地延伸至該鈍化層之該至少一開口中且實質上接觸該圖案化表面結構之該支撐部分之整個上表面及側壁。
  2. 如申請專利範圍第1項之半導體結構，其中該導電結構包含一焊接凸塊或一焊球。
  3. 如申請專利範圍第1項之半導體結構，其中該圖案化表面結構之該支撐部分包含一網狀結構、複數個規則排列柱子或一同心圓柱中之一者。
  4. 如申請專利範圍第3項之半導體結構，其中該圖案化表面結構之該支撐部分包含該等規則排列柱子，其具有包含一多邊形、一圓形或一橢圓形中之至少一者之一剖面。
  5. 如申請專利範圍第1項之半導體結構，其中該圖案化表面結構之該支撐部分之材料包含至少一種無機材料、至少一種有機材料或其組合；而該無機材料為二氧化矽、氮化矽、二氧化鈦或氧化鋁，該有機材料為聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole，PBO)。
  6. 如申請專利範圍第1項之半導體結構，其中該導電結構包含錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、其合金或其組合中之至少一者。
  7. 如申請專利範圍第1項之半導體結構，其中該鈍化層之該開口具有一形狀，其包含一多邊形、一圓形或一橢圓形中之至少一者。
  8. 一種半導體晶片，包含：一基板；金屬材料於該基板之上方；鈍化材料於該金屬材料之上方，該鈍化材料包含若干開口，至少一些開口暴露包含該鈍化材料之若干部分之一圖案化表面結構；以及若干導電結構，其包含一焊接材料，該焊接材料位於該等圖案化表面結構上方，該等導電結構至少部分地延伸至該鈍化材料之該至少一些開口中，且直接接觸該金屬材料，該導電結構實質上接觸該圖案化表面結構之整個上表面及側壁。
  9. 如申請專利範圍第8項之半導體晶片，其中該鈍化材料及該圖案化表面結構之各者包含一介電材料，其包含二氧化矽、氮化矽、二氧化鈦或其組合。
  10. 如申請專利範圍第8項之半導體晶片，其中該圖案化表面結構包含一網狀結構、複數個規則排列柱子或至少一同心圓柱中之一者。
  11. 如申請專利範圍第10項之半導體晶片，其中該圖案化表面結構包含該等規則排列柱子，其具有包含一多邊形、一圓形或一橢圓形中之至少一者之一剖面。
  12. 如申請專利範圍第10項之半導體晶片，其中該至少一同心圓柱包含兩個同心圓柱。
  13. 如申請專利範圍第8項之半導體晶片，其中該導電結構包含一焊接凸塊或一焊球。
  14. 如申請專利範圍第8項之半導體晶片，其中該導電結構包含錫(Sn)、銀(Ag)、銅(Cu)、金(Au)、其合金或其組合中之至少一者。
TW104130982A 2015-06-05 2015-09-18 具有圖案化表面結構的半導體結構及包括該等結構的半導體晶片 TWI645529B (zh)

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