CN106102349B - A kind of technique improving plating filling perforation recess value - Google Patents
A kind of technique improving plating filling perforation recess value Download PDFInfo
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- CN106102349B CN106102349B CN201610515365.7A CN201610515365A CN106102349B CN 106102349 B CN106102349 B CN 106102349B CN 201610515365 A CN201610515365 A CN 201610515365A CN 106102349 B CN106102349 B CN 106102349B
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- dimple
- level
- value
- copper
- subtracts
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention discloses a kind of techniques for improving plating filling perforation recess value, comprising the following steps: 1) confirmation exceeds the requirement of 10 μm of Dimple maximum value >；2) it grades: being graded according to Dimple maximum value；3) etching subtracts copper: according to the rating result of step 2), being etched and subtracts copper operation；4) it is electroplated: according to the rating result of step 2), carrying out electroplating operations.The technique first detects the size of Dimple value and carries out grade evaluation, is successively etched further according to grade evaluation and subtracts copper and electroplating operations, can effectively reduce because Dimple value it is exceeded caused by pcb board scrap problem.
Description
Technical field
The present invention relates to circuit board manufacture fields, and in particular to a kind of technique for improving plating filling perforation recess value.
Background technique
Plating filling perforation (blind hole and through-hole) technology is widely used in high density interconnection substrate (HDI) and encapsulation base at present
Plate field.Blind hole aperture or through-hole radius-thickness ratio plating filling perforation (pore structure) due to and electroplating additive basic principle
, inevitably there is Dimple value in limitation.Since blind hole is related to subsequent welding process, usually there are different rule to Dimple value
The requirement of lattice generally requires Dimple≤10um, but often in the actual production process, since the problems such as liquid medicine control is easy to produce
Raw Dimple excessive problem, PCB manufacturing enterprise is often using whole the case where scrapping.Therefore to having generated a part or whole part
The exceeded situation of Dimple value, carries out processing of doing over again, to guarantee yield rate.
Summary of the invention
For overcome the deficiencies in the prior art, the purpose of the invention is to provide a kind of reduction Dimple value excessive problem
Improvement plating filling perforation recess value technique.
The purpose of the present invention is implemented with the following technical solutions:
A kind of technique improving plating filling perforation recess value, comprising the following steps:
1) confirmation exceeds required value: by 10 μm of Dimple maximum value > for as defining standard, confirmation Dimple value exceeds
Required value；
2) it grades: being graded according to Dimple maximum value, wherein regard 10 μm of Dimple≤15 μm < as the first order；
It regard 15 μm of Dimple≤20 μm < as the second level；It regard 20 μm of Dimple≤25 μm < as the third level；By 25 μm of < Dimple
≤ 30 μm are used as the fourth stage；It regard Dimple > 30 as level V；
3) etching subtracts copper: according to the rating result of step 2), being etched and subtracts copper operation, wherein the first order subtracts 2-5 μm of copper；
The second level, the third level subtract 5-10 μm of copper respectively；The fourth stage subtracts 10-15 μm of copper；Level V subtracts 20 μm of copper；
4) it is electroplated: according to the rating result of step 2), carrying out electroplating operations, wherein first order electroplating thickness is 4-7 μm；The
Second level, third level difference electroplating thickness are 7-12 μm；The fourth stage, level V difference electroplating thickness are 10-15 μm.
Preferably, further including a step 5) detection confirmation: detection Dimple maximum value after step 4), when Dimple maximum
10 μm of value >, step 2) is repeated to step 4).
Preferably, the current density of electroplating operations is 1.0-2.0ASD in step 4).
Preferably, the current density of electroplating operations is 1.1-1.5ASD in step 4).
Preferably, selecting current density according to the rating result of step 2) in step 4), wherein the first order is 1.3-
1.7ASD。
Preferably, selecting current density according to the rating result of step 2) in step 4), wherein the second level is 1.1-
1.5ASD。
Preferably, selecting current density according to the rating result of step 2), wherein the third level, the fourth stage in step 4)
It is 1.0-1.4ASD with level V.
Compared with prior art, the beneficial effects of the present invention are:
The size that the present invention first detects Dimple value carries out grade evaluation, is etched further according to grade evaluation and subtracts copper and electricity
Plate program, can effectively reduce because Dimple value it is exceeded caused by pcb board scrap problem.
Detailed description of the invention
Fig. 1 is that through-hole structure schematic diagram is filled out in the plating of embodiment 1；
In Fig. 1, each appended drawing reference: 1, dry film；2, through-hole；3, dielectric layer；4, copper is thick.
Specific embodiment
In the following, being described further in conjunction with attached drawing and specific embodiment to the present invention.
The present invention provides a kind of technique for improving plating filling perforation recess value, comprising the following steps:
1) confirmation exceeds required value: by 10 μm of Dimple maximum value > for as defining standard, confirmation Dimple value exceeds
Required value；The plating for being only more than 10 μm to Dimple maximum value is filled out through-hole and is processed；
2) it grades: measuring the maximum value of Dimple, graded according to Dimple maximum value, wherein by 10 μm of <
Dimple≤15 μm are used as the first order；It regard 15 μm of Dimple≤20 μm < as the second level；20 μm of Dimple≤25 μm < are made
For the third level；It regard 25 μm of Dimple≤30 μm < as the fourth stage；It regard Dimple > 30 as level V；The grading is conducive to
Subsequent etching is instructed to subtract copper and electroplating operations；
3) etching subtracts copper: according to the rating result of step 2), being etched and subtracts copper operation, wherein the first order subtracts 2-5 μm of copper；
The second level, the third level subtract 5-10 μm of copper respectively；The fourth stage subtracts 10-15 μm of copper；Level V subtracts 20 μm of copper；Etching subtracts copper and is conducive to
Copper thickness is equably reduced on copper plate, reduces the difference between different loci Dimple value, to provide one for subsequent plating
The basal plane of a uniform ground；
4) it is electroplated: according to the rating result of step 2), carrying out electroplating operations, wherein first order electroplating thickness is 4-7 μm；The
Second level, third level difference electroplating thickness are 7-12 μm；The fourth stage, level V difference electroplating thickness are 10-15 μm.
Using technique provided by the invention, the dimple maximum value of processed plating filling perforation meets plating less than 10 μm
The specification requirement of filling perforation, can effectively reduce because Dimple value it is exceeded caused by pcb board scrap problem.
Embodiment 1: through-hole production is filled out in plating
As shown in Figure 1, through-hole is filled out in production plating, wherein 2 aperture of through-hole is 80 μm, and thickness of dielectric layers is 100 μm, is used
76min is electroplated in current density 1.4ASD.
Embodiment 2:
A kind of technique improving plating filling perforation recess value, comprising the following steps:
1) confirmation exceeds required value: through-hole is filled out in the plating that Example 1 obtains, and is conduct by 10 μm of Dimple maximum value >
Defining standard, confirmation Dimple value exceed required value；Through-hole is filled out in the plating of embodiment 1, and actual measurement Dimple maximum value is 25 μm, because
The plating of this embodiment 1 fills out through-hole beyond required value；
2) it grades: measuring the maximum value of Dimple, graded according to Dimple maximum value, wherein by 10 μm of <
Dimple≤15 μm are used as the first order；It regard 15 μm of Dimple≤20 μm < as the second level；20 μm of Dimple≤25 μm < are made
For the third level；It regard 25 μm of Dimple≤30 μm < as the fourth stage；It regard Dimple > 30 as level V；Therefore embodiment 1
The Dimple maximum value that through-hole is filled out in plating is 25 μm, the i.e. third level；
3) etching subtracts copper: according to the rating result of step 2), being etched and subtracts copper operation, wherein the first order subtracts 2-5 μm of copper；
The second level, the third level subtract 5-10 μm of copper respectively；The fourth stage subtracts 10-15 μm of copper；Level V subtracts 20 μm of copper；Because of the plating of embodiment 1
The Dimple maximum value of through-hole is filled out in the third level, so etching subtracts 8 μm of copper；
4) it is electroplated: according to the rating result of step 2), carrying out electroplating operations, wherein first order electroplating thickness is 4-7 μm；The
Second level, third level difference electroplating thickness are 7-12 μm；The fourth stage, level V difference electroplating thickness are 10-15 μm；Because of embodiment 1
Plating fill out the Dimple maximum value of through-hole in the third level, so being electroplated with 1.2ASD current density, electroplating thickness is 8 μ
m。
Using the present embodiment treated plating fill out through-hole, again measure dimple maximum value be only 7 μm.That is, using this
Embodiment provide technique, can efficiently reduce because Dimple value it is exceeded caused by pcb board scrap problem.
Embodiment 3:
A kind of technique improving plating filling perforation recess value, comprising the following steps:
1) confirmation exceeds required value: through-hole is filled out in the plating that Example 1 obtains, and is conduct by 10 μm of Dimple maximum value >
Defining standard, confirmation Dimple value exceed required value；Through-hole is filled out in the plating of embodiment 1, and actual measurement Dimple maximum value is 32 μm, because
The plating of this embodiment 1 fills out through-hole beyond required value；
2) it grades: measuring the maximum value of Dimple, graded according to Dimple maximum value, wherein by 10 μm of <
Dimple≤15 μm are used as the first order；It regard 15 μm of Dimple≤20 μm < as the second level；20 μm of Dimple≤25 μm < are made
For the third level；It regard 25 μm of Dimple≤30 μm < as the fourth stage；It regard Dimple > 30 as level V；Because through-hole is filled out in plating
Dimple maximum value is 32 μm, i.e. level V；
3) etching subtracts copper: according to the rating result of step 2), being etched and subtracts copper operation, wherein the first order subtracts 2-5 μm of copper；
The second level, the third level subtract 5-10 μm of copper respectively；The fourth stage subtracts 10-15 μm of copper；Level V subtracts 20 μm of copper；Because of the plating of embodiment 1
The Dimple maximum value of through-hole is filled out in level V, so etching subtracts 20 μm of copper；
4) it is electroplated: according to the rating result of step 2), carrying out electroplating operations, wherein first order electroplating thickness is 4-7 μm；The
Second level, third level difference electroplating thickness are 7-12 μm；The fourth stage, level V difference electroplating thickness are 10-15 μm；Because of embodiment 1
Plating fill out the Dimple maximum value of through-hole in level V, so being electroplated with 1.1ASD current density, electroplating thickness is 13 μ
m。
Using the present embodiment treated plating fill out through-hole, again measure dimple maximum value be only 9 μm.That is, using this
Embodiment provide technique, can efficiently reduce because Dimple value it is exceeded caused by pcb board scrap problem.
Embodiment 4:
A kind of technique improving plating filling perforation recess value, comprising the following steps:
1) confirmation exceeds required value: through-hole is filled out in the plating that Example 1 obtains, and is conduct by 10 μm of Dimple maximum value >
Defining standard, confirmation Dimple value exceed required value；Through-hole is filled out in the plating of embodiment 1, and actual measurement Dimple maximum value is 14 μm, because
The plating of this embodiment 1 fills out through-hole beyond required value；
2) it grades: measuring the maximum value of Dimple, graded according to Dimple maximum value, wherein by 10 μm of <
Dimple≤15 μm are used as the first order；It regard 15 μm of Dimple≤20 μm < as the second level；20 μm of Dimple≤25 μm < are made
For the third level；It regard 25 μm of Dimple≤30 μm < as the fourth stage；It regard Dimple > 30 as level V；Because through-hole is filled out in plating
Dimple maximum value is 14 μm, the i.e. first order；
3) etching subtracts copper: according to the rating result of step 2), being etched and subtracts copper operation, wherein the first order subtracts 2-5 μm of copper；
The second level, the third level subtract 5-10 μm of copper respectively；The fourth stage subtracts 10-15 μm of copper；Level V subtracts 20 μm of copper；Because of the plating of embodiment 1
The Dimple maximum value of through-hole is filled out in the first order, so etching subtracts 5 μm of copper；
4) it is electroplated: according to the rating result of step 2), carrying out electroplating operations, wherein first order electroplating thickness is 4-7 μm；The
Second level, third level difference electroplating thickness are 7-12 μm；The fourth stage, level V difference electroplating thickness are 10-15 μm；Because of embodiment 1
Plating fill out the Dimple maximum value of through-hole in the first order, so being electroplated with 1.5ASD current density, electroplating thickness is 7 μ
m。
Using the present embodiment treated plating fill out through-hole, again measure dimple maximum value be only 6 μm.That is, using this
Embodiment provide technique, can efficiently reduce because Dimple value it is exceeded caused by pcb board scrap problem.
Embodiment 5:
A kind of technique improving plating filling perforation recess value, comprising the following steps:
1) confirmation exceeds required value: through-hole is filled out in the plating that Example 1 obtains, and is conduct by 10 μm of Dimple maximum value >
Defining standard, confirmation Dimple value exceed required value；Through-hole is filled out in the plating of embodiment 1, and actual measurement Dimple maximum value is 19 μm, because
The plating of this embodiment 1 fills out through-hole beyond required value；
2) it grades: measuring the maximum value of Dimple, graded according to Dimple maximum value, wherein by 10 μm of <
Dimple≤15 μm are used as the first order；It regard 15 μm of Dimple≤20 μm < as the second level；20 μm of Dimple≤25 μm < are made
For the third level；It regard 25 μm of Dimple≤30 μm < as the fourth stage；It regard Dimple > 30 as level V；Because through-hole is filled out in plating
Dimple maximum value is 19 μm, the i.e. second level；
3) etching subtracts copper: according to the rating result of step 2), being etched and subtracts copper operation, wherein the first order subtracts 2-5 μm of copper；
The second level, the third level subtract 5-10 μm of copper respectively；The fourth stage subtracts 10-15 μm of copper；Level V subtracts 20 μm of copper；Because of the plating of embodiment 1
The Dimple maximum value of through-hole is filled out in the second level, so etching subtracts 7 μm of copper；
4) it is electroplated: according to the rating result of step 2), carrying out electroplating operations, wherein first order electroplating thickness is 4-7 μm；The
Second level, third level difference electroplating thickness are 7-12 μm；The fourth stage, level V difference electroplating thickness are 10-15 μm；Because of embodiment 1
Plating fill out the Dimple maximum value of through-hole in the second level, so being electroplated with 1.3ASD current density, electroplating thickness is 10 μ
m。
Using the present embodiment treated plating fill out through-hole, again measure dimple maximum value be only 8 μm.Use this reality
Apply example offer technique, can efficiently reduce because Dimple value it is exceeded caused by pcb board scrap problem.
Embodiment 6:
A kind of technique improving plating filling perforation recess value, comprising the following steps:
1) confirmation exceeds required value: through-hole is filled out in the plating that Example 1 obtains, and is conduct by 10 μm of Dimple maximum value >
Defining standard, confirmation Dimple value exceed required value；Through-hole is filled out in the plating of embodiment 1, and actual measurement Dimple maximum value is 28 μm, because
The plating of this embodiment 1 fills out through-hole beyond required value；
2) it grades: measuring the maximum value of Dimple, graded according to Dimple maximum value, wherein by 10 μm of <
Dimple≤15 μm are used as the first order；It regard 15 μm of Dimple≤20 μm < as the second level；20 μm of Dimple≤25 μm < are made
For the third level；It regard 25 μm of Dimple≤30 μm < as the fourth stage；It regard Dimple > 30 as level V；Because through-hole is filled out in plating
Dimple maximum value is 28 μm, the i.e. fourth stage；
3) etching subtracts copper: according to the rating result of step 2), being etched and subtracts copper operation, wherein the first order subtracts 2-5 μm of copper；
The second level, the third level subtract 5-10 μm of copper respectively；The fourth stage subtracts 10-15 μm of copper；Level V subtracts 20 μm of copper；Because of the plating of embodiment 1
The Dimple maximum value of through-hole is filled out in the fourth stage, so etching subtracts 14 μm of copper；
4) it is electroplated: according to the rating result of step 2), carrying out electroplating operations, wherein first order electroplating thickness is 4-7 μm；The
Second level, third level difference electroplating thickness are 7-12 μm；The fourth stage, level V difference electroplating thickness are 10-15 μm；Because of embodiment 1
Plating fill out the Dimple maximum value of through-hole in the fourth stage, so being electroplated with 1.2ASD current density, electroplating thickness is 12 μ
m；
5) detection confirmation: detection Dimple maximum value repeats step 2) to step 4) as 10 μm of Dimple maximum value >,
Detection Dimple maximum value is 6 μm again.Technique provided in this embodiment is used, can be efficiently reduced because Dimple value is exceeded
Cause pcb board scrap problem.
It will be apparent to those skilled in the art that can make various other according to the above description of the technical scheme and ideas
Corresponding change and deformation, and all these changes and deformation all should belong to the protection scope of the claims in the present invention
Within.
Claims (6)
1. a kind of technique for improving plating filling perforation recess value, comprising the following steps:
1) confirmation exceeds required value: by 10 μm of Dimple maximum value > for as defining standard, confirmation Dimple value, which exceeds, to be required
Value；
2) it grades: being graded according to Dimple maximum value, regard 10 μm of Dimple≤15 μm < as the first order；By 15 μm of <
Dimple≤20 μm are used as the second level；It regard 20 μm of Dimple≤25 μm < as the third level；By 25 μm of Dimple≤30 μm <
As the fourth stage；It regard Dimple > 30 as level V；
3) etching subtracts copper: according to the rating result of step 2, being etched and subtracts copper operation, wherein the first order subtracts 2-5 μm of copper；Second
Grade, the third level subtract 5-10 μm of copper respectively；The fourth stage subtracts 10-15 μm of copper；Level V subtracts 20 μm of copper；
4) it is electroplated: according to the rating result of step 2, carrying out electroplating operations, wherein first order electroplating thickness is 4-7 μm；Second
Grade, third level difference electroplating thickness are 7-12 μm；The fourth stage, level V difference electroplating thickness are 10-15 μm；5) detection confirmation:
It detects Dimple maximum value and repeats step 2 to step 4) as 10 μm of Dimple maximum value >.
2. technique according to claim 1, which is characterized in that in step 4), the current density of electroplating operations is 1.0-
2.0ASD。
3. technique according to claim 1, which is characterized in that in step 4), the current density of electroplating operations is 1.1-
1.5ASD。
4. technique according to claim 1, which is characterized in that in step 4), select electricity according to the rating result of step 2
Current density, wherein the first order is 1.3-1.7 ASD.
5. technique according to claim 1, which is characterized in that in step 4), select electricity according to the rating result of step 2
Current density, wherein the second level is 1.1-1.5 ASD.
6. technique according to claim 1, which is characterized in that in step 4), select electricity according to the rating result of step 2
Current density, wherein the third level, the fourth stage and level V are 1.0-1.4 ASD.
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| CN201610515365.7A CN106102349B (en) | 2016-06-30 | 2016-06-30 | A kind of technique improving plating filling perforation recess value |
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| JP2013118370A (en) * | 2011-12-05 | 2013-06-13 | Samsung Electro-Mechanics Co Ltd | Via hole plating method and printed circuit board manufactured using the same |
| KR20140020661A (en) * | 2012-08-10 | 2014-02-19 | 삼성전기주식회사 | Repair method for via of circuit board |
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