CN106098770A - 一种新型栅结构的GaN基HEMT器件 - Google Patents

一种新型栅结构的GaN基HEMT器件 Download PDF

Info

Publication number
CN106098770A
CN106098770A CN201610638795.8A CN201610638795A CN106098770A CN 106098770 A CN106098770 A CN 106098770A CN 201610638795 A CN201610638795 A CN 201610638795A CN 106098770 A CN106098770 A CN 106098770A
Authority
CN
China
Prior art keywords
drain electrode
grid
gan base
jack
bottom grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610638795.8A
Other languages
English (en)
Inventor
李宝国
马京路
韩威
张书敬
张达泉
孙丞
杨荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huashi Jiaku Semiconductor Co ltd
Original Assignee
HEBEI FAREAST COMMUNICATION SYSTEM ENGINEERING Co Ltd
Original Suzhou Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HEBEI FAREAST COMMUNICATION SYSTEM ENGINEERING Co Ltd, Original Suzhou Microelectronics Co Ltd filed Critical HEBEI FAREAST COMMUNICATION SYSTEM ENGINEERING Co Ltd
Priority to CN201610638795.8A priority Critical patent/CN106098770A/zh
Publication of CN106098770A publication Critical patent/CN106098770A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种新型栅结构的GaN基HEMT器件，所述绝缘层的上端设有倒直角梯形的插孔，且插孔位于源极和漏极之间，所述插孔内插接有对应的直角梯形的底层栅极，所述底层栅极的上端设有顶层栅极。该新型栅结构的GaN基HEMT器件，底层栅极为直角梯形结构，使底层栅极与势垒层的距离呈现阶梯状增加，不是形成突变方式，这种结构可以提高器件的击穿电压，并且不用增加栅极与漏极之间的距离，同时因为底层栅极靠近漏极端的右下角部分不会形成直角的方式，同样会减少器件的热电子效应，从而提高器件的可靠性和使用寿命，而且，通过减少顶层栅极和势垒层之间的距离可以更好的抑制器件电流崩溃效应。

Description

一种新型栅结构的GaN基HEMT器件
技术领域
本发明涉及GaN基HEMT器件技术领域具体为一种新型栅结构的GaN基HEMT器件。
背景技术
作为第三代半导体材料代表GaN基HEMT(High Electron Mobility Transisors)器件,其具有击穿电场高、迁移率高、禁带宽度大、抗辐射能力强、热导率好等优点，GaN的这些优良性质，综合了前两代Si和GaAs等半导体材料的优点，这些无可替代的优势使GaN成为研究热点，进而在微波射频、大功率方面有广泛的应用前景。随着5G时代的来临，LDMOS(Lateral Double-Diffused Metal-Oxide Semiconductor)将不能满足基站功放系统对高频、宽带、高效等要求，研发新一代GaN HEMT器件取代LDMOS器件在基站上的应用成为迫切需要。由于GaN HEMT器件在应用的时候产生电流崩塌效应，该效应容易导致器件性能下降，如增益、射频输出功率、效率等，改善器件电流崩塌效应是提高器件性能可行性的方法。GaN器件可靠性和性能是一对矛盾的体系，提高器件的可靠性，可以通过增加器件的击穿电压实现，而提高器件的击穿电压一般会导致器件的导通电阻增加，从而降低器件的性能，如何提高器件的击穿电压，而不提高器件的导通电阻成为亟需解决的问题。为此，我们设计一种新型栅结构的GaN基HEMT器件。
发明内容
本发明的目的在于提供一种新型栅结构的GaN基HEMT器件，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种新型栅结构的GaN基HEMT器件，包括衬底，所述衬底的上端设有沟道层，且沟道层的上端设有势垒层，所述势垒层的上端左右两侧分别设有源极和漏极，且源极和漏极之间设有绝缘层，所述绝缘层的左右两端分别延伸覆盖到源极和漏极的上端，所述绝缘层的上端设有倒直角梯形的插孔，且插孔位于源极和漏极之间，所述插孔的斜边靠近漏极，所述插孔内插接有对应的直角梯形的底层栅极，所述底层栅极的上端设有顶层栅极。
优选的，所述底层栅极与顶层栅极为一体成型结构。
优选的，所述沟道层的厚度为0.5-5um。
优选的，所述势垒层的厚度为5-500um。
与现有技术相比，本发明的有益效果是：该新型栅结构的GaN基HEMT器件，底层栅极为直角梯形结构，使底层栅极与势垒层的距离呈现阶梯状增加，不是形成突变方式，这种结构可以提高器件的击穿电压，并且不用增加栅极与漏极之间的距离，同时因为底层栅极靠近漏极端的右下角部分不会形成直角的方式，同样会减少器件的热电子效应，从而提高器件的可靠性和使用寿命，而且，通过减少顶层栅极和势垒层之间的距离可以更好的抑制器件电流崩溃效应。
附图说明
图1为本发明结构示意图；
图2为本发明结构的A结构放大图。
图中：1衬底、2沟道层、3势垒层、4源极、5漏极、6绝缘层、7插孔、8底层栅极、9顶层栅极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1-2，本发明提供一种技术方案：一种新型栅结构的GaN基HEMT器件，包括衬底1，衬底1为SiC，衬底1的上端设有沟道层2，且沟道层2的上端设有势垒层3，沟道层2的厚度为0.5-5um，势垒层3的厚度为5-500um，势垒层3的上端左右两侧分别设有源极4和漏极5，且源极4和漏极5之间设有绝缘层6。
绝缘层6的左右两端分别延伸覆盖到源极4和漏极5的上端，绝缘层6的上端设有倒直角梯形的插孔7，且插孔7位于源极4和漏极5之间，插孔7的斜边靠近漏极5，插孔7内插接有对应的直角梯形的底层栅极8，底层栅极8呈三角形，为肖特基栅极，底层栅极8的上端设有顶层栅极9，底层栅极8与顶层栅极9为一体成型结构，一个整体。
该新型栅结构的GaN基HEMT器件，底层栅极8为直角梯形结构，使底层栅极8与势垒层3的距离呈现阶梯状增加，不是形成突变方式，这种结构可以提高器件的击穿电压，并且不用增加顶层栅极9与漏极5之间的距离，同时因为底层栅极8靠近漏极5端的右下角部分不会形成直角的方式，同样会减少器件的热电子效应，从而提高器件的可靠性和使用寿命，而且，通过减少顶层栅极9和势垒层3之间的距离可以更好的抑制器件电流崩溃效应。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (4)

1.一种新型栅结构的GaN基HEMT器件，包括衬底(1)，其特征在于：所述衬底(1)的上端设有沟道层(2)，且沟道层(2)的上端设有势垒层(3)，所述势垒层(3)的上端左右两侧分别设有源极(4)和漏极(5)，且源极(4)和漏极(5)之间设有绝缘层(6)，所述绝缘层(6)的左右两端分别延伸覆盖到源极(4)和漏极(5)的上端，所述绝缘层(6)的上端设有倒直角梯形的插孔(7)，且插孔(7)位于源极(4)和漏极(5)之间，所述插孔(7)的斜边靠近漏极(5)，所述插孔(7)内插接有对应的直角梯形的底层栅极(8)，所述底层栅极(8)的上端设有顶层栅极(9)。
2.根据权利要求1所述的一种新型栅结构的GaN基HEMT器件，其特征在于：所述底层栅极(8)与顶层栅极(9)为一体成型结构。
3.根据权利要求1所述的一种新型栅结构的GaN基HEMT器件，其特征在于：所述沟道层(2)的厚度为0.5-5um。
4.根据权利要求1所述的一种新型栅结构的GaN基HEMT器件，其特征在于：所述势垒层(3)的厚度为5-500um。
CN201610638795.8A 2016-08-08 2016-08-08 一种新型栅结构的GaN基HEMT器件 Pending CN106098770A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610638795.8A CN106098770A (zh) 2016-08-08 2016-08-08 一种新型栅结构的GaN基HEMT器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610638795.8A CN106098770A (zh) 2016-08-08 2016-08-08 一种新型栅结构的GaN基HEMT器件

Publications (1)

Publication Number Publication Date
CN106098770A true CN106098770A (zh) 2016-11-09

Family

ID=57454531

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610638795.8A Pending CN106098770A (zh) 2016-08-08 2016-08-08 一种新型栅结构的GaN基HEMT器件

Country Status (1)

Country Link
CN (1) CN106098770A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108333209A (zh) * 2018-02-28 2018-07-27 中国电子科技集团公司第十三研究所 一种GaN HEMT加速寿命试验方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130160A (zh) * 2011-01-06 2011-07-20 西安电子科技大学 槽形沟道AlGaN/GaN增强型HEMT器件及制作方法
CN102315262A (zh) * 2010-07-06 2012-01-11 西安能讯微电子有限公司 半导体器件及其制造方法
CN102856355A (zh) * 2012-09-04 2013-01-02 程凯 增强型半导体器件
CN205920974U (zh) * 2016-08-08 2017-02-01 苏州本然微电子有限公司 一种新型栅结构的GaN基HEMT器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102315262A (zh) * 2010-07-06 2012-01-11 西安能讯微电子有限公司 半导体器件及其制造方法
CN102130160A (zh) * 2011-01-06 2011-07-20 西安电子科技大学 槽形沟道AlGaN/GaN增强型HEMT器件及制作方法
CN102856355A (zh) * 2012-09-04 2013-01-02 程凯 增强型半导体器件
CN205920974U (zh) * 2016-08-08 2017-02-01 苏州本然微电子有限公司 一种新型栅结构的GaN基HEMT器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108333209A (zh) * 2018-02-28 2018-07-27 中国电子科技集团公司第十三研究所 一种GaN HEMT加速寿命试验方法
CN108333209B (zh) * 2018-02-28 2020-04-28 中国电子科技集团公司第十三研究所 一种GaN HEMT加速寿命试验方法

Similar Documents

Publication Publication Date Title
CN110047910B (zh) 一种高耐压能力的异质结半导体器件
CN104600107B (zh) 电子器件
CN110649096B (zh) 一种高压n沟道HEMT器件
CN104521000A (zh) 具有可调的高栅极-源极额定电压的iii族氮化物增强型晶体管
CN104538440B (zh) 一种缓冲层荷电resurf hemt器件
CN104253117A (zh) 半导体装置
CN104051523A (zh) 一种低欧姆接触电阻的半导体器件及其制作方法
CN104201201A (zh) 一种用于GaN基HEMT器件的自适应偏置场板
CN102201442B (zh) 基于沟道阵列结构的异质结场效应晶体管
CN110660851A (zh) 一种高压n沟道HEMT器件
CN102403349B (zh) Ⅲ族氮化物mishemt器件
CN111403480A (zh) 一种高压AlGaN/GaN HEMT器件及其制备方法
CN102738228A (zh) 栅边缘凹槽型源场板结构高电子迁移率晶体管
CN105140302A (zh) 电荷补偿耐压结构垂直氮化镓基异质结场效应管
CN106098757A (zh) 场效应晶体管
CN110649097B (zh) 一种高压p沟道HFET器件
CN111969047A (zh) 一种具有复合背势垒层的氮化镓异质结场效应晶体管
CN110634950A (zh) 氧化镓垂直结构半导体电子器件及其制作方法
CN110660843A (zh) 一种高压p沟道HEMT器件
CN117174756B (zh) 具有双重多层屏蔽结构的SiC MOSFET元胞结构、器件及制备方法
CN205920974U (zh) 一种新型栅结构的GaN基HEMT器件
CN110880534B (zh) 一种具有复合缓冲层的氮化镓异质结场效应晶体管
CN106098770A (zh) 一种新型栅结构的GaN基HEMT器件
CN107093629A (zh) 增强型hfet
KR20140105056A (ko) 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20230419

Address after: Room 803, Building 2, No. 111 Xiangke Road, China (Shanghai) Pilot Free Trade Zone, Pudong New Area, Shanghai, 200120

Applicant after: Shanghai Huashi Jiaku Semiconductor Co.,Ltd.

Address before: Unit 4-B403, Creative Industry Park, No. 328 Xinghu Street, Industrial Park, Suzhou City, Jiangsu Province, 215123

Applicant before: SUZHOU BENRAN MICROELECTRONICS CO.,LTD.

Applicant before: HEBEI FAREAST COMMUNICATION SYSTEM ENGINEERING Co.,Ltd.

TA01 Transfer of patent application right
RJ01 Rejection of invention patent application after publication

Application publication date: 20161109

RJ01 Rejection of invention patent application after publication