CN106094956A - The many processing circuitry of wireless signal based on Internet of Things - Google Patents
The many processing circuitry of wireless signal based on Internet of Things Download PDFInfo
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- CN106094956A CN106094956A CN201610680838.9A CN201610680838A CN106094956A CN 106094956 A CN106094956 A CN 106094956A CN 201610680838 A CN201610680838 A CN 201610680838A CN 106094956 A CN106094956 A CN 106094956A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/563—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation
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Abstract
The invention discloses a kind of many processing circuitry of wireless signal based on Internet of Things, it is characterized in that: mainly by processing chip U, audion VT4, wireless signal receiver A, polar capacitor C10, diode D6, Zener diode D5, correction of frequency errors circuit, sampling hold circuit, the compositions such as the signal level regulation circuit that signal wave reception filtering circuit, the audion bias amplifier being serially connected between signal wave reception filtering circuit and sampling hold circuit, and the OUT pin that with the negative pole of polar capacitor C11 and processes chip U respectively and G pin are connected.Interference signal in the signal of telecommunication received can be suppressed or eliminate by the present invention, and the dutycycle of the square-wave signal of the digital signal frequency after processing chip U conversion can also be adjusted by the present invention, the level making the digital signal of output keeps stable, thus improves the present invention accuracy to signal processing.
Description
Technical field
The present invention relates to automation field, specifically refer to a kind of wireless signal of based on Internet of Things many processing of circuit system
System.
Background technology
The application of modern agricultural technology brings huge economy, society and ecological benefits for society.Along with society
Development, the consciousness of people's water saving gradually strengthens, and in order to reach the purpose of water saving, people generally use agricultural Internet of Things to come farming
The irrigation of thing is managed, to improve the effect of irrigation water efficiency and irrigation；The many employings of people at present are by humidity sensor, nothing
Line signal acquiring system, wireless signal processing system, wireless control system, video monitoring system and automatic water sprinkler systme composition
Agricultural Internet of Things；Wherein the wireless control system in agricultural Internet of Things is then the number by being transmitted wireless signal processing system
Word information controls automatic water sprinkler systme, and therefore, can automatic water sprinkler systme irrigate then for crops accurately accurately
Depend on that wireless signal processing system is the most accurate to signal processing.
But, the wireless signal processing system of existing agricultural Internet of Things there is also signal in terms of the process of the docking collection of letters number
The process of the low problem of accuracy processed, the i.e. humidity information that humidity sensor is transmitted by its wireless signal processing system is accurate
Really property is relatively low, causes the wireless control system in agricultural Internet of Things cannot control automatic water sprinkler systme accurately and carries out crops
Irrigate, the serious growth that have impact on crops.
Therefore it provides a kind of agriculture Internet of Things wireless signal processing system that can accurately process signal is to work as
It is engaged in anxious.
Summary of the invention
It is an object of the invention to the process in the docking collection of letters number of gram wireless signal processing system of existing agricultural Internet of Things
Aspect there is also the defect that the accuracy of signal processing is low, it is provided that a kind of wireless signal of based on Internet of Things many processing of circuit system
System.
The purpose of the present invention is by following technical proposals reality: the many processing circuitry of wireless signal based on Internet of Things,
Mainly by processing chip U, audion VT4, wireless signal receiver A, the sampling being connected with the IN pin processing chip U keeps
Circuit, positive pole is connected with the emitter stage of audion VT4, negative pole is connected with the COMP pin processing chip U after resistance R16
Polar capacitor C10, one end with process chip U COMP pin be connected, the other end is connected with the GND pin of process chip U
Connect resistance R18, the P pole of the rear ground connection base stage with audion VT4 after resistance R17 be connected, N pole and the OUT pipe processing chip U
The diode D6 that foot is connected, positive pole colelctor electrode with audion VT4 after inductance L2 is connected, negative pole after resistance R19 with
Polar capacitor C11, the N pole that is connected of CLK pin processing chip U is connected with the VC pin processing chip U, the other end is with outward
The Zener diode D5 that portion power supply VCC is connected, the signal being connected with the signal output part of wireless signal receiver A receives filter
Wave circuit, the audion bias amplifier being serially connected between signal wave reception filtering circuit and sampling hold circuit, respectively with pole
Property electric capacity C11 the signal level regulation circuit that is connected with the OUT pin processing chip U of negative pole, and be serially connected in process core
Correction of frequency errors circuit composition between the G pin of sheet U and signal level regulation circuit；Described audion bias amplifier
It is connected with the P pole of signal wave reception filtering circuit and Zener diode D5 the most respectively；The B pin of described process chip U and polarity
The negative pole of electric capacity C10 is connected.
Described correction of frequency errors electricity routing amplifier P5, amplifier P6, audion VT8, audion VT9, positive pole is through electricity
Be connected with the colelctor electrode of audion VT9 after sense L4, polarity electricity that negative pole positive pole with amplifier P5 after resistance R40 is connected
Hold that C20, P pole colelctor electrode with audion VT9 after resistance R35 is connected, N pole is connected with the emitter stage of audion VT8
Diode D12, positive pole colelctor electrode with audion VT8 after resistance R36 is connected, polar capacitor C24, the P pole of minus earth
The diode that emitter stage with audion VT9 is connected after adjustable resistance R39, N pole is connected with the negative pole of polar capacitor C24
D13, the adjustable resistance that one end is connected with the colelctor electrode of audion VT8, the other end is connected with the negative pole of polar capacitor C24
R37, positive pole base stage with audion VT9 after resistance R38 is connected, negative pole after resistance R41 with the outfan of amplifier P5
The polar capacitor C22 being connected, positive pole is connected with the adjustable end of adjustable resistance R39, negative pole is connected with the positive pole of amplifier P5
The polar capacitor C21 connect, positive pole is connected with the base stage of audion VT8, negative pole after resistance R42 with the outfan of amplifier P6
Polar capacitor C23, the N pole being connected is connected with the outfan of amplifier P6, P pole after resistance R43 with amplifier P6 just
Diode D14, the N pole that pole is connected is connected with the negative pole of amplifier P5, P pole after resistance R44 with the positive pole of amplifier P6
The diode D15 being connected, positive pole is connected with the outfan of amplifier P6, negative pole is connected with signal level regulation circuit
Polar capacitor C25, and one end is connected with the negative pole of amplifier 4, the resistance R45 of other end ground connection composition；Described polarity electricity
The positive pole holding C20 is connected with the G pin processing chip U.
Further, described sampling hold circuit is by amplifier P3, amplifier P4, audion VT6, audion VT7, P pole
The diode D9 that positive pole with amplifier P3 is connected after resistance R27, negative pole is connected with audion bias amplifier, just
Pole polar capacitor C15 that negative pole is connected, negative pole is connected with the base stage of audion VT7 with amplifier P3 after resistance R28,
P pole be connected with the negative pole of amplifier P3 after two poles that are connected of ground connection, N pole colelctor electrode with audion VT7 after inductance L3
Pipe D10, positive pole emitter stage with audion VT6 after resistance R32 is connected, the polar capacitor C17 of minus earth, and positive pole is through electricity
Be connected with the positive pole of amplifier P4 after resistance R31, polarity electricity that negative pole outfan with amplifier P4 after resistance R33 is connected
Holding C18, positive pole P pole with diode D10 after resistance R29 is connected, negative pole negative with polar capacitor C18 after resistance R30
The polar capacitor C16 that pole is connected, positive pole is connected with the negative pole of amplifier P4, negative pole is connected with the outfan of amplifier P4
Polar capacitor C19, and P pole is connected with the negative pole of amplifier P4, N pole after resistance R34 with the outfan of amplifier P4
The diode D11 composition being connected；The base stage of described audion VT6 is connected with the outfan of amplifier P3, its colelctor electrode with
The emitter stage of audion VT7 is connected；The positive pole of described amplifier P4 also emitter stage with audion VT6 is connected, its output
The IN pin held and process chip U is connected.
Described signal wave reception filtering circuit is connected with the base stage of audion VT2 by audion VT1, audion VT2, positive pole
Connect, polar capacitor C3 that negative pole is connected with the signal output part of wireless receiver A, positive pole after resistance R3 with polar capacitor C3
Negative pole be connected, polar capacitor C4, the N pole of minus earth emitter stage with audion VT2 after resistance R6 is connected, P pole
The diode D2 that negative pole with polar capacitor C4 is connected after resistance R5, one end is connected with the base stage of audion VT2, another
The adjustable resistance R4 that is connected with the P pole of diode D2 of end, negative pole is connected with the base stage of audion VT2, positive pole is through resistance R2
Polar capacitor C2, the P pole that colelctor electrode with audion VT2 is connected afterwards is connected with the base stage of audion VT1, N pole and three poles
The diode D1 that the colelctor electrode of pipe VT2 is connected, and positive pole emitter stage with audion VT1 after resistance R1 be connected, negative
The polar capacitor C1 composition of pole ground connection；The colelctor electrode of described audion VT1 is collectively forming signal with the colelctor electrode of audion VT2 and connects
Receive filter circuit to be outfan and be connected with audion bias amplifier.
Described audion bias amplifier by amplifier P1, audion VT3, N pole after resistance R9 with audion VT3's
The diode D3 that base stage is connected, P pole is connected with the colelctor electrode of audion VT2, positive pole is connected with the P pole of diode D3,
The polar capacitor C5 that negative pole negative pole with amplifier P1 after resistance R7 is connected, positive pole negative with amplifier P1 after resistance R8
The polar capacitor C6 that pole is connected, negative pole is connected with the outfan of amplifier P1, negative pole after resistance R10 with amplifier P1's
Outfan is connected, positive pole colelctor electrode with audion VT3 after resistance R11 is connected polar capacitor C8, P pole and amplifier
The diode D4 that the positive pole of P1 is connected, N pole colelctor electrode with audion VT3 after resistance R12 is connected, negative pole and diode
The polar capacitor that the P pole of D4 is connected, positive pole is sequentially connected through inductance L1 colelctor electrode with audion VT3 after resistance R13
C7, one end is connected with the junction point of inductance L1 with resistance R13, the resistance R14 of other end ground connection, and positive pole and amplifier P1
The polar capacitor C9 that outfan is connected, negative pole is connected with the N pole of diode D9 after resistance R15 composition；Described amplification
The positive pole of device P1 is also connected with the N pole of diode D3, its minus earth；The outfan of described amplifier P1 also with audion
The emitter stage of VT3 is connected；The junction point of described inductance L1 and resistance R13 is also connected with the P pole of Zener diode D5.
Described signal level regulation circuit is by field effect transistor MOS, amplifier P2, audion VT5, positive pole and field effect transistor
The drain electrode of MOS is connected, negative pole colelctor electrode with audion VT5 after resistance R22 is connected polar capacitor C13, P pole and pole
The negative pole of property electric capacity C13 be connected after the diode D7 that is connected with the negative pole of amplifier P2 of ground connection, N pole, one end and audion
The adjustable resistance R23 that the colelctor electrode of VT5 is connected, the other end is connected with the negative pole of amplifier P2, positive pole after resistance R24 with
Polar capacitor C14, the P pole that the negative pole of amplifier P2 is connected, negative pole outfan with amplifier P2 after resistance R25 is connected
The diode that after being connected with the negative pole of amplifier P2, ground connection, N pole negative pole with polar capacitor C14 after resistance R26 is connected
D8, and positive pole grid with field effect transistor MOS after resistance R20 is connected, negative pole after resistance R221 with amplifier P2's
The polar capacitor C12 composition that outfan is connected；The source electrode of described field effect transistor MOS is connected with the negative pole of polar capacitor C11；
The base stage of described audion VT5 is connected with the OUT pin processing chip U, its emitter stage is connected with the positive pole of amplifier P2；
The positive pole of described polar capacitor C12 also negative pole with polar capacitor C25 is connected；The outfan of described amplifier P2 is as signal
The outfan of level adjustment circuit.
For the practical effect of the present invention, described process chip U the most preferentially have employed the integrated chip of MB40978 and comes real
Existing.
The present invention compared with prior art has the following advantages and beneficial effect:
(1) the interference signal in the signal of telecommunication received can be suppressed or eliminate by the present invention, and the present invention can also be right
The dutycycle of the square-wave signal processing the digital signal frequency after chip U conversion is adjusted, and makes the digital signal of output
Level keeps stable, thus improves the present invention accuracy to signal processing, makes the wireless control system in agricultural Internet of Things
Automatic water sprinkler systme can accurately be controlled crops are irrigated.
(2) phase place planted in ripple or the frequency error of the digital signal of output after processing chip U conversion can be entered by the present invention
Row correction, and the harmonic wave left in digital signal can be eliminated or suppress, make the bandwidth of digital signal keep stable, thus
Improve the present invention accuracy to signal processing.
(3) present invention can make the signal of telecommunication keep being basically unchanged before being changed, it is ensured that the process chip U of the present invention turns
Change precision, ensure that the present invention accuracy to signal processing.
(4) amplitude of the signal of telecommunication can be adjusted by the present invention, and can suppress common-mode signal, ensures that this
The invention accuracy to signal processing.
(5) the process chip U of the present invention the most preferentially have employed the integrated chip of MB40978 and realizes, this chip and external electrical
Sub-element combines, and can effectively load the interference of external electromagnetic ripple signal, thus improve the present invention standard to signal processing
Really property and reliability.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of the present invention.
Fig. 2 is the electrical block diagram of the sampling hold circuit of the present invention.
Fig. 3 is the electrical block diagram of the correction of frequency errors circuit of the present invention.
Detailed description of the invention
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited to
This.
Embodiment
As it is shown in figure 1, the present invention is mainly by processing chip U, audion VT4, wireless signal receiver A, resistance R16, electricity
Resistance R17, resistance R18, resistance R19, inductance L2, polar capacitor C10, polar capacitor C11, Zener diode D5, diode D6, frequently
Rate error correction circuit, sampling hold circuit, signal wave reception filtering circuit, audion bias amplifier, and signal level
Regulation circuit composition.
During connection, sampling hold circuit is connected with the IN pin processing chip U.The positive pole of polar capacitor C10 and three poles
The emitter stage of pipe VT4 is connected, and negative pole is connected with the COMP pin processing chip U after resistance R16.One end of resistance R18
With process chip U COMP pin be connected, the other end with process chip U GND pin be connected after ground connection.Diode D6's
P pole base stage with audion VT4 after resistance R17 is connected, and N pole is connected with the OUT pin processing chip U.Polar capacitor
The positive pole of C11 colelctor electrode with audion VT4 after inductance L2 is connected, negative pole after resistance R19 with the CLK processing chip U
Pin is connected.
Meanwhile, the N pole of Zener diode D5 is connected with the VC pin processing chip U, the other end and external power source VCC phase
Connect.Signal wave reception filtering circuit is connected with the signal output part of wireless signal receiver A.Audion bias amplifier string
It is connected between signal wave reception filtering circuit and sampling hold circuit.Signal level regulation circuit negative with polar capacitor C11 respectively
Pole is connected with the OUT pin processing chip U.Correction of frequency errors circuit is serially connected in G pin and the signal level processing chip U
Between regulation circuit.
Described audion bias amplifier P with signal wave reception filtering circuit and Zener diode D5 the most respectively is extremely connected
Connect；The described B pin of process chip U is connected with the negative pole of polar capacitor C10.During enforcement, the VC of the process chip U of the present invention
Pin is connected with outside 12V DC voltage.For the practical effect of the present invention, described process chip U the most preferentially adopts
Realize with the integrated chip of MB40978.Wherein, audion VT4, polar capacitor C10, diode D6, resistance R16 and resistance
The demagnetizer that R17 is formed, this demagnetizer can eliminate or suppress the interference to process chip U of the electromagnetic wave in the external world, make process chip U
The signal of telecommunication can accurately be carried out conversion process, effectively raise the accuracy to signal processing of the present invention.
Meanwhile, the outfan of its level adjustment circuit as the present invention outfan and with agricultural Internet of Things controlled in wireless
The input of the controller of system is connected, and this wireless control system is then that the digital signal transmitted according to the present invention controls
The soil of crops is irrigated by automatic water sprinkler systme, and therefore the present invention improves the accuracy to signal processing, i.e. improves
The accuracy that crops are irrigated by agriculture Internet of Things.
Further, described signal wave reception filtering circuit is by audion VT1, audion VT2, resistance R1, resistance R2, resistance
R3, adjustable resistance R4, resistance R5, resistance R6, polar capacitor C1, polar capacitor C2, polar capacitor C3, polar capacitor C4, two poles
Pipe D1, and diode D2 composition.
During connection, the positive pole of polar capacitor C3 is connected with the base stage of audion VT2, negative pole and the letter of wireless receiver A
Number outfan is connected.The positive pole of polar capacitor C4 negative pole with polar capacitor C3 after resistance R3 is connected, minus earth.Two
The N pole of pole pipe D2 emitter stage with audion VT2 after resistance R6 is connected, P pole negative with polar capacitor C4 after resistance R5
Pole is connected.One end of adjustable resistance R4 is connected with the base stage of audion VT2, and the other end is connected with the P pole of diode D2.
Meanwhile, the negative pole of polar capacitor C2 is connected with the base stage of audion VT2, positive pole after resistance R2 with audion
The colelctor electrode of VT2 is connected.The P pole of diode D1 is connected with the base stage of audion VT1, N pole and the colelctor electrode of audion VT2
It is connected.The positive pole of polar capacitor C1 emitter stage with audion VT1 after resistance R1 is connected, minus earth.Described three poles
It is outfan inclined with audion that the colelctor electrode of pipe VT1 and the colelctor electrode of audion VT2 are collectively forming signal wave reception filtering circuit
Put amplifying circuit to be connected.
During enforcement, the signal of telecommunication that wireless signal receiver A can be transmitted by this signal wave reception filtering circuit filters, i.e.
Forming multi-stage filter by polar capacitor C3 and polar capacitor C2 and polar capacitor C4, this multi-stage filter is in the signal of telecommunication
Interference signal carry out filtration repeatedly, meanwhile, by the resistance of adjustable resistance R4 is adjusted, make the low frequency in the signal of telecommunication
Signal cannot pass through, i.e. garbage signal is prevented from；Reference signal then can be passed through smoothly, thus the mistake of the collection of letters number that achieves a butt joint
Filter, it is ensured that the present invention accuracy to signal processing.
Further, described audion bias amplifier by amplifier P1, audion VT3, resistance R7, resistance R8,
Resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, polar capacitor C5, polar capacitor C6,
Polar capacitor C7, polar capacitor C8, polar capacitor C9, diode D3, and diode D4 form.
During connection, the N pole of diode D3 base stage with audion VT3 after resistance R9 is connected, P pole and audion VT2
Colelctor electrode be connected.The positive pole of polar capacitor C5 is connected with the P pole of diode D3, negative pole after resistance R7 with amplifier P1
Negative pole be connected.The positive pole of polar capacitor C6 negative pole with amplifier P1 after resistance R8 is connected, negative pole and amplifier P1
Outfan be connected.The negative pole of polar capacitor C8 outfan with amplifier P1 after resistance R10 is connected, and positive pole is through resistance
After R11, the colelctor electrode with audion VT3 is connected.
Wherein, the P pole of diode D4 is connected with the positive pole of amplifier P1, N pole after resistance R12 with audion VT3's
Colelctor electrode is connected.The negative pole of polar capacitor C7 is connected with the P pole of diode D4, and positive pole is sequentially through inductance L1 and resistance R13
Colelctor electrode with audion VT3 is connected afterwards.One end of resistance R14 is connected with the junction point of inductance L1 with resistance R13, another
End ground connection.The positive pole of polar capacitor C9 is connected with the outfan of amplifier P1, negative pole after resistance R15 with the N of diode D9
Pole is connected.
The positive pole of described amplifier P1 is also connected with the N pole of diode D3, its minus earth；Described amplifier P1's is defeated
Go out the end emitter stage also with audion VT3 to be connected；The junction point of described inductance L1 and resistance R13 is also with Zener diode D5's
P pole is connected.This audion bias amplifier is by amplifier P1 and audion VT3 and above-mentioned other electron component shape
The amplifier become, and the amplitude of the signal of telecommunication can be adjusted by this amplifier, and common-mode signal can be suppressed, thus really
Protect the present invention accuracy to signal processing.
Yet further, described signal level regulation circuit is by field effect transistor MOS, amplifier P2, audion VT5, resistance
R20, resistance R21, resistance R22, adjustable resistance R23, resistance R24, resistance R25, resistance R26, polar capacitor C12, polar capacitor
C13, polar capacitor C14, diode D7, and diode D8 form.
During connection, the positive pole of polar capacitor C13 is connected with the drain electrode of field effect transistor MOS, negative pole after resistance R22 with three
The colelctor electrode of pole pipe VT5 is connected.The P pole of diode D7 be connected with the negative pole of polar capacitor C13 after ground connection, N pole and amplification
The negative pole of device P2 is connected.One end of adjustable resistance R23 is connected with the colelctor electrode of audion VT5, the other end and amplifier P2
Negative pole be connected.
Meanwhile, the positive pole of polar capacitor C14 negative pole with amplifier P2 after resistance R24 is connected, and negative pole is through resistance R25
Outfan with amplifier P2 is connected afterwards.The P pole of diode D8 be connected with the negative pole of amplifier P2 after ground connection, N pole is through electricity
It is connected with the negative pole of polar capacitor C14 after resistance R26.The positive pole of polar capacitor C12 after resistance R20 with field effect transistor MOS
Grid is connected, and negative pole outfan with amplifier P2 after resistance R221 is connected.
The source electrode of described field effect transistor MOS is connected with the negative pole of polar capacitor C11；The base stage of described audion VT5 with
The OUT pin processing chip U is connected, and its emitter stage is connected with the positive pole of amplifier P2；The positive pole of described polar capacitor C12
The also negative pole with polar capacitor C25 is connected；The outfan of described amplifier P2 is as the outfan of signal level regulation circuit.
During enforcement, the square wave of the digital signal frequency after processing chip U conversion can be believed by this signal level regulation circuit
Number dutycycle be adjusted, make the level of the digital signal of output keep stable, thus improve the present invention to signal processing
Accuracy.Meanwhile, the outfan of its level adjustment circuit as the present invention outfan and with agricultural Internet of Things wireless controlled
The input of the controller of system processed is connected, and this wireless control system is then that the digital signal transmitted according to the present invention is controlled
The soil of crops is irrigated by automatic water sprinkler systme processed, and therefore the present invention improves the accuracy to signal processing, i.e. carries
The accuracy that crops are irrigated by high agriculture Internet of Things.
As in figure 2 it is shown, described sampling hold circuit is by amplifier P3, amplifier P4, audion VT6, audion VT7, electricity
Resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, resistance R32, resistance R33, resistance R34, polar capacitor C15, pole
Property electric capacity C16, polar capacitor C17, polar capacitor C18, diode D9, diode D10, diode D11, and inductance L3 group
Become.
During connection, the P pole of diode D9 positive pole with amplifier P3 after resistance R27 is connected, and negative pole is inclined with audion
Put amplifying circuit to be connected.The positive pole of polar capacitor C15 negative pole with amplifier P3 after resistance R28 is connected, negative pole and three
The base stage of pole pipe VT7 is connected.The P pole of diode D10 be connected with the negative pole of amplifier P3 after ground connection, N pole is after inductance L3
It is connected with the colelctor electrode of audion VT7.The positive pole of polar capacitor C17 emitter stage with audion VT6 after resistance R32 is connected
Connect, minus earth.
Meanwhile, the positive pole of polar capacitor C18 positive pole with amplifier P4 after resistance R31 is connected, and negative pole is through resistance R33
Outfan with amplifier P4 is connected afterwards.The positive pole of polar capacitor C16 P with diode D10 after resistance R29 is extremely connected
Connecing, negative pole negative pole with polar capacitor C18 after resistance R30 is connected.The positive pole of polar capacitor C19 and the negative pole of amplifier P4
Being connected, negative pole is connected with the outfan of amplifier P4.The P pole of diode D11 is connected with the negative pole of amplifier P4, N pole
After resistance R34, the outfan with amplifier P4 is connected.
The base stage of described audion VT6 is connected with the outfan of amplifier P3, its colelctor electrode and the transmitting of audion VT7
Pole is connected；The positive pole of described amplifier P4 also emitter stage with audion VT6 is connected, its outfan with process chip U's
IN pin is connected.
During enforcement, the signal of telecommunication is transmitted processing chip U when changing, and is transformed into EOC output number from startup
Word signal, needs certain conversion time.Within this conversion time, the signal of telecommunication to be held essentially constant, otherwise conversion accuracy
There is no guarantee that, particularly when frequency input signal is higher, the biggest transformed error can be caused.Prevent the product of this error
Raw, it is necessary to make the level of input signal maintain when processing chip U conversion and starting stable, and processing chip U EOC
After can follow the tracks of again the change of input signal.Therefore the present invention is provided with sampling hold circuit at the signal input part processing chip U,
When the signal of telecommunication of this sampling hold circuit output is high level, the base stage of audion VT6 turns on emitter stage, the signal of telecommunication of input
It is added on amplifier P4 by audion VT6 so that the change of the voltage follow signal of telecommunication input signal on the positive pole of amplifier P4
Changing and change, this period is referred to as the phase of following the tracks of.When the signal of telecommunication of sampling hold circuit output is low level, the base of audion VT6
Pole disconnects with emitter stage, and it is constant also that the now holding of the voltage on the positive pole of amplifier P4 audion VT6 disconnects the magnitude of voltage of moment
Changing the signal of telecommunication etc. pending chip U, this period is referred to as keeping the phase；This sampling hold circuit runs repeatedly with this,
The signal of telecommunication of the input level before processed chip U changes is made to remain stable, it is ensured that to process the chip U electricity to input
The precision of signal conversion, ensures that the present invention accuracy to signal processing.
As it is shown on figure 3, described correction of frequency errors electricity routing amplifier P5, amplifier P6, audion VT8, audion
VT9, resistance R35, resistance R36, adjustable resistance R37, resistance R38, adjustable resistance R39, resistance R40, resistance R41, resistance R42,
Resistance R43, resistance R44, resistance R45, polar capacitor C20, polar capacitor C21, polar capacitor C22, polar capacitor C23, polarity
Electric capacity C24, polar capacitor C25, diode D12, diode D13, diode D14, diode D15, and inductance L4 form.
During connection, the positive pole of polar capacitor C20 colelctor electrode with audion VT9 after inductance L4 is connected, and negative pole is through electricity
It is connected with the positive pole of amplifier P5 after resistance R40.The P pole of diode D12 after resistance R35 with the colelctor electrode phase of audion VT9
Connecting, N pole is connected with the emitter stage of audion VT8.The positive pole of polar capacitor C24 after resistance R36 with the collection of audion VT8
Electrode is connected, minus earth.The P pole of diode D13 emitter stage with audion VT9 after adjustable resistance R39 is connected, N
Pole is connected with the negative pole of polar capacitor C24.
Wherein, one end of adjustable resistance R37 is connected with the colelctor electrode of audion VT8, and the other end is with polar capacitor C24's
Negative pole is connected.The positive pole of polar capacitor C22 base stage with audion VT9 after resistance R38 is connected, and negative pole is through resistance R41
Outfan with amplifier P5 is connected afterwards.The positive pole of polar capacitor C21 is connected with the adjustable end of adjustable resistance R39, negative pole
It is connected with the positive pole of amplifier P5.The positive pole of polar capacitor C23 is connected with the base stage of audion VT8, and negative pole is through resistance R42
Outfan with amplifier P6 is connected afterwards.
Meanwhile, the N pole of diode D14 is connected with the outfan of amplifier P6, P pole after resistance R43 with amplifier P6
Positive pole be connected.The N pole of diode D15 is connected with the negative pole of amplifier P5, P pole after resistance R44 with amplifier P6's
Positive pole is connected.The positive pole of polar capacitor C25 is connected with the outfan of amplifier P6, and negative pole regulates circuit phase with signal level
Connect.One end of resistance R45 is connected with the negative pole of amplifier 4, other end ground connection.The positive pole of described polar capacitor C20 and place
The G pin of reason chip U is connected.
During operation, the audion VT8 of this correction of frequency errors circuit, polar capacitor C23, polar capacitor C24, polar capacitor
The annular electro mean longitude of the digital signal of the output of the main circuit that C23, resistance R35, resistance R42, inductance L4 and diode D12 are formed
After adjustable resistance R37 dividing potential drop compared with the level of reference signal, error amount be input to by polar capacitor C20, audion VT9,
The signal detector that adjustable resistance R39, diode D13, amplifier P5 and polar capacitor C22 are formed, through signal detector
Handling averagely, amplify, compare after, then through amplifier P6, diode D15, diode D14, resistance R43, resistance R44 and
The signal level comparator of resistance R45 composition achieves the power factor holding one of input signal power factor and sampled signal
Cause, even if the power factor of digital signal is close to the power factor of reference signal, thus reach the numeral processing chip U output
The purpose that the power factor error of the frequency of signal frequency and input signal is corrected, ensure that the present invention is to signal at
The accuracy of reason.
As it has been described above, just can well realize the present invention.
Claims (7)
1. the many processing circuitry of wireless signal based on Internet of Things, it is characterised in that: mainly by processing chip U, audion
VT4, wireless signal receiver A, the sampling hold circuit being connected with the IN pin processing chip U, positive pole is with audion VT4's
The polar capacitor C10 that emitter stage is connected, negative pole is connected with the COMP pin processing chip U after resistance R16, one end and place
Resistance R18, the P pole warp of ground connection after the COMP pin of reason chip U is connected, the other end is connected with the GND pin of process chip U
The diode D6 that after resistance R17, the base stage with audion VT4 is connected, N pole is connected with the OUT pin processing chip U, positive pole
After inductance L2, the colelctor electrode with audion VT4 is connected, negative pole is connected with the CLK pin processing chip U after resistance R19
Polar capacitor C11, N pole and process chip U the voltage stabilizing two that VC pin is connected, the other end is connected with external power source VCC
Pole pipe D5, the signal wave reception filtering circuit being connected with the signal output part of wireless signal receiver A, it is serially connected in signal and receives filter
Audion bias amplifier between wave circuit and sampling hold circuit, respectively with the negative pole of polar capacitor C11 and process core
The signal level regulation circuit that the OUT pin of sheet U is connected, and it is serially connected in the G pin processing chip U and signal level regulation
Correction of frequency errors circuit composition between circuit；Described audion bias amplifier the most respectively with signal wave reception filtering circuit
It is connected with the P pole of Zener diode D5；The described B pin of process chip U is connected with the negative pole of polar capacitor C10.
The many processing circuitry of wireless signal based on Internet of Things the most according to claim 1, it is characterised in that: described frequency
Rate error correction circuit by amplifier P5, amplifier P6, audion VT8, audion VT9, positive pole after inductance L4 with audion
Polar capacitor C20, the P pole that the colelctor electrode of VT9 is connected, negative pole positive pole with amplifier P5 after resistance R40 is connected is through electricity
Be connected with the colelctor electrode of audion VT9 after resistance R35, diode D12 that N pole is connected with the emitter stage of audion VT8, positive pole
After resistance R36, the colelctor electrode with audion VT8 is connected, polar capacitor C24, the P pole of minus earth is after adjustable resistance R39
Be connected with the emitter stage of audion VT9, diode D13 that N pole is connected with the negative pole of polar capacitor C24, one end and three poles
The adjustable resistance R37 that the colelctor electrode of pipe VT8 is connected, the other end is connected with the negative pole of polar capacitor C24, positive pole is through resistance
The polarity electricity that after R38, the base stage with audion VT9 is connected, negative pole outfan with amplifier P5 after resistance R41 is connected
Hold C22, the polar capacitor that positive pole is connected, negative pole is connected with the positive pole of amplifier P5 with the adjustable end of adjustable resistance R39
C21, the polarity that positive pole is connected with the base stage of audion VT8, negative pole outfan with amplifier P6 after resistance R42 is connected
Electric capacity C23, N pole is connected with the outfan of amplifier P6, P pole positive pole with amplifier P6 after resistance R43 is connected two
Pole pipe D14, two poles that N pole is connected with the negative pole of amplifier P5, P pole positive pole with amplifier P6 after resistance R44 is connected
Pipe D15, the polar capacitor C25 that positive pole is connected with the outfan of amplifier P6, negative pole is connected with signal level regulation circuit,
And one end is connected with the negative pole of amplifier 4, the resistance R45 of other end ground connection composition；The positive pole of described polar capacitor C20 with
The G pin processing chip U is connected.
The many processing circuitry of wireless signal based on Internet of Things the most according to claim 2, it is characterised in that adopt described in:
Sample holding circuit by amplifier P3, amplifier P4, audion VT6, audion VT7, P pole after resistance R27 with amplifier P3's
The diode D9 that positive pole is connected, negative pole is connected with audion bias amplifier, positive pole after resistance R28 with amplifier P3
Polar capacitor C15, the P pole that negative pole is connected, negative pole is connected with the base stage of audion VT7 be connected with the negative pole of amplifier P3
Meet the diode D10 that rear ground connection, the N pole colelctor electrode with audion VT7 after inductance L3 is connected, positive pole after resistance R32 with
The emitter stage of audion VT6 is connected, the polar capacitor C17 of minus earth, positive pole after resistance R31 with the positive pole of amplifier P4
Be connected, polar capacitor C18 that negative pole outfan with amplifier P4 after resistance R33 is connected, positive pole after resistance R29 with
The polar capacitor C16 that the P pole of diode D10 is connected, negative pole negative pole with polar capacitor C18 after resistance R30 is connected, just
The polar capacitor C19 that pole is connected with the negative pole of amplifier P4, negative pole is connected with the outfan of amplifier P4, and P pole with
The diode D11 composition that the negative pole of amplifier P4 is connected, N pole outfan with amplifier P4 after resistance R34 is connected；Institute
The outfan of the base stage and amplifier P3 of stating audion VT6 is connected, its colelctor electrode is connected with the emitter stage of audion VT7；
The positive pole of described amplifier P4 also emitter stage with audion VT6 is connected, its outfan is connected with the IN pin processing chip U
Connect.
The many processing circuitry of wireless signal based on Internet of Things the most according to claim 3, it is characterised in that: described letter
Number wave reception filtering circuit is by audion VT1, audion VT2, and positive pole is connected with the base stage of audion VT2, negative pole connects with wireless
Receiving the polar capacitor C3 that is connected of signal output part of device A, positive pole negative pole with polar capacitor C3 after resistance R3 is connected, negative
Polar capacitor C4, the N pole of pole ground connection emitter stage with audion VT2 after resistance R6 is connected, P pole after resistance R5 with polarity
The diode D2 that the negative pole of electric capacity C4 is connected, one end is connected with the base stage of audion VT2, the P of the other end and diode D2
The adjustable resistance R4 that pole is connected, negative pole is connected with the base stage of audion VT2, positive pole after resistance R2 with audion VT2's
Polar capacitor C2, the P pole that colelctor electrode is connected is connected with the base stage of audion VT1, the colelctor electrode phase of N pole and audion VT2
The diode D1 connected, and positive pole emitter stage with audion VT1 after resistance R1 is connected, the polar capacitor of minus earth
C1 forms；It is output that the colelctor electrode of described audion VT1 and the colelctor electrode of audion VT2 are collectively forming signal wave reception filtering circuit
End is also connected with audion bias amplifier.
The many processing circuitry of wireless signal based on Internet of Things the most according to claim 4, it is characterised in that: described three
Pole pipe bias amplifier is by amplifier P1, and audion VT3, N pole base stage with audion VT3 after resistance R9 is connected, P pole
The diode D3 being connected with the colelctor electrode of audion VT2, positive pole is connected with the P pole of diode D3, negative pole is after resistance R7
The polar capacitor C5 being connected with the negative pole of amplifier P1, positive pole negative pole with amplifier P1 after resistance R8 is connected, negative pole
The polar capacitor C6 being connected with the outfan of amplifier P1, negative pole outfan with amplifier P1 after resistance R10 is connected,
Polar capacitor C8, the P pole that positive pole colelctor electrode with audion VT3 after resistance R11 is connected is connected with the positive pole of amplifier P1
Connect, diode D4 that N pole colelctor electrode with audion VT3 after resistance R12 is connected, negative pole is extremely connected with the P of diode D4
Connect, polar capacitor C7 that positive pole is sequentially connected through inductance L1 colelctor electrode with audion VT3 after resistance R13, one end and electricity
The junction point of sense L1 and resistance R13 is connected, the resistance R14 of other end ground connection, and the outfan phase of positive pole and amplifier P1
The polar capacitor C9 composition that connection, negative pole are connected with the N pole of diode D9 after resistance R15；The positive pole of described amplifier P1
Also be connected with the N pole of diode D3, its minus earth；The outfan of described amplifier P1 also with the emitter stage of audion VT3
It is connected；The junction point of described inductance L1 and resistance R13 is also connected with the P pole of Zener diode D5.
The many processing circuitry of wireless signal based on Internet of Things the most according to claim 5, it is characterised in that: described letter
Number level adjustment circuit by field effect transistor MOS, amplifier P2, audion VT5, positive pole is connected with the drain electrode of field effect transistor MOS,
The negative pole of polar capacitor C13, the P pole that negative pole colelctor electrode with audion VT5 after resistance R22 is connected and polar capacitor C13
The diode D7 that after being connected, ground connection, N pole are connected with the negative pole of amplifier P2, one end is connected with the colelctor electrode of audion VT5
Connect, adjustable resistance R23 that the other end is connected with the negative pole of amplifier P2, positive pole after resistance R24 with the negative pole of amplifier P2
Be connected, polar capacitor C14, P pole that negative pole outfan with amplifier P2 after resistance R25 is connected negative with amplifier P2's
Pole be connected after the diode D8 that is connected of ground connection, N pole negative pole with polar capacitor C14 after resistance R26, and positive pole is through electricity
Be connected with the grid of field effect transistor MOS after resistance R20, pole that negative pole outfan with amplifier P2 after resistance R221 is connected
Property electric capacity C12 composition；The source electrode of described field effect transistor MOS is connected with the negative pole of polar capacitor C11；Described audion VT5's
Base stage is connected with the OUT pin processing chip U, its emitter stage is connected with the positive pole of amplifier P2；Described polar capacitor C12
Positive pole also negative pole with polar capacitor C25 be connected；The outfan of described amplifier P2 is as signal level regulation circuit
Outfan.
The many processing circuitry of wireless signal based on Internet of Things the most according to claim 6, it is characterised in that: described place
Reason chip U is the integrated chip of MB40897.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610680838.9A CN106094956A (en) | 2016-08-17 | 2016-08-17 | The many processing circuitry of wireless signal based on Internet of Things |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610680838.9A CN106094956A (en) | 2016-08-17 | 2016-08-17 | The many processing circuitry of wireless signal based on Internet of Things |
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| Publication Number | Publication Date |
|---|---|
| CN106094956A true CN106094956A (en) | 2016-11-09 |
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ID=58069398
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610680838.9A Withdrawn CN106094956A (en) | 2016-08-17 | 2016-08-17 | The many processing circuitry of wireless signal based on Internet of Things |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106094956A (en) |
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2016
- 2016-08-17 CN CN201610680838.9A patent/CN106094956A/en not_active Withdrawn
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