CN106330339A - Signal comprehensive regulation type processing system for roasting furnace infrared recognition device - Google Patents
Signal comprehensive regulation type processing system for roasting furnace infrared recognition device Download PDFInfo
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- CN106330339A CN106330339A CN201610752537.2A CN201610752537A CN106330339A CN 106330339 A CN106330339 A CN 106330339A CN 201610752537 A CN201610752537 A CN 201610752537A CN 106330339 A CN106330339 A CN 106330339A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/697—Arrangements for reducing noise and distortion
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Abstract
The invention discloses a signal comprehensive regulation type processing system for a roasting furnace infrared recognition device. The signal comprehensive regulation type processing system is characterized by mainly comprising a processing chip U, a triode VT3, a wireless receiver W, an inductor L2, an inductor L3, a signal receiving circuit, a frequency error correction circuit, a signal output amplifying circuit connected with a VOUT pin and a GPOS pin of the processing chip U separately, and a signal conditioning circuit connected in series between the frequency error correction circuit and the signal output amplifying circuit. The signal comprehensive regulation type processing system disclosed by the invention can correct multicarrier phases or frequency errors of digital signals to ensure more stable digital signals, and can also amplify weak current signals or charge signals in output signals to ensure more stable signals, thereby improving the signal processing effect of the signal comprehensive regulation type processing system and effectively ensuring the accuracy of the infrared automatic recognition device in monitoring the working positions of furnace chambers where the equipment of a flame system is located.
Description
Technical field
The present invention relates to a kind of processing system, specifically, be a kind of roaster infrared light identification device signal
Comprehensive adjustment type processing system.
Background technology
By technological requirement in calcining carbon furnace control system, flame system equipment need on roaster by temperature and time
Half interval contour moves to another furnace chamber from a furnace chamber and is operated, and traditional calcining carbon furnace control system furnace chamber identification is equal
Wire jack plug mode is used to realize.Owing to these flame system equipment needs often to move on roaster, and moving
It is necessary for plugging connected end time dynamic, therefore often results in cable and connector such as loose contact occurs, breaks
The problems such as line, thus cause monitoring system not know the operating position of flame system each equipment place furnace chamber, and then affect work
The real-time storage of skill parameter and the inquiry of historical data.
Along with the development of science and technology, infrared light automatic identification equipment is widely used in the prison of calcining carbon furnace chamber number
Control, this infrared light automatic identification equipment is many by the transmitter module for bay information, and is used for receiving this room information
Wireless signal processing system, and the main controller composition for the real-time storage of technological parameter and the inquiry of historical data；And
Wireless signal processing system is then that continual the sending of transmitter module is had the infrared light beam signal of furnace chamber information and carried out
Receiving and process, main controller obtains carbon roasting furnace after then processing according to the digital information of wireless signal processing system transmission
Technological parameter, therefore the docking of wireless signal processing system is received signal processing and is the most accurately determined the charcoal element roasting that main controller obtains
Burn the accuracy of the technological parameter of stove.
But, the signal processing system docking collection of letters number of existing calcining carbon furnace chamber infrared light automatic identification equipment
Treatment effect is poor, causes the operating position monitoring of infrared light automatic identification equipment equipment each to flame system place furnace chamber to occur
Deviation, and then affect the real-time storage of the technological parameter of calcining carbon furnace chamber number and the inquiry of historical data.
Therefore it provides a kind of calcining carbon furnace chamber infrared light automatic identification equipment letter that can improve signal processing effect
Number processing system is the task of top priority.
Summary of the invention
It is an object of the invention to overcome the signal processing of existing calcining carbon furnace chamber infrared light automatic identification equipment
The poor defect for the treatment of effect that system docking is collected mail number, it is provided that a kind of roaster infrared light identification device signal synthesis adjust
Nodal pattern processing system.
To achieve these goals, the scheme that the present invention uses is as follows: a kind of roaster infrared light identification device signal
Comprehensive adjustment type processing system, mainly by processing chip U, audion VT3, wireless receiver W, negative pole is with process chip U's
The polar capacitor C5 that GNEG pin is connected, positive pole is connected with the colelctor electrode of audion VT3, positive pole after inductance L2 with three poles
After the colelctor electrode of pipe VT3 is connected, negative pole is connected with the emitter stage of audion VT3, polar capacitor C4, the N pole of ground connection is through resistance
Two poles that after R8, the emitter stage with audion VT3 is connected, P pole is connected with the FDBK pin processing chip U after resistance R9
Pipe D4, is serially connected in the inductance L3 between the VC pin and the GPOS pin that process chip U, is serially connected in wireless receiver W and processes core
Signal receiving circuit between the IN pin of sheet U, the frequency being connected with the VNEG pin processing chip U and FDBK pin respectively
Error correction circuit, the signal output amplifier being connected with the VOUT pin processing chip U and GPOS pin respectively, and
The signal conditioning circuit composition being serially connected between correction of frequency errors circuit and signal output amplifier；Described signal receives electricity
Road is also connected with the VC pin processing chip U；The IN pin of described process chip U also colelctor electrode with audion VT3 is connected
Connect, its GND pin ground connection.
Further, described signal conditioning circuit is by amplifier P4, amplifier P5, audion VT6, and positive pole is through resistance R23
Positive pole with amplifier P4 is connected afterwards, negative pole is connected with correction of frequency errors circuit polar capacitor C14, P pole and polarity
The diode D11 that the positive pole of electric capacity C14 is connected, N pole is connected with the emitter stage of audion VT6, positive pole is with amplifier P4's
The polar capacitor C13 that positive pole is connected, negative pole outfan with amplifier P4 after resistance R22 is connected, positive pole is through adjustable electric
Be connected with the base stage of audion VT6 after resistance R25, polarity that negative pole outfan with amplifier P4 after resistance R24 is connected
Electric capacity C15, N pole is connected with the negative pole of polar capacitor C15, P pole colelctor electrode with audion VT6 after inductance L4 is connected
Diode D12, the polar capacitor that negative pole is connected with the positive pole of amplifier P5, positive pole is connected with the outfan of amplifier P4
C16, P pole positive pole with amplifier P5 after resistance R27 is connected, N pole outfan with amplifier P5 after resistance R28 is connected
The diode D14 connect, the resistance that one end is connected with the positive pole of amplifier P5, the other end is connected with the N pole of diode D14
R26, positive pole negative pole with amplifier P5 after resistance R21 is connected, polar capacitor C17, the P pole of minus earth is through resistance R29
The diode D13 that outfan with amplifier P5 is connected afterwards, N pole is connected with the negative pole of amplifier P5, and one end with put
The outfan of big device P5 is connected, the resistance R30 composition of other end ground connection；The grounded collector of described audion VT6；Described put
The minus earth of big device P4；The outfan of described amplifier P5 is also connected with signal output amplifier.
Described signal receiving circuit is by amplifier P1, amplifier P2, audion VT1, audion VT2, and negative pole is through resistance R1
The polar capacitor C1 that positive pole with amplifier P1 is connected afterwards, positive pole is connected with the output stage of wireless receiver W, one end with put
The resistance R2 that negative pole is connected, the other end is connected with the colelctor electrode of audion VT1 of big device P1, positive pole is with audion VT1's
Emitter stage is connected, polar capacitor C2, the P pole of minus earth colelctor electrode with audion VT1 after resistance R3 is connected, N pole
The diode D2 that negative pole with polar capacitor C2 is connected after resistance R6, one end is connected with the negative pole of polar capacitor C2, separately
The resistance R5 that one end is connected with the positive pole of amplifier P2, positive pole base stage with audion VT1 after inductance L1 is connected, negative pole
Polar capacitor C3, the P pole being connected with the positive pole of amplifier P2 be connected with the negative pole of amplifier P2 after ground connection, N pole through resistance
The diode D3 that after R7, outfan with amplifier P2 is connected, one end is connected with the base stage of audion VT2, the other end and pole
The adjustable resistance R4 that the positive pole of property electric capacity C3 is connected, and P pole is connected with the outfan of amplifier P1, N pole and audion
The diode D1 composition that the emitter stage of VT2 is connected；The outfan of described amplifier P2 also colelctor electrode with audion VT2 is connected
Connect；The positive pole of described polar capacitor C3 also negative pole with amplifier P1 is connected；The anelectrode of described amplifier P1 and process core
The VC pin of sheet U is connected, its negative electrode ground connection, its outfan the most also with process chip U IN pin be connected.
Described correction of frequency errors circuit is by field effect transistor MOS, audion VT4, P pole and the VNEG pin processing chip U
Be connected, diode D6 that N pole is connected with the source electrode of field effect transistor MOS, positive pole is connected with the colelctor electrode of audion VT4,
Be connected with the base stage of audion VT4 after polar capacitor C6, P electrode resistance R11 of minus earth, the diode D5 of N pole ground connection, just
The polar capacitor C7 that pole is connected with the base stage of audion VT4, be connected with the N pole of diode D5 after negative pole resistance R10, positive pole
After adjustable resistance R15, the drain electrode with field effect transistor MOS is connected, negative pole N pole with diode D5 after resistance R13 is connected
Polar capacitor C9, positive pole is connected with the adjustable side of adjustable resistance R15, negative pole after resistance R12 with the P pole phase of diode D5
The polar capacitor C8 connected, and one end is connected with the negative pole of polar capacitor C9, the other end is connected with the N pole of diode D5
Adjustable resistance R14 composition；The emitter stage of described audion VT4 respectively with process the FDBK pin of chip U and field effect transistor MOS
Grid be connected；The positive pole of described polar capacitor C7 also adjustable side with adjustable resistance R15 is connected；Described polar capacitor C9
Negative pole also negative pole with polar capacitor C14 be connected.
Described signal output amplifier is connected with the GPOS pin processing chip U by amplifier P3, audion VT5, P pole
Connect, diode D9 that N pole positive pole with amplifier P3 after resistance R19 is connected, positive pole after resistance R18 with diode D9's
Polar capacitor C10, the P pole that N pole is connected, negative pole is connected with the VOUT pin of process chip U and the VOUT pipe processing chip U
The output of diode D7, the N pole that foot is connected, N pole base stage with audion VT5 after resistance R16 is connected and amplifier P3
The diode D8 that end is connected, P pole negative pole with amplifier P3 after resistance R17 is connected, the output of positive pole and amplifier P3
End is connected, polar capacitor C11, P pole that negative pole is connected with the emitter stage of audion VT5 after resistance R20 with diode D9
The diode D10 that N pole is connected, N pole outfan with amplifier P3 after resistance R21 is connected, and positive pole and two poles
The polar capacitor C12 composition of ground connection after the N pole of pipe D9 is connected, negative pole is connected with the P pole of diode D10；Described amplifier
The minus earth of P3；The colelctor electrode of described audion VT5 is connected with the outfan of amplifier P5；Described audion VT5 sends out
Emitter-base bandgap grading is as the outfan of signal output amplifier.
For the practical effect of the present invention, described process chip U the most preferentially have employed the integrated chip of AD603A and comes real
Existing.
The present invention compared with prior art, has the following advantages and beneficial effect:
(1) the interference electric wave signal in the signal received can be eliminated by the present invention；And the present invention can also be to numeral
Many cultivations wave phase of signal or frequency error are corrected, and make digital signal more steady；And can to output signal in faint
Current signal or charge signal are amplified, and make signal more stable, thus improve the present invention effect to signal processing, have
The accuracy of the operating position monitoring of the infrared light automatic identification equipment equipment each to flame system that the ensure that place furnace chamber of effect.
(2) bandwidth of digital signal can be limited by the present invention, to filter the High-frequency Interference in digital signal and spike
Burr, and the High-frequency Interference in digital signal is filtered, make digital signal more totally, more steadily, thus improve this
The invention accuracy to signal processing.
(3) the process chip U of the present invention the most preferentially have employed the integrated chip of AD603A and realizes, this chip and peripheral circuit
Combine, can effectively improve stability and the reliability of the present invention.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of the present invention.
Fig. 2 is the electrical block diagram of the signal conditioning circuit of the present invention.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is described in further detail, but embodiments of the present invention are not
It is limited to this.
Embodiment
During enforcement, the present invention is mainly by processing chip U, audion VT3, wireless receiver W, resistance R8, resistance R9, polarity
Electric capacity C4, polar capacitor C5, inductance L2, inductance L3, diode D4, signal conditioning circuit, signal receiving circuit, frequency error school
Positive circuit, and signal output amplifier composition.
During connection, the negative pole of polar capacitor C5 is connected with the GNEG pin processing chip U, and positive pole is with audion VT3's
Colelctor electrode is connected.The positive pole of polar capacitor C4 colelctor electrode with audion VT3 after inductance L2 is connected, negative pole and audion
The emitter stage of VT3 be connected after ground connection.The N pole of diode D4 emitter stage with audion VT3 after resistance R8 is connected, P pole
It is connected with the FDBK pin processing chip U after resistance R9.
Wherein, inductance L3 is serially connected between VC pin and the GPOS pin processing chip U.Signal receiving circuit is serially connected in nothing
Between line receiver W and the IN pin processing chip U.Correction of frequency errors circuit respectively with process chip U VNEG pin and
FDBK pin is connected.Signal output amplifier is connected with the VOUT pin processing chip U and GPOS pin respectively.Signal
Modulate circuit is serially connected between correction of frequency errors circuit and signal output amplifier.Described signal receiving circuit also with process
The VC pin of chip U is connected；The IN pin of described process chip U also colelctor electrode with audion VT3 is connected, and its GND manages
Foot ground connection.
During enforcement, described wireless receiver W has furnace chamber information for receiving continual the sending of transmitter module
Infrared light beam signal, the signal of reception is then converted to the signal of telecommunication and is transmitted by this wireless receiver W.And described audion
VT3, resistance R8, resistance R9, polar capacitor C4, polar capacitor C5, inductance L2 and diode D4 then define electromagnetism interference device,
What the external world can be produced by this electromagnetism interference device suppresses or weakens the electromagnetic interference signal processing chip U, the most really
Protect the process chip U effect to signal processing, thus improve the present invention treatment effect to signal.Reality for the present invention
Border using effect, described process chip U the most preferentially have employed the integrated chip of AD603A and realizes, and the VC pin of this chip is then with outward
Portion's power supply is connected, and the external power source of the present invention is 12V DC source.
Wherein, the interference electric wave signal in the signal received then is eliminated by the signal receiving circuit of the present invention；And
Many cultivations wave phase of digital signal or frequency error can also be corrected by the correction of frequency errors circuit of the present invention, make numeral letter
Number more steady.Meanwhile, the signal output amplifier of the present invention can be to the low current signal in the signal of output or electric charge letter
Number it is amplified, makes signal more stable, thus improve the present invention effect to signal processing.Described signal output is amplified
Circuit then by the digital data transmission after processing and amplifying to main controller, main controller then according to wireless signal processing system transmission number
Word information obtains the technological parameter of carbon roasting furnace after processing.Therefore the present invention can effectively guarantee that infrared light identifies automatically
The accuracy of the operating position monitoring of device equipment each to flame system place furnace chamber, and then ensure that calcining carbon furnace chamber number
The real-time storage of technological parameter and historical data can be inquired about.
Further, described signal receiving circuit is by amplifier P1, amplifier P2, audion VT1, audion VT2, resistance
R1, resistance R2, resistance R3, adjustable resistance R4, resistance R5, resistance R6, resistance R7, polar capacitor C1, polar capacitor C2, polarity electricity
Hold C3, inductance L1, diode D1, diode D2, and diode D3 composition.
During connection, the negative pole of polar capacitor C1 positive pole with amplifier P1 after resistance R1 is connected, and positive pole connects with wireless
The output stage receiving device W is connected.One end of resistance R2 is connected with the negative pole of amplifier P1, the other end and the collection of audion VT1
Electrode is connected.The positive pole of polar capacitor C2 is connected with the emitter stage of audion VT1, minus earth.The P pole warp of diode D2
After resistance R3, the colelctor electrode with audion VT1 is connected, and N pole negative pole with polar capacitor C2 after resistance R6 is connected.
Wherein, one end of resistance R5 is connected with the negative pole of polar capacitor C2, and the other end is connected with the positive pole of amplifier P2
Connect.The positive pole of polar capacitor C3 base stage with audion VT1 after inductance L1 is connected, and negative pole is connected with the positive pole of amplifier P2
Connect.The P pole of diode D3 be connected with the negative pole of amplifier P2 after ground connection, N pole after resistance R7 with the outfan of amplifier P2
It is connected.One end of adjustable resistance R4 is connected with the base stage of audion VT2, and the other end is connected with the positive pole of polar capacitor C3
Connect.The P pole of diode D1 is connected with the outfan of amplifier P1, and N pole is connected with the emitter stage of audion VT2.
The outfan of described amplifier P2 also colelctor electrode with audion VT2 is connected；The positive pole of described polar capacitor C3
The also negative pole with amplifier P1 is connected；The anelectrode of described amplifier P1 is connected with the VC pin processing chip U, its negative electricity
Pole ground connection, its outfan is the most also connected with the IN pin processing chip U.
Further, described correction of frequency errors circuit is by field effect transistor MOS, audion VT4, resistance R10, resistance
R11, resistance R12, resistance R13, adjustable resistance R14, adjustable resistance R15, polar capacitor C polar capacitor C6, polar capacitor C7, pole
Property electric capacity C8, polar capacitor C9, diode D5, and diode D6 composition.
During connection, the P pole of diode D6 is connected with the VNEG pin processing chip U, N pole and the source of field effect transistor MOS
Pole is connected.The positive pole of polar capacitor C6 is connected with the colelctor electrode of audion VT4, minus earth.The P electrode resistance of diode D5
After R11, the base stage with audion VT4 is connected, N pole ground connection.The positive pole of polar capacitor C7 is connected with the base stage of audion VT4,
After negative pole resistance R10, the N pole with diode D5 is connected.
Meanwhile, the drain electrode with field effect transistor MOS after adjustable resistance R15 of the positive pole of polar capacitor C9 is connected, negative pole warp
After resistance R13, the N pole with diode D5 is connected.The positive pole of polar capacitor C8 is connected with the adjustable side of adjustable resistance R15, negative
P pole with diode D5 after resistance R12, pole is connected.One end of adjustable resistance R14 is connected with the negative pole of polar capacitor C9,
The other end is connected with the N pole of diode D5.
The emitter stage of described audion VT4 is connected with the FDBK pin of process chip U and the grid of field effect transistor MOS respectively
Connect；The positive pole of described polar capacitor C7 also adjustable side with adjustable resistance R15 is connected；The negative pole of described polar capacitor C9 also with
The negative pole of polar capacitor C14 is connected.
Yet further, described signal output amplifier by amplifier P3, audion VT5, resistance R16, resistance R17,
Resistance R18, resistance R19, resistance R20, resistance R21, polar capacitor C10, polar capacitor C11, polar capacitor C12, diode D8,
Diode D9, and diode D10 composition.
During connection, the P pole of diode D9 with process chip U GPOS pin be connected, N pole after resistance R19 with amplification
The positive pole of device P3 is connected.The positive pole of polar capacitor C10 N pole with diode D9 after resistance R18 is connected, negative pole and process
The VOUT pin of chip U is connected.The P pole of diode D7 is connected with the VOUT pin processing chip U, and N pole is after resistance R16
It is connected with the base stage of audion VT5.The N pole of diode D8 is connected with the outfan of amplifier P3, and P pole is after resistance R17
It is connected with the negative pole of amplifier P3.
Meanwhile, the positive pole of polar capacitor C11 is connected with the outfan of amplifier P3, negative pole and the transmitting of audion VT5
Pole is connected.N pole with diode D9 after resistance R20, the P pole of diode D10 is connected, N pole after resistance R21 with amplification
The outfan of device P3 is connected.The positive pole of polar capacitor C12 is connected with the N pole of diode D9, negative pole and the P of diode D10
Pole be connected after ground connection.The minus earth of described amplifier P3；The colelctor electrode of described audion VT5 and the outfan of amplifier P5
It is connected；The emitter stage of described audion VT5 is as the outfan of signal output amplifier.
As in figure 2 it is shown, described signal conditioning circuit is by amplifier P4, amplifier P5, audion VT6, resistance R22, resistance
R23, resistance R24, adjustable resistance R25, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, polar capacitor C13,
Polar capacitor C14, polar capacitor C15, polar capacitor C16, polar capacitor C17, diode D11, diode D12, diode
D13, diode D14, and inductance L4 form.
During connection, the positive pole of polar capacitor C14 positive pole with amplifier P4 after resistance R23 is connected, negative pole and frequency
Error correction circuit is connected.The P pole of diode D11 is connected with the positive pole of polar capacitor C14, and N pole is sent out with audion VT6's
Emitter-base bandgap grading is connected.The positive pole of polar capacitor C13 is connected with the positive pole of amplifier P4, negative pole after resistance R22 with amplifier P4
Outfan be connected.The positive pole of polar capacitor C15 base stage with audion VT6 after adjustable resistance R25 is connected, negative pole warp
After resistance R24, the outfan with amplifier P4 is connected.
Wherein, the N pole of diode D12 is connected with the negative pole of polar capacitor C15, P pole after inductance L4 with audion VT6
Colelctor electrode be connected.The negative pole of polar capacitor C16 is connected with the positive pole of amplifier P5, positive pole and the outfan of amplifier P4
It is connected.The P pole of diode D14 positive pole with amplifier P5 after resistance R27 is connected, N pole after resistance R28 with amplifier
The outfan of P5 is connected.One end of resistance R26 is connected with the positive pole of amplifier P5, the N pole phase of the other end and diode D14
Connect.
Meanwhile, the positive pole of polar capacitor C17 negative pole with amplifier P5 after resistance R21 is connected, minus earth.Two poles
The P pole of pipe D13 outfan with amplifier P5 after resistance R29 is connected, and N pole is connected with the negative pole of amplifier P5.Resistance
One end of R30 is connected with the outfan of amplifier P5, other end ground connection.The grounded collector of described audion VT6；Described put
The minus earth of big device P4；The outfan of described amplifier P5 is also connected with signal output amplifier.
During operation, the polar capacitor C1 in the signal receiving circuit of the present invention as filter capacitor by wireless receiver W institute
Low frequency signal in the signal of telecommunication of transmission eliminates or suppresses, and the amplifier P1 of this signal receiving circuit and amplifier P2 shape
Having become second order impedor, the interference electric wave signal in the signal of telecommunication is eliminated by this second order impedor, makes the electric wave frequency of the signal of telecommunication
Rate is more stable；Wherein, many cultivations of the digital signal that the correction of frequency errors circuit of the present invention generates after then processing chip U conversion
Wave phase or frequency error are corrected, and make digital signal more steady.Meanwhile, the signal output amplifier of the present invention is to frequency
Low current signal or charge signal in the digital signal of error correction circuit transmission are amplified, and make the level frequent of signal
More stable, thus improve the present invention effect to signal processing.Described signal output amplifier is then by processing and amplifying
After digital data transmission to main controller, main controller then according to wireless signal processing system transmission digital information process after
Obtain the technological parameter of carbon roasting furnace, and then ensure that real-time storage and the history number of the technological parameter of calcining carbon furnace chamber number
According to being inquired about.
Wherein, the present invention is in order to be adjusted, then at correction of frequency errors circuit the digital signal processing chip U output
And it is provided with signal conditioning circuit between signal output amplifier.The audion VT6 of this signal conditioning circuit, electric capacity C15, can
Adjust resistance R25, inductance L4 and diode D12 constitute a biasing circuit, amplifier P4, polar capacitor C13, resistance R22 with
And resistance R2 forms a pre-amplification circuit, this biasing circuit and pre-amplification circuit combine can be with distortionless to numeral
Signal is amplified.Polar capacitor C16 therein is capacitance, and polar capacitor C13 can be to the band of pre-amplification circuit
Width limits, to filter the High-frequency Interference in digital signal and spike burr.Meanwhile, amplifier P5, polar capacitor C17 and electricity
Resistance R21 diode D13, diode D14 and resistance R26 constitute a harmonic device, and this harmonic device can be further to flow velocity
High-frequency Interference in digital signal filters, and digital signal can be nursed one's health by this signal conditioning circuit, makes digital signal more
Stable, thus improve the present invention effect to signal processing.
According to above-described embodiment, can well realize the present invention.
Claims (6)
1. a roaster infrared light identification device signal synthesis adjustment type processing system, it is characterised in that main by processing
Chip U, audion VT3, wireless receiver W, negative pole is connected with the GNEG pin processing chip U, positive pole and audion VT3
The polar capacitor C5 that colelctor electrode is connected, positive pole colelctor electrode with audion VT3 after inductance L2 is connected, negative pole and audion
The emitter stage of VT3 be connected after polar capacitor C4, the N pole of ground connection emitter stage with audion VT3 after resistance R8 be connected, P
Pole after resistance R9 with the diode D4 that is connected of FDBK pin processing chip U, be serially connected in the VC pin processing chip U with
Inductance L3 between GPOS pin, is serially connected in the signal receiving circuit between wireless receiver W and the IN pin processing chip U,
The correction of frequency errors circuit being connected with the VNEG pin processing chip U and FDBK pin respectively, respectively with process chip U's
The signal output amplifier that VOUT pin is connected with GPOS pin, and it is defeated with signal to be serially connected in correction of frequency errors circuit
Go out the signal conditioning circuit composition between amplifying circuit；Described signal receiving circuit is also connected with the VC pin processing chip U；
The IN pin of described process chip U also colelctor electrode with audion VT3 is connected, its GND pin ground connection.
A kind of roaster infrared light identification device signal synthesis adjustment type processing system the most according to claim 1, its
Be characterised by, described signal conditioning circuit by amplifier P4, amplifier P5, audion VT6, positive pole after resistance R23 with amplification
Polar capacitor C14, the P pole that the positive pole of device P4 is connected, negative pole is connected with correction of frequency errors circuit is with polar capacitor C14's
The diode D11 that positive pole is connected, N pole is connected with the emitter stage of audion VT6, positive pole is connected with the positive pole of amplifier P4
Connect, polar capacitor C13 that negative pole outfan with amplifier P4 after resistance R22 is connected, positive pole after adjustable resistance R25 with
The polar capacitor C15, N that the base stage of audion VT6 is connected, negative pole outfan with amplifier P4 after resistance R24 is connected
The diode that pole is connected with the negative pole of polar capacitor C15, P pole colelctor electrode with audion VT6 after inductance L4 is connected
D12, polar capacitor C16, the P pole that negative pole is connected with the positive pole of amplifier P5, positive pole is connected with the outfan of amplifier P4
Positive pole with amplifier P5 is connected after resistance R27, N pole outfan with amplifier P5 after resistance R28 is connected two
Pole pipe D14, the resistance R26 that one end is connected with the positive pole of amplifier P5, the other end is connected with the N pole of diode D14, positive pole
After resistance R21 the negative pole with amplifier P5 be connected, polar capacitor C17, the P pole of minus earth after resistance R29 with amplification
The diode D13 that the outfan of device P5 is connected, N pole is connected with the negative pole of amplifier P5, and one end is with amplifier P5's
Outfan is connected, the resistance R30 of other end ground connection composition；The grounded collector of described audion VT6；Described amplifier P4's
Minus earth；The outfan of described amplifier P5 is also connected with signal output amplifier.
A kind of roaster infrared light identification device signal synthesis adjustment type processing system the most according to claim 2, its
Being characterised by, described signal receiving circuit is by amplifier P1, amplifier P2, audion VT1, audion VT2, and negative pole is through resistance R1
The polar capacitor C1 that positive pole with amplifier P1 is connected afterwards, positive pole is connected with the output stage of wireless receiver W, one end with put
The resistance R2 that negative pole is connected, the other end is connected with the colelctor electrode of audion VT1 of big device P1, positive pole is with audion VT1's
Emitter stage is connected, polar capacitor C2, the P pole of minus earth colelctor electrode with audion VT1 after resistance R3 is connected, N pole
The diode D2 that negative pole with polar capacitor C2 is connected after resistance R6, one end is connected with the negative pole of polar capacitor C2, separately
The resistance R5 that one end is connected with the positive pole of amplifier P2, positive pole base stage with audion VT1 after inductance L1 is connected, negative pole
Polar capacitor C3, the P pole being connected with the positive pole of amplifier P2 be connected with the negative pole of amplifier P2 after ground connection, N pole through resistance
The diode D3 that after R7, outfan with amplifier P2 is connected, one end is connected with the base stage of audion VT2, the other end and pole
The adjustable resistance R4 that the positive pole of property electric capacity C3 is connected, and P pole is connected with the outfan of amplifier P1, N pole and audion
The diode D1 composition that the emitter stage of VT2 is connected；The outfan of described amplifier P2 also colelctor electrode with audion VT2 is connected
Connect；The positive pole of described polar capacitor C3 also negative pole with amplifier P1 is connected；The anelectrode of described amplifier P1 and process core
The VC pin of sheet U is connected, its negative electrode ground connection, its outfan the most also with process chip U IN pin be connected.
A kind of roaster infrared light identification device signal synthesis adjustment type processing system the most according to claim 3, its
Being characterised by, described correction of frequency errors circuit is by field effect transistor MOS, audion VT4, P pole and the VNEG pin processing chip U
Be connected, diode D6 that N pole is connected with the source electrode of field effect transistor MOS, positive pole is connected with the colelctor electrode of audion VT4,
Be connected with the base stage of audion VT4 after polar capacitor C6, P electrode resistance R11 of minus earth, the diode D5 of N pole ground connection, just
The polar capacitor C7 that pole is connected with the base stage of audion VT4, be connected with the N pole of diode D5 after negative pole resistance R10, positive pole
After adjustable resistance R15, the drain electrode with field effect transistor MOS is connected, negative pole N pole with diode D5 after resistance R13 is connected
Polar capacitor C9, positive pole is connected with the adjustable side of adjustable resistance R15, negative pole after resistance R12 with the P pole phase of diode D5
The polar capacitor C8 connected, and one end is connected with the negative pole of polar capacitor C9, the other end is connected with the N pole of diode D5
Adjustable resistance R14 composition；The emitter stage of described audion VT4 respectively with process the FDBK pin of chip U and field effect transistor MOS
Grid be connected；The positive pole of described polar capacitor C7 also adjustable side with adjustable resistance R15 is connected；Described polar capacitor C9
Negative pole also negative pole with polar capacitor C14 be connected.
A kind of roaster infrared light identification device signal synthesis adjustment type processing system the most according to claim 4, its
Being characterised by, described signal output amplifier is by amplifier P3, audion VT5, P pole and the GPOS pin phase processing chip U
Connect, diode D9 that N pole positive pole with amplifier P3 after resistance R19 is connected, positive pole after resistance R18 with diode D9
Polar capacitor C10, the P pole that N pole is connected, negative pole is connected with the VOUT pin of process chip U with process chip U VOUT
Diode D7, the N pole that pin is connected, N pole base stage with audion VT5 after resistance R16 is connected is defeated with amplifier P3's
Going out the diode D8 that end is connected, P pole negative pole with amplifier P3 after resistance R17 is connected, positive pole is defeated with amplifier P3's
Go out end be connected, polar capacitor C11, P pole that negative pole is connected with the emitter stage of audion VT5 after resistance R20 with diode
The diode D10 that the N pole of D9 is connected, N pole outfan with amplifier P3 after resistance R21 is connected, and positive pole and two
The polar capacitor C12 composition of ground connection after the N pole of pole pipe D9 is connected, negative pole is connected with the P pole of diode D10；Described amplification
The minus earth of device P3；The colelctor electrode of described audion VT5 is connected with the outfan of amplifier P5；Described audion VT5's
Emitter stage is as the outfan of signal output amplifier.
A kind of roaster infrared light identification device signal synthesis adjustment type processing system the most according to claim 5, its
Being characterised by, described process chip U is the integrated chip of AD603A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610752537.2A CN106330339A (en) | 2016-08-29 | 2016-08-29 | Signal comprehensive regulation type processing system for roasting furnace infrared recognition device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610752537.2A CN106330339A (en) | 2016-08-29 | 2016-08-29 | Signal comprehensive regulation type processing system for roasting furnace infrared recognition device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106330339A true CN106330339A (en) | 2017-01-11 |
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ID=57788972
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610752537.2A Withdrawn CN106330339A (en) | 2016-08-29 | 2016-08-29 | Signal comprehensive regulation type processing system for roasting furnace infrared recognition device |
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| Country | Link |
|---|---|
| CN (1) | CN106330339A (en) |
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2016
- 2016-08-29 CN CN201610752537.2A patent/CN106330339A/en not_active Withdrawn
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