CN106441089A - Current waveform adjustable signal processing system for roasting furnace infrared light recognition device - Google Patents
Current waveform adjustable signal processing system for roasting furnace infrared light recognition device Download PDFInfo
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- CN106441089A CN106441089A CN201610749843.0A CN201610749843A CN106441089A CN 106441089 A CN106441089 A CN 106441089A CN 201610749843 A CN201610749843 A CN 201610749843A CN 106441089 A CN106441089 A CN 106441089A
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- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
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Abstract
The present invention discloses a current waveform adjustable signal processing system for a roasting furnace infrared light recognition device. The current waveform adjustable signal processing system is characterized in that the current waveform adjustable signal processing system is mainly composed of a processing chip U, a triode VT3, a wireless receiver W, an inductor L2, an inductor L3, an electromagnetic interference suppression circuit, a signal receiving circuit, a frequency error correcting circuit, a signal output amplifying circuit and a signal conditioning circuit which is connected in series between the frequency error correcting circuit and the signal output amplifying circuit. The current waveform adjustable signal processing system of the invention can correct the multi-carrier phase or frequency errors of digital signals to make the digital signals more stable; the current waveform adjustable signal processing system of the invention can amplify weak current signals or charge signals in outputted signals to make the signals more stable; and therefore, the signal processing effect of the current waveform adjustable signal processing system can be improved, and the accuracy of monitoring on the working locations of the devices of a flame system in a furnace room performed by the infrared light recognition device can be effectively ensured.
Description
Technical field
The present invention relates to a kind of processing system, specifically, it is a kind of roaster infrared light identifying device electric current
Waveform adjustable signal processing system.
Background technology
In calcining carbon furnace control system press technological requirement, flame system equipment need on roaster by temperature and when
Half interval contour moves to another furnace chamber from a furnace chamber and is operated, and traditional calcining carbon furnace control system furnace chamber identification is all
To be realized using wire jack plug mode.Because these flame system equipment need often to move on roaster, and moving
It is necessary for when dynamic plugging connected end, therefore often result in cable and connector such as loose contact, breaks
The problems such as line, thus leading to monitoring system not know the operating position of flame system each equipment place furnace chamber, and then affect work
The real-time storage of skill parameter and the inquiry of historical data.
With scientific and technological continuous development, infrared light automatic identification equipment is widely used in the prison of calcining carbon furnace chamber number
Control, how this infrared light automatic identification equipment is by the transmitter module for bay information, and is used for receiving this room information
Wireless signal processing system, and the main controller composition for the real-time storage of technological parameter and the inquiry of historical data；And
Wireless signal processing system is then that send continual to transmitter module has the infrared light beam signal of furnace chamber information and carry out
Receive and process, main controller obtains carbon roasting furnace after then being processed according to the digital information of wireless signal processing system transmission
Technological parameter, therefore wireless signal processing system processes to receipt signal and whether accurately determines the charcoal element roasting that main controller obtains
Burn the degree of accuracy of the technological parameter of stove.
However, the signal processing system of existing calcining carbon furnace chamber infrared light automatic identification equipment is to receipt signal
Treatment effect is poor, leads to infrared light automatic identification equipment that the operating position monitoring of flame system each equipment place furnace chamber is occurred
Deviation, and then affect the real-time storage of technological parameter of calcining carbon furnace chamber number and the inquiry of historical data.
Therefore it provides a kind of calcining carbon furnace chamber infrared light automatic identification equipment letter that can improve signal transacting effect
Number processing system is the task of top priority.
Content of the invention
It is an object of the invention to overcoming the signal transacting of existing calcining carbon furnace chamber infrared light automatic identification equipment
The poor defect for the treatment of effect that system docking is collected mail number, a kind of roaster infrared light identifying device current waveform providing can
Adjust signal processing system.
To achieve these goals, the scheme that the present invention adopts is as follows：A kind of roaster infrared light identifying device electric current
Waveform adjustable signal processing system, mainly by process chip U, triode VT3, wireless receiver W, negative pole and process chip U
The polar capacitor C5 that GNEG pin is connected, positive pole is connected with the colelctor electrode of triode VT3, positive pole after inductance L2 with three poles
The polar capacitor C4 of ground connection after the colelctor electrode of pipe VT3 is connected, negative pole is connected with the emitter stage of triode VT3, N pole is through resistance
Be connected with the emitter stage of triode VT3 after R8, two poles that P pole is connected with the FDBK pin of process chip U after resistance R9
Pipe D4, is serially connected in the inductance L3 between the VC pin of process chip U and GPOS pin, is serially connected in base stage and the place of triode VT3
Electromagnetic interference suppression circuit between the COM pin of reason chip U, be serially connected in wireless receiver W and process chip U IN pin it
Between signal receiving circuit, the correction of frequency errors circuit being connected with VNEG pin and the FDBK pin of process chip U respectively,
The signal output amplifying circuit being connected with VOUT pin and the GPOS pin of process chip U respectively, and it is serially connected in frequency by mistake
Signal conditioning circuit composition between difference correcting circuit and signal output amplifying circuit；Described signal receiving circuit also with process core
The VC pin of piece U is connected；Its GND pin ground connection of described process chip U.
Described electromagnetic interference suppression circuit by amplifier P6, triode VT7, N pole after resistance R33 with amplifier P6 just
The diode D15 that pole is connected, P pole is connected with the base stage of triode VT3, negative pole is connected with the positive pole of amplifier P6, just
The polar capacitor C18 that pole is connected with the base stage of triode VT3 after adjustable resistance R31, the N pole phase of one end and diode D15
Connect, the other end ground connection resistance R34, negative pole is connected with the emitter stage of triode VT7, positive pole after inductance L5 with amplifier
The polar capacitor C19 that the positive pole of P6 is connected, N pole is connected with the positive pole of amplifier P6, P pole after resistance R32 with triode
The diode D16 that the base stage of VT7 is connected, N pole is connected with the output end of amplifier P6 after resistance R36, P pole and amplifier
The diode D17 that the negative pole of P6 is connected, one end is connected with the negative pole of amplifier P6, the output end of the other end and amplifier P6
The adjustable resistance R37 being connected, positive pole is connected with the colelctor electrode of triode VT7 after resistance R35, the polarity of minus earth electricity
Hold C21, and the polarity electricity that positive pole is connected, negative pole is connected with the colelctor electrode of triode VT7 with the output end of amplifier P6
Hold C20 composition；The minus earth of described amplifier P6；The COM pin also with process chip U for the negative pole of described polar capacitor C20
It is connected.
Further, by amplifier P4, amplifier P5, triode VT6, positive pole is through resistance R23 for described signal conditioning circuit
Be connected with the positive pole of amplifier P4 afterwards, polar capacitor C14, P pole and polarity that negative pole is connected with correction of frequency errors circuit
The diode D11 that the positive pole of electric capacity C14 is connected, N pole is connected with the emitter stage of triode VT6, positive pole is with amplifier P4's
The polar capacitor C13 that positive pole is connected, negative pole is connected with the output end of amplifier P4 after resistance R22, positive pole is through adjustable electric
Be connected with the base stage of triode VT6 after resistance R25, polarity that negative pole is connected with the output end of amplifier P4 after resistance R24
Electric capacity C15, N pole is connected with the negative pole of polar capacitor C15, P pole is connected with the colelctor electrode of triode VT6 after inductance L4
Diode D12, the polar capacitor that negative pole is connected with the positive pole of amplifier P5, positive pole is connected with the output end of amplifier P4
C16, P pole is connected with the positive pole of amplifier P5 after resistance R27, N pole is connected with the output end of amplifier P5 after resistance R28
The diode D14 connecing, the resistance that one end is connected with the positive pole of amplifier P5, the other end is connected with the N pole of diode D14
R26, positive pole is connected with the negative pole of amplifier P5 after resistance R21, the polar capacitor C17 of minus earth, and P pole is through resistance R29
Be connected with the output end of amplifier P5 afterwards, diode D13 that N pole is connected with the negative pole of amplifier P5, and one end with put
The output end of big device P5 is connected, the resistance R30 composition of other end ground connection；The grounded collector of described triode VT6；Described put
The minus earth of big device P4；The output end of described amplifier P5 is also connected with signal output amplifying circuit.
, by amplifier P1, amplifier P2, triode VT1, triode VT2, negative pole is through resistance R1 for described signal receiving circuit
Be connected with the positive pole of amplifier P1 afterwards, polar capacitor C1 that positive pole is connected with the output stage of wireless receiver W, one end with put
The resistance R2 that the negative pole of big device P1 is connected, the other end is connected with the colelctor electrode of triode VT1, positive pole is with triode VT1's
Emitter stage is connected, the polar capacitor C2 of minus earth, and P pole is connected with the colelctor electrode of triode VT1 after resistance R3, N pole
The diode D2 being connected with the negative pole of polar capacitor C2 after resistance R6, one end is connected with the negative pole of polar capacitor C2, separately
The resistance R5 that one end is connected with the positive pole of amplifier P2, positive pole is connected with the base stage of triode VT1 after inductance L1, negative pole
The polar capacitor C3 being connected with the positive pole of amplifier P2, P pole is grounded after being connected with the negative pole of amplifier P2, N pole is through resistance
The diode D3 being connected with the output end of amplifier P2 after R7, one end is connected with the base stage of triode VT2, the other end and pole
The adjustable resistance R4 that the positive pole of property electric capacity C3 is connected, and P pole be connected with the output end of amplifier P1, N pole and triode
The diode D1 composition that the emitter stage of VT2 is connected；The output end of described amplifier P2 is also connected with the colelctor electrode of triode VT2
Connect；The positive pole of described polar capacitor C3 is also connected with the negative pole of amplifier P1；The positive electrode of described amplifier P1 and process core
The VC pin of piece U is connected, its negative electrode is grounded, its output end is then also connected with the IN pin of process chip U.
Described correction of frequency errors circuit by FET MOS, the VNEG pin of triode VT4, P pole and process chip U
Be connected, diode D6 that N pole is connected with the source electrode of FET MOS, positive pole is connected with the colelctor electrode of triode VT4,
The polar capacitor C6 of minus earth, be connected with the base stage of triode VT4 after P electrode resistance R11, N pole ground connection diode D5, just
The polar capacitor C7 that pole is connected with the base stage of triode VT4, be connected with the N pole of diode D5 after negative pole resistance R10, positive pole
It is connected with the drain electrode of FET MOS after adjustable resistance R15, negative pole is connected with the N pole of diode D5 after resistance R13
Polar capacitor C9, positive pole is connected with the adjustable side of adjustable resistance R15, negative pole P pole phase with diode D5 after resistance R12
The polar capacitor C8 connecting, and one end is connected with the negative pole of polar capacitor C9, the other end is connected with the N pole of diode D5
Adjustable resistance R14 composition；The emitter stage of described triode VT4 FDBK pin and the FET MOS with process chip U respectively
Grid be connected；The positive pole of described polar capacitor C7 is also connected with the adjustable side of adjustable resistance R15；Described polar capacitor C9
Negative pole be also connected with the negative pole of polar capacitor C14.
Described signal output amplifying circuit is connected with the GPOS pin of process chip U by amplifier P3, triode VT5, P pole
Connect, diode D9 that N pole is connected with the positive pole of amplifier P3 after resistance R19, positive pole is after resistance R18 with diode D9's
The VOUT pipe of the polar capacitor C10 that N pole is connected, negative pole is connected with the VOUT pin of process chip U, P pole and process chip U
The output of the diode D7 that pin is connected, N pole is connected with the base stage of triode VT5 after resistance R16, N pole and amplifier P3
The output of the diode D8 that end is connected, P pole is connected with the negative pole of amplifier P3 after resistance R17, positive pole and amplifier P3
End is connected, polar capacitor C11 that negative pole is connected with the emitter stage of triode VT5, P pole after resistance R20 with diode D9
N pole be connected, diode D10 that N pole is connected with the output end of amplifier P3 after resistance R21, and positive pole and two poles
The polar capacitor C12 composition of ground connection after the N pole of pipe D9 is connected, negative pole is connected with the P pole of diode D10；Described amplifier
The minus earth of P3；The colelctor electrode of described triode VT5 is connected with the output end of amplifier P5；Described triode VT5 sends out
Emitter-base bandgap grading is as the output end of signal output amplifying circuit.
For the practical effect of the present invention, described process chip U then preferentially employs AD603A integrated chip and comes in fact
Existing.
The present invention compared with prior art, has advantages below and beneficial effect：
(1) present invention can eliminate to the interference electric wave signal in the signal receiving；And the present invention can also be to numeral
Many cultivations wave phase of signal or frequency error are corrected, and make data signal more steady；And can be to faint in the signal of output
Current signal or charge signal are amplified, and make signal more stable, thus improve the effect to signal transacting for the present invention, have
The accuracy that ensure that the operating position monitoring to flame system each equipment place furnace chamber for the infrared light automatic identification equipment of effect.
(2) the strong electromagnetic electric wave in electric signal can be eliminated or be suppressed by the present invention, make the electric current in electric signal
Waveform held stationary, can effectively reduce the null offset in electric signal, thus improve the effect to signal transacting of the present invention
Really.
(3) present invention can limit to the bandwidth of data signal, to filter the High-frequency Interference in data signal and spike
Burr, and the High-frequency Interference in data signal is filtered, make data signal cleaner, more steady, thus improve this
The accuracy to signal transacting for the invention.
(4) process chip U of the present invention then preferentially employs AD603A integrated chip to realize, this chip and peripheral circuit
Combine, can effectively improve stability and the reliability of the present invention.
Brief description
Fig. 1 is the overall structure diagram of the present invention.
Fig. 2 is the electrical block diagram of the signal conditioning circuit of the present invention.
Fig. 3 is the electrical block diagram of the electromagnetic interference suppression circuit of the present invention.
Specific embodiment
With reference to embodiment and its accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not
It is limited to this.
Embodiment
During enforcement, the present invention is mainly by process chip U, triode VT3, wireless receiver W, resistance R8, resistance R9, polarity
Electric capacity C4, polar capacitor C5, inductance L2, inductance L3, diode D4, electromagnetic interference suppression circuit, signal conditioning circuit, signal connects
Receive circuit, correction of frequency errors circuit, and signal output amplifying circuit composition.
During connection, the negative pole of polar capacitor C5 is connected with the GNEG pin of process chip U, and positive pole is with triode VT3's
Colelctor electrode is connected.The positive pole of polar capacitor C4 is connected with the colelctor electrode of triode VT3 after inductance L2, negative pole and triode
The emitter stage of VT3 is grounded after being connected.The N pole of diode D4 is connected with the emitter stage of triode VT3 after resistance R8, P pole
It is connected with the FDBK pin of process chip U after resistance R9.
Wherein, inductance L3 is serially connected between the VC pin of process chip U and GPOS pin.Electromagnetic interference suppression circuit concatenates
Between the base stage of triode VT3 and the COM pin of process chip U.Signal receiving circuit is serially connected in wireless receiver W and process
Between the IN pin of chip U.Correction of frequency errors circuit is connected with the VNEG pin of process chip U and FDBK pin respectively.
Signal output amplifying circuit is connected with the VOUT pin of process chip U and GPOS pin respectively.Signal conditioning circuit is serially connected in
Between correction of frequency errors circuit and signal output amplifying circuit.The VC pin also with process chip U for the described signal receiving circuit
It is connected；The GND pin ground connection of described process chip U.
During enforcement, described wireless receiver W has furnace chamber information for receiving continual the sending of transmitter module
Infrared light beam signal, the signal of reception is then converted to electric signal and is transmitted by this wireless receiver W.And described triode
VT3, resistance R8, resistance R9, polar capacitor C4, polar capacitor C5, inductance L2 and diode D4 then define electromagnetism interference device,
The extraneous electromagnetic interference signal to process chip U producing can be suppressed or be weakened, effectively really by this electromagnetism interference device
Protect the effect to signal transacting for process chip U, thus improve the treatment effect to signal for the present invention.Reality for the present invention
Border using effect, described process chip U then preferentially employs AD603A integrated chip to realize, and the VC pin of this chip is then with outward
Portion's power supply is connected, and the external power source of the present invention is 12V dc source.
Wherein, the signal receiving circuit of the present invention then eliminates to the interference electric wave signal in the signal receiving；And
The correction of frequency errors circuit of the present invention can also be corrected to many cultivations wave phase of data signal or frequency error, makes numeral letter
Number more steady.Meanwhile, the signal output amplifying circuit of the present invention can be to the low current signal in the signal of output or electric charge letter
Number being amplified, making signal more stable, thus improve the effect to signal transacting for the present invention.Described signal output is amplified
Circuit then by the digital data transmission after enhanced processing to main controller, main controller then according to wireless signal processing system transmission number
Word information obtains the technological parameter of carbon roasting furnace after being processed.Therefore the present invention can effectively guarantee infrared light automatic identification
The accuracy of the operating position monitoring to flame system each equipment place furnace chamber for the device, and then ensure that calcining carbon furnace chamber number
The real-time storage of technological parameter and historical data can be inquired about.
Further, described signal receiving circuit is by amplifier P1, amplifier P2, triode VT1, triode VT2, resistance
R1, resistance R2, resistance R3, adjustable resistance R4, resistance R5, resistance R6, resistance R7, polar capacitor C1, polar capacitor C2, polarity electricity
Hold C3, inductance L1, diode D1, diode D2, and diode D3 composition.
During connection, the negative pole of polar capacitor C1 is connected with the positive pole of amplifier P1 after resistance R1, and positive pole connects with wirelessly
The output stage receiving device W is connected.One end of resistance R2 is connected with the negative pole of amplifier P1, the collection of the other end and triode VT1
Electrode is connected.The positive pole of polar capacitor C2 is connected with the emitter stage of triode VT1, minus earth.The P pole warp of diode D2
It is connected with the colelctor electrode of triode VT1 after resistance R3, N pole is connected with the negative pole of polar capacitor C2 after resistance R6.
Wherein, one end of resistance R5 is connected with the negative pole of polar capacitor C2, and the other end is connected with the positive pole of amplifier P2
Connect.The positive pole of polar capacitor C3 is connected with the base stage of triode VT1 after inductance L1, and negative pole is connected with the positive pole of amplifier P2
Connect.The P pole of diode D3 is grounded after being connected with the negative pole of amplifier P2, N pole output end with amplifier P2 after resistance R7
It is connected.One end of adjustable resistance R4 is connected with the base stage of triode VT2, and the other end is connected with the positive pole of polar capacitor C3
Connect.The P pole of diode D1 is connected with the output end of amplifier P1, and N pole is connected with the emitter stage of triode VT2.
The output end of described amplifier P2 is also connected with the colelctor electrode of triode VT2；The positive pole of described polar capacitor C3
Also it is connected with the negative pole of amplifier P1；The positive electrode of described amplifier P1 is connected with the VC pin of process chip U, its negative electricity
Pole is grounded, and its output end is then also connected with the IN pin of process chip U.
Further, described correction of frequency errors circuit is by FET MOS, triode VT4, resistance R10, resistance
R11, resistance R12, resistance R13, adjustable resistance R14, adjustable resistance R15, polar capacitor C polar capacitor C6, polar capacitor C7, pole
Property electric capacity C8, polar capacitor C9, diode D5, and diode D6 composition.
During connection, the P pole of diode D6 is connected with the VNEG pin of process chip U, the source of N pole and FET MOS
Pole is connected.The positive pole of polar capacitor C6 is connected with the colelctor electrode of triode VT4, minus earth.The P electrode resistance of diode D5
It is connected with the base stage of triode VT4 after R11, N pole is grounded.The positive pole of polar capacitor C7 is connected with the base stage of triode VT4,
It is connected with the N pole of diode D5 after negative pole resistance R10.
Meanwhile, the positive pole of polar capacitor C9 is connected with the drain electrode of FET MOS after adjustable resistance R15, negative pole warp
It is connected with the N pole of diode D5 after resistance R13.The positive pole of polar capacitor C8 is connected with the adjustable side of adjustable resistance R15, bears
Pole is connected with the P pole of diode D5 after resistance R12.One end of adjustable resistance R14 is connected with the negative pole of polar capacitor C9,
The other end is connected with the N pole of diode D5.
The emitter stage of described triode VT4 is connected with the FDBK pin of process chip U and the grid of FET MOS respectively
Connect；The positive pole of described polar capacitor C7 is also connected with the adjustable side of adjustable resistance R15；The negative pole of described polar capacitor C9 also with
The negative pole of polar capacitor C14 is connected.
Yet further, described signal output amplifying circuit is by amplifier P3, triode VT5, resistance R16, resistance R17,
Resistance R18, resistance R19, resistance R20, resistance R21, polar capacitor C10, polar capacitor C11, polar capacitor C12, diode D8,
Diode D9, and diode D10 composition.
During connection, the P pole of diode D9 is connected with the GPOS pin of process chip U, N pole after resistance R19 with amplification
The positive pole of device P3 is connected.The positive pole of polar capacitor C10 is connected with the N pole of diode D9 after resistance R18, negative pole and process
The VOUT pin of chip U is connected.The P pole of diode D7 is connected with the VOUT pin of process chip U, and N pole is after resistance R16
It is connected with the base stage of triode VT5.The N pole of diode D8 is connected with the output end of amplifier P3, and P pole is after resistance R17
It is connected with the negative pole of amplifier P3.
Meanwhile, the positive pole of polar capacitor C11 is connected with the output end of amplifier P3, the transmitting of negative pole and triode VT5
Pole is connected.The P pole of diode D10 is connected with the N pole of diode D9 after resistance R20, N pole after resistance R21 with amplification
The output end of device P3 is connected.The positive pole of polar capacitor C12 is connected with the N pole of diode D9, the P of negative pole and diode D10
Pole is grounded after being connected.The minus earth of described amplifier P3；The colelctor electrode of described triode VT5 and the output end of amplifier P5
It is connected；The emitter stage of described triode VT5 is as the output end of signal output amplifying circuit.
As shown in Fig. 2 described signal conditioning circuit is by amplifier P4, amplifier P5, triode VT6, resistance R22, resistance
R23, resistance R24, adjustable resistance R25, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, polar capacitor C13,
Polar capacitor C14, polar capacitor C15, polar capacitor C16, polar capacitor C17, diode D11, diode D12, diode
D13, diode D14, and inductance L4 form.
During connection, the positive pole of polar capacitor C14 is connected with the positive pole of amplifier P4 after resistance R23, negative pole and frequency
Error correction circuit is connected.The P pole of diode D11 is connected with the positive pole of polar capacitor C14, and N pole is sent out with triode VT6's
Emitter-base bandgap grading is connected.The positive pole of polar capacitor C13 is connected with the positive pole of amplifier P4, negative pole after resistance R22 with amplifier P4
Output end be connected.The positive pole of polar capacitor C15 is connected with the base stage of triode VT6 after adjustable resistance R25, negative pole warp
It is connected with the output end of amplifier P4 after resistance R24.
Wherein, the N pole of diode D12 is connected with the negative pole of polar capacitor C15, P pole after inductance L4 with triode VT6
Colelctor electrode be connected.The negative pole of polar capacitor C16 is connected with the positive pole of amplifier P5, the output end of positive pole and amplifier P4
It is connected.The P pole of diode D14 is connected with the positive pole of amplifier P5 after resistance R27, N pole after resistance R28 with amplifier
The output end of P5 is connected.One end of resistance R26 is connected with the positive pole of amplifier P5, the N pole phase of the other end and diode D14
Connect.
Meanwhile, the positive pole of polar capacitor C17 is connected with the negative pole of amplifier P5 after resistance R21, minus earth.Two poles
The P pole of pipe D13 is connected with the output end of amplifier P5 after resistance R29, and N pole is connected with the negative pole of amplifier P5.Resistance
One end of R30 is connected with the output end of amplifier P5, and the other end is grounded.The grounded collector of described triode VT6；Described put
The minus earth of big device P4；The output end of described amplifier P5 is also connected with signal output amplifying circuit.
As shown in figure 3, described electromagnetic interference suppression circuit is by amplifier P6, triode VT7, adjustable resistance R31, resistance
R32, resistance R33, resistance R34, resistance R35, resistance R36, adjustable resistance R37, polar capacitor C18, polar capacitor C19, polarity
Electric capacity C20, polar capacitor C21, diode D15, diode D16, diode D17, and inductance L5 form.
During connection, the N pole of diode D15 is connected with the positive pole of amplifier P6 after resistance R33, P pole and triode VT3
Base stage be connected.The negative pole of polar capacitor C18 is connected with the positive pole of amplifier P6, and positive pole is after adjustable resistance R31 with three
The base stage of pole pipe VT3 is connected.One end of resistance R34 is connected with the N pole of diode D15, and the other end is grounded.Polar capacitor
The negative pole of C19 is connected with the emitter stage of triode VT7, and positive pole is connected with the positive pole of amplifier P6 after inductance L5.
Wherein, the N pole of diode D16 is connected with the positive pole of amplifier P6, and P pole is after resistance R32 with triode VT7's
Base stage is connected.The N pole of diode D17 is connected with the output end of amplifier P6 after resistance R36, and P pole is with amplifier P6's
Negative pole is connected.One end of adjustable resistance R37 is connected with the negative pole of amplifier P6, the output end phase of the other end and amplifier P6
Connect.
Meanwhile, the positive pole of polar capacitor C21 is connected with the colelctor electrode of triode VT7 after resistance R35, minus earth.
The positive pole of polar capacitor C20 is connected with the output end of amplifier P6, and negative pole is connected with the colelctor electrode of triode VT7.Described
The minus earth of amplifier P6；The negative pole of described polar capacitor C20 is also connected with the COM pin of process chip U.
During operation, polar capacitor C1 in the signal receiving circuit of the present invention is as filter capacitor by wireless receiver W institute
Low frequency signal in the electric signal of transmission is eliminated or is suppressed, and the amplifier P1 of this signal receiving circuit and amplifier P2 shape
Become second order impedor, this second order impedor eliminates to the interference electric wave signal in electric signal, made the electric wave frequency of electric signal
Rate is more stable；Wherein, the correction of frequency errors circuit of the present invention then process chip U conversion after generate data signal many cultivations
Wave phase or frequency error are corrected, and make data signal more steady.Meanwhile, the signal output amplifying circuit of the present invention is to frequency
Low current signal in the data signal of error correction circuit transmission or charge signal are amplified, and make the level frequent of signal
More stable, thus improve the effect to signal transacting for the present invention.Described signal output amplifying circuit is then by enhanced processing
Digital data transmission afterwards to main controller, main controller then according to wireless signal processing system transmission digital information processed after
Obtain the technological parameter of carbon roasting furnace, and then ensure that real-time storage and the history number of the technological parameter of calcining carbon furnace chamber number
According to can be inquired about.
Wherein, the present invention, in order to be able to being eliminated to the strong electromagnetic electric wave in electric signal or suppressing, makes in electric signal
Current waveform held stationary, the null offset in electric signal can be effectively reduced, therefore in base stage and the process of triode VT3
It is provided with electromagnetic interference suppression circuit between the COM pin of chip U.The diode D15 of this electromagnetic interference suppression circuit, polarity electricity
Hold C18, resistance R33 and adjustable resistance R31 defines high resistance circuit, this high resistance circuit can be effectively by the strong electromagnetic in electric signal
Interference electric wave is eliminated or is suppressed；The regulation that amplifier P6, polar capacitor C5, inductance L5 and adjustable resistance R37 are formed simultaneously
Device, this adjuster can be adjusted to the pulsation of signal level, can effectively reduce the null offset in electric signal, make electric signal
Ordinary telegram be consistent, even if electric signal is more stable, this electromagnetic interference suppression circuit can effectively make electric signal keep stable
State, thus improve the effect to signal transacting of the present invention.
Meanwhile, the present invention is adjusted for the data signal that process chip U is exported, then in correction of frequency errors circuit
It is provided with signal conditioning circuit and signal output amplifying circuit between.The triode VT6 of this signal conditioning circuit, electric capacity C15, can
Adjust resistance R25, inductance L4 and diode D12 constitute a biasing circuit, amplifier P4, polar capacitor C13, resistance R22 with
And resistance R2 forms a pre-amplification circuit, this biasing circuit and pre-amplification circuit combine can be with distortionless to numeral
Signal is amplified.Polar capacitor C16 therein is capacitance, and polar capacitor C13 can be to the band of pre-amplification circuit
Width is limited, to filter the High-frequency Interference in data signal and spike burr.Meanwhile, amplifier P5, polar capacitor C17 and electricity
Resistance R21 diode D13, diode D14 and resistance R26 constitute a harmonic device, and this harmonic device can be further to flow velocity
High-frequency Interference in data signal is filtered, and this signal conditioning circuit can be nursed one's health to data signal, makes data signal more
Stable, thus improve the effect to signal transacting for the present invention.
According to above-described embodiment, you can realize the present invention well.
Claims (7)
1. a kind of roaster infrared light identifying device current waveform adjustable signal processing system it is characterised in that main by
Reason chip U, triode VT3, wireless receiver W, negative pole is connected with the GNEG pin of process chip U, positive pole and triode VT3
The polar capacitor C5 that is connected of colelctor electrode, positive pole is connected with the colelctor electrode of triode VT3 after inductance L2, negative pole and three poles
The emitter stage of pipe VT3 be connected after ground connection polar capacitor C4, N pole is connected with the emitter stage of triode VT3 after resistance R8,
The diode D4 that P pole is connected with the FDBK pin of process chip U after resistance R9, be serially connected in the VC pin of process chip U with
Inductance L3 between GPOS pin, is serially connected in the electromagnetic interference between the base stage of triode VT3 and the COM pin of process chip U
Suppression circuit, is serially connected in the signal receiving circuit between wireless receiver W and the IN pin of process chip U, respectively with process core
The correction of frequency errors circuit that the VNEG pin of piece U is connected with FDBK pin, respectively with the VOUT pin of process chip U and
The signal output amplifying circuit that GPOS pin is connected, and it is serially connected in correction of frequency errors circuit and signal output amplifying circuit
Between signal conditioning circuit composition；Described signal receiving circuit is also connected with the VC pin of process chip U；Described process core
Its GND pin ground connection of piece U.
2. a kind of roaster infrared light identifying device current waveform adjustable signal processing system according to claim 1,
It is characterized in that, described electromagnetic interference suppression circuit by amplifier P6, triode VT7, N pole after resistance R33 with amplifier P6
Positive pole be connected, diode D15 that P pole is connected with the base stage of triode VT3, negative pole is connected with the positive pole of amplifier P6
Connect, polar capacitor C18 that positive pole is connected with the base stage of triode VT3 after adjustable resistance R31, the N of one end and diode D15
Pole is connected, the other end ground connection resistance R34, negative pole is connected with the emitter stage of triode VT7, positive pole after inductance L5 with put
The polar capacitor C19 that the positive pole of big device P6 is connected, N pole is connected with the positive pole of amplifier P6, P pole after resistance R32 with three
The diode D16 that the base stage of pole pipe VT7 is connected, N pole is connected with the output end of amplifier P6 after resistance R36, P pole with put
The diode D17 that the negative pole of big device P6 is connected, one end is connected with the negative pole of amplifier P6, the other end and amplifier P6 defeated
Go out the adjustable resistance R37 that end is connected, positive pole is connected with the colelctor electrode of triode VT7 after resistance R35, the pole of minus earth
Property electric capacity C21, and the pole that positive pole is connected with the output end of amplifier P6, negative pole is connected with the colelctor electrode of triode VT7
Property electric capacity C20 composition；The minus earth of described amplifier P6；The COM also with process chip U for the negative pole of described polar capacitor C20
Pin is connected.
3. a kind of roaster infrared light identifying device current waveform adjustable signal processing system according to claim 2,
It is characterized in that, described signal conditioning circuit by amplifier P4, amplifier P5, triode VT6, positive pole after resistance R23 with put
The polar capacitor C14 that the positive pole of big device P4 is connected, negative pole is connected with correction of frequency errors circuit, P pole and polar capacitor C14
Positive pole be connected, diode D11 that N pole is connected with the emitter stage of triode VT6, positive pole is connected with the positive pole of amplifier P4
Connect, polar capacitor C13 that negative pole is connected with the output end of amplifier P4 after resistance R22, positive pole after adjustable resistance R25 with
The base stage of triode VT6 is connected, negative pole is connected with the output end of amplifier P4 after resistance R24 polar capacitor C15, N
The diode that pole is connected with the negative pole of polar capacitor C15, P pole is connected with the colelctor electrode of triode VT6 after inductance L4
D12, the polar capacitor C16 that negative pole is connected with the positive pole of amplifier P5, positive pole is connected with the output end of amplifier P4, P pole
It is connected with the positive pole of amplifier P5 after resistance R27, N pole is connected with the output end of amplifier P5 after resistance R28 two
Pole pipe D14, the resistance R26 that one end is connected with the positive pole of amplifier P5, the other end is connected with the N pole of diode D14, positive pole
Be connected with the negative pole of amplifier P5 after resistance R21, the polar capacitor C17 of minus earth, P pole after resistance R29 with amplification
The diode D13 that the output end of device P5 is connected, N pole is connected with the negative pole of amplifier P5, and one end is with amplifier P5's
Output end is connected, the resistance R30 composition of other end ground connection；The grounded collector of described triode VT6；Described amplifier P4's
Minus earth；The output end of described amplifier P5 is also connected with signal output amplifying circuit.
4. a kind of roaster infrared light identifying device current waveform adjustable signal processing system according to claim 3,
It is characterized in that, by amplifier P1, amplifier P2, triode VT1, triode VT2, negative pole is through resistance for described signal receiving circuit
Be connected with the positive pole of amplifier P1 after R1, polar capacitor C1 that positive pole is connected with the output stage of wireless receiver W, one end with
The resistance R2 that the negative pole of amplifier P1 is connected, the other end is connected with the colelctor electrode of triode VT1, positive pole and triode VT1
Emitter stage be connected, the polar capacitor C2 of minus earth, P pole is connected with the colelctor electrode of triode VT1 after resistance R3, N
The diode D2 that pole is connected with the negative pole of polar capacitor C2 after resistance R6, one end is connected with the negative pole of polar capacitor C2,
The resistance R5 that the other end is connected with the positive pole of amplifier P2, positive pole is connected with the base stage of triode VT1 after inductance L1, bears
The polar capacitor C3 that pole is connected with the positive pole of amplifier P2, P pole is grounded after being connected with the negative pole of amplifier P2, N pole is through electricity
The diode D3 that is connected with the output end of amplifier P2 after resistance R7, one end is connected with the base stage of triode VT2, the other end and
The adjustable resistance R4 that the positive pole of polar capacitor C3 is connected, and P pole be connected with the output end of amplifier P1, N pole and three poles
The diode D1 composition that the emitter stage of pipe VT2 is connected；The colelctor electrode phase also with triode VT2 for the output end of described amplifier P2
Connect；The positive pole of described polar capacitor C3 is also connected with the negative pole of amplifier P1；The positive electrode of described amplifier P1 and process
The VC pin of chip U is connected, its negative electrode is grounded, its output end is then also connected with the IN pin of process chip U.
5. a kind of roaster infrared light identifying device current waveform adjustable signal processing system according to claim 4,
It is characterized in that, by FET MOS, the VNEG of triode VT4, P pole and process chip U manages described correction of frequency errors circuit
The diode D6 that pin is connected, N pole is connected with the source electrode of FET MOS, positive pole is connected with the colelctor electrode of triode VT4
Connect, the polar capacitor C6 of minus earth, be connected with the base stage of triode VT4 after P electrode resistance R11, N pole ground connection diode
D5, positive pole is connected with the base stage of triode VT4, the polar capacitor that is connected with the N pole of diode D5 after negative pole resistance R10
C7, positive pole is connected with the drain electrode of FET MOS after adjustable resistance R15, negative pole N with diode D5 after resistance R13
The polar capacitor C9 that pole is connected, positive pole is connected with the adjustable side of adjustable resistance R15, negative pole after resistance R12 with diode
The polar capacitor C8 that the P pole of D5 is connected, and one end be connected with the negative pole of polar capacitor C9, the other end and diode D5
The adjustable resistance R14 composition that N pole is connected；The emitter stage of described triode VT4 FDBK pin and the field with process chip U respectively
The grid of effect pipe MOS is connected；The positive pole of described polar capacitor C7 is also connected with the adjustable side of adjustable resistance R15；Described
The negative pole of polar capacitor C9 is also connected with the negative pole of polar capacitor C14.
6. a kind of roaster infrared light identifying device current waveform adjustable signal processing system according to claim 5,
It is characterized in that, described signal output amplifying circuit by amplifier P3, the GPOS pin of triode VT5, P pole and process chip U
Be connected, diode D9 that N pole is connected with the positive pole of amplifier P3 after resistance R19, positive pole after resistance R18 with diode
The polar capacitor C10 that the N pole of D9 is connected, negative pole is connected with the VOUT pin of process chip U, P pole and process chip U
The diode D7 that VOUT pin is connected, N pole is connected with the base stage of triode VT5 after resistance R16, N pole and amplifier P3
Output end be connected, diode D8 that P pole is connected with the negative pole of amplifier P3 after resistance R17, positive pole and amplifier P3
Output end be connected, polar capacitor C11 that negative pole is connected with the emitter stage of triode VT5, P pole is after resistance R20 with two
The diode D10 that the N pole of pole pipe D9 is connected, N pole is connected with the output end of amplifier P3 after resistance R21, and positive pole
Be connected with the N pole of diode D9, negative pole be connected with the P pole of diode D10 after ground connection polar capacitor C12 composition；Described
The minus earth of amplifier P3；The colelctor electrode of described triode VT5 is connected with the output end of amplifier P5；Described triode
The emitter stage of VT5 is as the output end of signal output amplifying circuit.
7. a kind of roaster infrared light identifying device current waveform adjustable signal processing system according to claim 6,
It is characterized in that, described process chip U is AD603A integrated chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610749843.0A CN106441089A (en) | 2016-08-29 | 2016-08-29 | Current waveform adjustable signal processing system for roasting furnace infrared light recognition device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610749843.0A CN106441089A (en) | 2016-08-29 | 2016-08-29 | Current waveform adjustable signal processing system for roasting furnace infrared light recognition device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106441089A true CN106441089A (en) | 2017-02-22 |
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ID=58182746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610749843.0A Withdrawn CN106441089A (en) | 2016-08-29 | 2016-08-29 | Current waveform adjustable signal processing system for roasting furnace infrared light recognition device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106441089A (en) |
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2016
- 2016-08-29 CN CN201610749843.0A patent/CN106441089A/en not_active Withdrawn
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Application publication date: 20170222 |