CN105915760A - High-definition image signal processing system based on passive compensating circuit - Google Patents
High-definition image signal processing system based on passive compensating circuit Download PDFInfo
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- CN105915760A CN105915760A CN201610393460.4A CN201610393460A CN105915760A CN 105915760 A CN105915760 A CN 105915760A CN 201610393460 A CN201610393460 A CN 201610393460A CN 105915760 A CN105915760 A CN 105915760A
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- pole
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- audion
- pin
- polar capacitor
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/148—Video amplifiers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
Abstract
The invention discloses a high-definition image signal processing system based on a passive compensating circuit. The system is characterized in that the system is mainly formed by an image collector, a processing chip U, a polarity capacitor C5, a diode D3, a signal amplification circuit, a resistor R11, a resistor R12, a signal noise prevention filter circuit and the passive compensating circuit, wherein one end of the resistor R11 is connected to an N pole of the diode D3 and the other end of the resistor R11 is connected to a CE base pin of the processing chip U; one end of the resistor R12 is connected to an AGND base pin of the processing chip U and the other end of the resistor R12 is connected to a DGND base pin of the processing chip U and then is grounded; the signal noise prevention filter circuit is connected to an REF base pin and a PIN2 base pin of the processing chip U respectively; and the passive compensating circuit is connected in series between an RC base pin of the processing chip U and a signal amplification circuit. By using the system, a processed image signal is amplified and output and a frequency bandwidth of the image signal become large so that an input terminal image signal and a sampling signal maintain to be consistent and image display can be effectively prevented from distortion.
Description
Technical field
The present invention relates to electronic applications, specifically, be a kind of high-definition image based on Passively compensated circuit letter
Number processing system.
Background technology
Along with the constantly development of society's science and technology, image processing system has been widely used in recognition of face, has taken the photograph
The fields such as shadow shooting；But, there is noise control poor performance in current image processing system, and to picture signal
Process inaccurate defect, thus cause image to show and distortion, unclear problem occur, it is impossible to meet people
Requirement.
Therefore it provides one can improve noise control performance, can ensure that again and picture signal is processed image accurately
Processing system is the task of top priority.
Summary of the invention
It is an object of the invention to overcome image processing system of the prior art to there is noise control poor performance, to figure
Image signal process inaccurate defect, it is provided that a kind of based on Passively compensated circuit high-definition image signal processing
System.
The present invention is achieved through the following technical solutions: a kind of high-definition image signal based on Passively compensated circuit
Processing system, mainly by image acquisition device, processes chip U, positive pole after resistance R9 with process chip U
CS pin is connected, polar capacitor C5, the P pole of minus earth is connected with the RC pin processing chip U,
The diode D3 that N pole negative pole with polar capacitor C5 after resistance R10 is connected, one end and diode D3
The resistance R11 that N pole is connected, the other end is connected with the CE pin of process chip U, one end and place
After the AGND pin of reason chip U is connected, the other end is connected with the DGND pin of process chip U
The resistance R12 of ground connection, the signal being connected with the REF pin processing chip U and PIN2 pin respectively is prevented
Make an uproar filter circuit, be connected with the AO pin processing chip U and DB1 pin and DB2 pin respectively
Signal amplification circuit, and be serially connected in process chip U RC pin and signal amplification circuit between nothing
Source compensates circuit composition；Described signal noise control filter circuit is connected with signal amplification circuit；Described image is adopted
Storage is connected with signal noise control filter circuit.
Described Passively compensated circuit is by field effect transistor MOS, amplifier P3, audion VT3, and positive pole is sequentially
Be connected through resistance R18 source electrode with field effect transistor MOS after resistance R17, negative pole is after resistance R20
The polar capacitor C7 being connected with the drain electrode of field effect transistor MOS, positive pole after resistance R19 with field effect transistor
The polarity electricity that the source electrode of MOS is connected, negative pole colelctor electrode with audion VT3 after resistance R23 is connected
Holding C8, one end is connected with the grid of field effect transistor MOS, the colelctor electrode phase of the other end and audion VT3
Inductance L2, the N pole connected is connected with the electrode input end of amplifier P3, P pole and polar capacitor C8
The diode D5 that positive pole is connected, negative pole outfan with amplifier P3 after resistance R25 is connected, just
Polar capacitor C9, P pole that pole negative input with amplifier P3 after resistance R24 is connected and polarity
Two poles that the negative pole of electric capacity C9 is connected, N pole base stage with audion VT3 after resistance R22 is connected
Pipe D7, positive pole is connected with the emitter stage of audion VT3, after negative pole resistance R26 with polar capacitor C9's
The polar capacitor C10 that positive pole is connected, one end is connected with the negative pole of polar capacitor C10, the other end and two
The adjustable resistance R27 that the P pole of pole pipe D7 is connected, and P pole is connected with the colelctor electrode of audion VT3
Connect, diode D6 composition that N pole negative pole with polar capacitor C7 after resistance R21 is connected；Described pole
The property negative pole of electric capacity C7 be connected with the negative pole of polar capacitor C10 after ground connection；Described adjustable resistance R27's
Adjustable end as the outfan of Passively compensated circuit and is connected with signal amplification circuit；Described field effect transistor
The source electrode of MOS as the input of Passively compensated circuit and is connected with the RC pin processing chip U.
Described signal noise control filtered electrical routing amplifier P1, audion VT1, audion VT2, positive pole with
The base stage of audion VT1 is connected, negative pole electrode input end with amplifier P1 after resistance R5 is connected
Polar capacitor C1, one end is connected with the base stage of audion VT1, the collection of the other end and audion VT1
The resistance R1 that electrode is connected, one end is connected with the colelctor electrode of audion VT1, the other end and audion
The resistance R4 that the colelctor electrode of VT2 is connected, negative pole emitter stage with audion VT1 after resistance R3 is connected
Connect, polar capacitor C2, N pole that positive pole is connected with the PIN2 pin of process chip U with process chip U
The diode that PIN2 pin is connected, P pole emitter stage with audion VT1 after resistance R2 is connected
D2, one end is connected with the emitter stage of audion VT2, the PIN2 pin phase of the other end and process chip U
Connect inductance L, P pole be connected with the negative input of amplifier P1, N pole after resistance R6 with amplification
The diode D1 that the outfan of device P1 is connected, negative pole is connected with the negative input of amplifier P1 and is followed by
Ground, the polar capacitor C3 that is connected with diode D1N pole after resistance R7 of positive pole, and negative pole and process
The pole that the REF pin of chip U is connected, positive pole is connected with the N pole of diode D1 after resistance R8
Property electric capacity C4 composition；The base stage of described audion VT2 is connected with the negative pole of polar capacitor C2；Described pole
The negative pole of property electric capacity C1 is as the input of signal noise control filter circuit；The colelctor electrode of described audion VT2
It is connected with signal amplification circuit.
Described signal amplification circuit is connected with the colelctor electrode of audion VT2 by amplifier P2, P pole and is followed by
The diode D4 that ground, N pole are connected with the AO pin processing chip U, one end and the N of diode D4
The resistance R14 that pole is connected, the other end is connected with the electrode input end of amplifier P2, negative pole and amplifier
The polar capacitor C6 that the electrode input end of P2 is connected, positive pole is connected with the DB2 pin of process chip U,
One end is connected with the electrode input end of amplifier P2, the other end is connected with the outfan with amplifier P2
Adjustable resistance R15, one end is connected with the negative pole of polar capacitor C6, the other end and process chip U
The resistance R13 that DB1 pin is connected, and one end is connected with the negative input of amplifier P2, another
The resistance R16 composition that termination is connected with the adjustable end of adjustable resistance R27；The outfan of described amplifier P2
Outfan as signal amplification circuit.
For the practical effect of the present invention, described process chip U the most preferentially uses the integrated core of AD574A
Sheet realizes.
The present invention compared with prior art, has the following advantages and beneficial effect:
(1) the interference current wave during the present invention can effectively eliminate the picture signal of input, effectively eliminates
Garbage signal frequency in picture signal, makes picture signal to transmit smoothly, ensures that energy of the present invention
Picture signal is processed accurately.
(2) low frequency signal of picture signal can be adjusted by the present invention, makes low frequency signal and high-frequency signal
Frequency fluctuation is identical, thus improves the accuracy that picture signal is processed by the present invention, thus prevents image
The situation of distortion occurs during display.
(3) present invention can export after the picture signal after processing being amplified, and makes the frequency band of picture signal
Wide change is big, so that input picture signal keeps consistent with sampled signal, is effectively prevented image and shows
The situation of distortion occurs.
(4) within image fault rate effectively can be dropped to 2% by the present invention, thus the present invention can meet people and exist
The field such as recognition of face, photography and vedio recording can obtain the demand of high-definition image.
(5) the integrated chip of AD574A that present invention employs stable performance is used as processing chip, effectively
Improve the stability that picture signal is processed by the present invention.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of the present invention.
Fig. 2 is the electrical block diagram of the Passively compensated circuit of the present invention.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is described in further detail, but the enforcement of the present invention
Mode is not limited to this.
Embodiment
As it is shown in figure 1, the present invention is mainly by image acquisition device, process chip U, resistance R9, resistance R10,
Resistance R11, resistance R12, polar capacitor C5, diode D3, Passively compensated circuit, signal noise control filters
Circuit, and signal amplification circuit composition.
During enforcement, the positive pole of polar capacitor C5 after resistance R9 with process chip U CS pin be connected,
Its minus earth.The P pole of diode D3 is connected with the RC pin processing chip U, its N pole is through electricity
It is connected with the negative pole of polar capacitor C5 after resistance R10.The N pole phase of one end of resistance R11 and diode D3
Connect, its other end is connected with the CE pin processing chip U.One end of resistance R12 and process chip
Ground connection after the AGND pin of U is connected, its other end is connected with the DGND pin processing chip U.
Signal noise control filter circuit is connected with the REF pin processing chip U and PIN2 pin respectively.Signal is put
Being connected with the AO pin processing chip U and DB1 pin and DB2 pin respectively of big circuit.Nothing
Source compensates circuit and is serially connected between RC pin and the signal amplification circuit processing chip U.Described signal noise control
Filter circuit is connected with signal amplification circuit；Described image acquisition device is connected with signal noise control filter circuit.
Wherein, described signal noise control filtered electrical routing amplifier P1, audion VT1, audion VT2,
Resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8,
Polar capacitor C1, polar capacitor C2, polar capacitor C3, polar capacitor C4, diode D1, diode
D2, and inductance L composition.
During connection, the positive pole of polar capacitor C1 is connected with the base stage of audion VT1, its negative pole is through resistance
After R5, the electrode input end with amplifier P1 is connected.One end of resistance R1 and the base stage of audion VT1
Be connected, its other end is connected with the colelctor electrode of audion VT1.One end of resistance R4 and audion VT1
Colelctor electrode be connected, its other end is connected with the colelctor electrode of audion VT2.Polar capacitor C2's is negative
Pole emitter stage with audion VT1 after resistance R3 is connected, its positive pole and the PIN2 processing chip U
Pin is connected.The N pole of diode D2 is connected with the PIN2 pin processing chip U, its P pole is through electricity
It is connected with the emitter stage of audion VT1 after resistance R2.
Meanwhile, one end of inductance L be connected with the emitter stage of audion VT2, its other end with process core
The PIN2 pin of sheet U is connected.The P pole of diode D1 is connected with the negative input of amplifier P1,
Its N pole outfan with amplifier P1 after resistance R6 is connected.The negative pole of polar capacitor C3 and amplification
After the negative input of device P1 is connected, ground connection, its positive pole are connected with diode D1N pole after resistance R7.
The negative pole of polar capacitor C4 with process chip U REF pin be connected, its positive pole after resistance R8 with two
The N pole of pole pipe D1 is connected.
The base stage of described audion VT2 is connected with the negative pole of polar capacitor C2；Described polar capacitor C1
Negative pole as the input of signal noise control filter circuit and be connected with image acquisition device；Described audion
The colelctor electrode of VT2 is connected with signal amplification circuit.
Meanwhile, described signal amplification circuit is by amplifier P2, resistance R13, resistance R14, adjustable resistance
R15, resistance R16, polar capacitor C6, and diode D4 form.
During connection, the P pole of diode D4 be connected with the colelctor electrode of audion VT2 after ground connection, its N pole
It is connected with the AO pin processing chip U.One end of resistance R14 is connected with the N pole of diode D4,
Its other end is connected with the electrode input end of amplifier P2.The negative pole of polar capacitor C6 is with amplifier P2's
Electrode input end is connected, its positive pole is connected with the DB2 pin processing chip U.
Wherein, one end of adjustable resistance R15 be connected with the electrode input end of amplifier P2, its other end
It is connected with the outfan with amplifier P2.One end of resistance R13 is connected with the negative pole of polar capacitor C6,
Its other end is connected with the DB1 pin processing chip U.One end of resistance R16 is negative with amplifier P2's
Pole input is connected, its another termination is connected with the adjustable end of adjustable resistance R27.Described amplifier P2
Outfan as the outfan of signal amplification circuit and be connected with image display device.
As in figure 2 it is shown, described Passively compensated circuit is by field effect transistor MOS, amplifier P3, audion VT3,
Resistance R17, resistance R18, resistance R19, resistance R20, resistance R21, resistance R22, resistance R23,
Resistance R24, resistance R25, resistance R26, adjustable resistance R27, polar capacitor C7, polar capacitor C8,
Polar capacitor C9, polar capacitor C10, diode D5, diode D6, diode D7, and inductance
L2 forms.
During connection, the positive pole of polar capacitor C7 sequentially after resistance R18 and resistance R17 with field effect transistor
The source electrode of MOS is connected, the drain electrode with field effect transistor MOS after resistance R20 of its negative pole is connected.Pole
The positive pole of property electric capacity C8 source electrode with field effect transistor MOS after resistance R19 is connected, its negative pole is through resistance
After R23, the colelctor electrode with audion VT3 is connected.One end of inductance L2 and the grid of field effect transistor MOS
Be connected, its other end is connected with the colelctor electrode of audion VT3.The N pole of diode D5 and amplifier
The electrode input end of P3 is connected, its P pole is connected with the positive pole of polar capacitor C8.
Meanwhile, the negative pole of polar capacitor C9 outfan with amplifier P3 after resistance R25 be connected, its
Positive pole negative input with amplifier P3 after resistance R24 is connected.The P pole of diode D7 and polarity
The negative pole of electric capacity C9 is connected, its N pole base stage with audion VT3 after resistance R22 is connected.Pole
Property the positive pole of electric capacity C10 be connected with the emitter stage of audion VT3, after its negative pole resistance R26 with polarity electricity
The positive pole holding C9 is connected.One end of adjustable resistance R27 is connected with the negative pole of polar capacitor C10, it
The other end is connected with the P pole of diode D7.The P pole of diode D6 and the colelctor electrode phase of audion VT3
Connect, its N pole negative pole with polar capacitor C7 after resistance R21 is connected.
The negative pole of described polar capacitor C7 be connected with the negative pole of polar capacitor C10 after ground connection；Described adjustable
The adjustable end of resistance R27 as the outfan of Passively compensated circuit and is connected with signal amplification circuit；Described
The source electrode of field effect transistor MOS as Passively compensated circuit input and with process chip U RC pin phase
Connect.
During operation, the present invention can export after the picture signal after processing being amplified simultaneously, makes picture signal
Frequency bandwidth becomes big, so that input picture signal keeps consistent with sampled signal, is effectively prevented figure
As the situation of distortion occurs in display.Meanwhile, the low frequency signal of picture signal can be adjusted by the present invention, makes
Low frequency signal is identical with the frequency fluctuation of high-frequency signal, thus improves the standard that picture signal is processed by the present invention
, there is the situation of distortion in really property when being effectively prevented image display.
Within image fault rate effectively can be dropped to 2% by the present invention, thus the present invention can meet people at face
The fields such as identification, photography and vedio recording can obtain the demand of high-definition image.In order to preferably implement the present invention, described
Process chip U the most preferentially have employed the integrated chip of AD574A of stable performance and realizes, and effectively raises
The stability that picture signal is processed by the present invention.
According to above-described embodiment, can well realize the present invention.
Claims (5)
1. a high-definition image signal processing system based on Passively compensated circuit, it is characterised in that main
By image acquisition device, process chip U, positive pole is connected with the CS pin processing chip U after resistance R9,
Polar capacitor C5, the P pole of minus earth is connected with the RC pin processing chip U, N pole is through resistance R10
The diode D3 that negative pole with polar capacitor C5 is connected afterwards, one end is connected with the N pole of diode D3,
The resistance R11 that the other end is connected with the CE pin processing chip U, one end and the AGND processing chip U
The resistance R12 of ground connection after pin is connected, the other end is connected with the DGND pin of process chip U, point
The signal noise control filter circuit not being connected with REF pin and the PIN2 pin of process chip U, respectively with
Process the signal amplification circuit that the AO pin of chip U is connected with DB1 pin and DB2 pin, with
And the Passively compensated circuit composition being serially connected between the RC pin and the signal amplification circuit that process chip U；Institute
State signal noise control filter circuit to be connected with signal amplification circuit；Described image acquisition device filters with signal noise control
Circuit is connected.
A kind of high-definition image of based on Passively compensated circuit the most according to claim 1 signal processing system
System, it is characterised in that described Passively compensated circuit by field effect transistor MOS, amplifier P3, audion VT3,
Positive pole is sequentially connected through resistance R18 source electrode with field effect transistor MOS after resistance R17, negative pole is through electricity
The polar capacitor C7 that is connected with the drain electrode of field effect transistor MOS after resistance R20, positive pole after resistance R19 with
The source electrode of field effect transistor MOS is connected, negative pole colelctor electrode with audion VT3 after resistance R23 is connected
The polar capacitor C8 connect, one end is connected with the grid of field effect transistor MOS, the other end and audion VT3
Inductance L2, the N pole that is connected of colelctor electrode be connected with the electrode input end of amplifier P3, P pole and polarity
The diode D5 that the positive pole of electric capacity C8 is connected, negative pole after resistance R25 with the outfan phase of amplifier P3
Connect, polar capacitor C9, P that positive pole negative input with amplifier P3 after resistance R24 is connected
Pole is connected with the negative pole of polar capacitor C9, N pole base stage with audion VT3 after resistance R22 is connected
The diode D7 connect, positive pole is connected with the emitter stage of audion VT3, after negative pole resistance R26 with polarity
The polar capacitor C10 that the positive pole of electric capacity C9 is connected, one end is connected with the negative pole of polar capacitor C10, separately
The adjustable resistance R27 that one end is connected with the P pole of diode D7, and the collection of P pole and audion VT3
The diode D6 composition that electrode is connected, N pole negative pole with polar capacitor C7 after resistance R21 is connected；
The negative pole of described polar capacitor C7 be connected with the negative pole of polar capacitor C10 after ground connection；Described adjustable resistance
The adjustable end of R27 as the outfan of Passively compensated circuit and is connected with signal amplification circuit；Described field effect
The source electrode of pipe MOS as the input of Passively compensated circuit and is connected with the RC pin processing chip U.
A kind of high-definition image of based on Passively compensated circuit the most according to claim 2 signal processing system
System, it is characterised in that described signal noise control filtered electrical routing amplifier P1, audion VT1, audion VT2,
Positive pole is connected with the base stage of audion VT1, negative pole after resistance R5 with the electrode input end of amplifier P1
The polar capacitor C1 being connected, one end is connected with the base stage of audion VT1, the other end and audion VT1
The resistance R1 that is connected of colelctor electrode, one end is connected with the colelctor electrode of audion VT1, the other end and three poles
The resistance R4 that the colelctor electrode of pipe VT2 is connected, negative pole after resistance R3 with the emitter stage phase of audion VT1
Polar capacitor C2, the N pole that connection, positive pole are connected with the PIN2 pin of process chip U and process chip
Two poles that the PIN2 pin of U is connected, P pole emitter stage with audion VT1 after resistance R2 is connected
Pipe D2, one end is connected with the emitter stage of audion VT2, the PIN2 pin of the other end and process chip U
Inductance L, the P pole being connected is connected with the negative input of amplifier P1, N pole after resistance R6 with put
The diode D1 that the outfan of big device P1 is connected, after negative pole is connected with the negative input of amplifier P1
The polar capacitor C3 that ground connection, positive pole are connected with diode D1N pole after resistance R7, and negative pole and place
The REF pin of reason chip U is connected, positive pole is connected with the N pole of diode D1 after resistance R8
Polar capacitor C4 forms；The base stage of described audion VT2 is connected with the negative pole of polar capacitor C2；Described
The negative pole of polar capacitor C1 is as the input of signal noise control filter circuit；The current collection of described audion VT2
Pole is connected with signal amplification circuit.
A kind of high-definition image of based on Passively compensated circuit the most according to claim 3 signal processing system
System, it is characterised in that described signal amplification circuit is by the colelctor electrode of amplifier P2, P pole Yu audion VT2
The diode D4 that after being connected, ground connection, N pole are connected with the AO pin processing chip U, one end and two poles
The resistance R14 that the N pole of pipe D4 is connected, the other end is connected with the electrode input end of amplifier P2, negative
Pole is connected with the electrode input end of amplifier P2, positive pole is connected with the DB2 pin of process chip U
Polar capacitor C6, one end is connected with the electrode input end of amplifier P2, the other end with amplifier P2's
The adjustable resistance R15 that outfan is connected, one end is connected with the negative pole of polar capacitor C6, the other end and place
The resistance R13 that is connected of DB1 pin of reason chip U, and the negative input of one end and amplifier P2
Be connected, another terminates the resistance R16 composition being connected with the adjustable end of adjustable resistance R27；Described amplification
The outfan of device P2 is as the outfan of signal amplification circuit.
A kind of high-definition image of based on Passively compensated circuit the most according to claim 4 signal processing system
System, it is characterised in that described process chip U is the integrated chip of AD574A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610393460.4A CN105915760A (en) | 2016-06-02 | 2016-06-02 | High-definition image signal processing system based on passive compensating circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610393460.4A CN105915760A (en) | 2016-06-02 | 2016-06-02 | High-definition image signal processing system based on passive compensating circuit |
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| CN105915760A true CN105915760A (en) | 2016-08-31 |
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ID=56743308
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113296275A (en) * | 2021-06-01 | 2021-08-24 | 佳木斯大学 | Medical image observation lamp box for image department |
-
2016
- 2016-06-02 CN CN201610393460.4A patent/CN105915760A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113296275A (en) * | 2021-06-01 | 2021-08-24 | 佳木斯大学 | Medical image observation lamp box for image department |
| CN113296275B (en) * | 2021-06-01 | 2022-08-16 | 佳木斯大学 | Medical image observation lamp box for image department |
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Application publication date: 20160831 |