CN105872314A - Signal buffer image signal processing system based on signal anti-noising filtering circuit - Google Patents
Signal buffer image signal processing system based on signal anti-noising filtering circuit Download PDFInfo
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- CN105872314A CN105872314A CN201610393501.XA CN201610393501A CN105872314A CN 105872314 A CN105872314 A CN 105872314A CN 201610393501 A CN201610393501 A CN 201610393501A CN 105872314 A CN105872314 A CN 105872314A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/68—Control of cameras or camera modules for stable pick-up of the scene, e.g. compensating for camera body vibrations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/148—Video amplifiers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
Abstract
The invention discloses a signal buffer image signal processing system based on a signal anti-noising filtering circuit. The signal buffer image signal processing system is characterized by mainly consisting of an image collector, a signal amplification circuit, a processing chip U, a polar capacitor C5, a diode D3, a resistor R11, a resistor R12, the signal anti-noising filtering circuit, a signal synchronous demodulation circuit and a signal buffer circuit, wherein the signal anti-noising filtering circuit is connected with a pin REF and a pin PIN2 of the processing chip U; the signal synchronous demodulation circuit is connected in series between the pin PIN2 of the processing chip U and the signal anti-noising filtering circuit; the signal buffer circuit is connected in series between the signal anti-noising filtering circuit and the signal amplification circuit. The signal buffer image signal processing system can simultaneously amplify the processed signal and output the image signal after the amplification, so that the frequency bandwidth of the image signal is increased; the image signal at the input end maintains consistency with the sampling signal; the condition of distortion of the image display is effectively prevented.
Description
Technical field
The present invention relates to electronic applications, specifically, be that a kind of signal based on signal noise control filter circuit delays
Rush image-signal processing system.
Background technology
Along with the constantly development of society's science and technology, image processing system has been widely used in recognition of face, has taken the photograph
The fields such as shadow shooting；But, there is noise control poor performance in current image processing system, operating current sound is big,
And picture signal is processed inaccurate defect, thus cause image to show and distortion occurs, unclear ask
Topic, it is impossible to meet the requirement of people.
Therefore it provides one can improve noise control performance, can ensure that again and picture signal is processed image accurately
Processing system is the task of top priority.
Summary of the invention
It is an object of the invention to overcome image processing system of the prior art to there is noise control poor performance, to figure
Image signal process inaccurate defect, it is provided that a kind of based on signal noise control filter circuit signal buffers images
Signal processing system.
The present invention is achieved through the following technical solutions: a kind of signal based on signal noise control filter circuit buffers
Image-signal processing system, mainly by image acquisition device, process chip U, positive pole after resistance R9 with process
The CS pin of chip U is connected, polar capacitor C5, the P pole of minus earth with process chip U RC
The diode D3 that pin is connected, N pole negative pole with polar capacitor C5 after resistance R10 is connected, one
The resistance that end is connected with the N pole of diode D3, the other end is connected with the CE pin of process chip U
R11, one end is connected with the AGND pin processing chip U, the DGND of the other end and process chip U
Pin be connected after the resistance R12 of ground connection, respectively with REF pin and the PIN2 pin phase processing chip U
The signal noise control filter circuit connected, is serially connected in the PIN2 pin processing chip U and signal noise control filter circuit
Between signal synchronous demodulation circuit, respectively with process the AO pin of chip U and DB1 pin and DB2
The signal amplification circuit that pin is connected, and be serially connected in signal noise control filter circuit and signal amplification circuit it
Between signal buffer circuit composition；Described image acquisition device is connected with signal noise control filter circuit.
Described signal buffer circuit is by the base stage of amplifier P4, triode VT7, one end and triode VT7
Be connected, the other end as the input of signal buffer circuit and be connected with signal noise control filter circuit can
Adjusting resistance R28, positive pole is sequentially connected through resistance R29 electrode input end with amplifier P4 after resistance R31
Connect, polar capacitor C12, N pole that negative pole is connected with the adjustable end of adjustable resistance R28 is after resistance R39
Be connected with the base stage of triode VT7, P pole after adjustable resistance R40 with the colelctor electrode phase of triode VT7
Connect diode D9, negative pole be connected with the P pole of diode D9 after resistance R38 after ground connection, positive pole
Polar capacitor C14, the N pole that output with amplifier P4 is connected after resistance R33 is after resistance R34
Be connected with the positive pole of polar capacitor C14, P pole with diode D9 after resistance R35, P pole is connected
Diode D8, negative pole is connected with the P pole of diode D9, positive pole after resistance R37 with diode D8
The polar capacitor C15 that is connected of N pole, negative pole emitter stage with triode VT7 after resistance R36 is connected
Connect, polarity electricity that positive pole is sequentially connected through resistance R30 positive pole with polar capacitor C14 after resistance R32
Hold C13, and P pole is connected with the positive pole of polar capacitor C13, N pole after inductance L2 with polar capacitor
The diode D7 composition that the positive pole of C14 is connected；The negative input ground connection of described amplifier P4；Described
The positive pole of polar capacitor C14 as the output of signal buffer circuit and is connected with signal amplification circuit.
Described signal synchronous demodulation circuit is by amplifier P3, triode VT3, triode VT4, triode
VT5, triode VT6, positive pole is connected with the base stage of triode VT4, negative pole after resistance R21 with three
The polar capacitor C8 that the emitter stage of pole pipe VT5 is connected, one end is connected with the base stage of triode VT3,
The colelctor electrode phase of resistance R19, the N pole that the other end is connected with the base stage of triode VT4 and triode VT4
Connect, diode D5 that P pole emitter stage with triode VT3 after resistance R17 is connected, positive pole is through electricity
Resistance R18 after be connected with the colelctor electrode of triode VT4, negative pole after resistance R20 with amplifier P3 just
The polar capacitor C9 that pole input is connected, positive pole emitter stage with triode VT6 after resistance R23 is connected
Connect, polar capacitor C10 that negative pole is connected with the electrode input end of amplifier P3, positive pole and amplifier P3
Output be connected, negative pole as signal synchronous demodulation circuit output and with process chip U PIN2
The polar capacitor C11 that pin is connected, one end is connected with the negative input of amplifier P3, another termination
The resistance R27 on ground, one end is connected with the emitter stage of triode VT4, the base of the other end and triode VT6
The adjustable resistance R22 that pole is connected, positive pole is connected with the colelctor electrode of triode VT5, the pole of minus earth
Property electric capacity C7, and N pole colelctor electrode with triode VT6 after resistance R26 is connected, P pole sequentially
Through the diode D6 composition that resistance R25 negative pole with polar capacitor C7 after resistance R24 is connected；Described
The base stage of triode VT5 as the input of signal synchronous demodulation circuit and is connected with signal noise control filter circuit
Connecing, its emitter stage is connected with the colelctor electrode of triode VT3；The N pole ground connection of described diode D6.
Described signal noise control filtered electrical routing amplifier P1, triode VT1, triode VT2, positive pole with
The base stage of triode VT1 is connected, negative pole electrode input end with amplifier P1 after resistance R5 is connected
Polar capacitor C1, one end is connected with the base stage of triode VT1, the collection of the other end and triode VT1
The resistance R1 that electrode is connected, one end is connected with the colelctor electrode of triode VT1, the other end and triode
The resistance R4 that the colelctor electrode of VT2 is connected, negative pole emitter stage with triode VT1 after resistance R3 is connected
Connect, the base of polar capacitor C2, N pole that positive pole is connected with the base stage of triode VT5 and triode VT5
The diode D2 that pole is connected, P pole emitter stage with triode VT1 after resistance R2 is connected, one end
Be connected with the emitter stage of triode VT2, inductance L1 that the other end is connected with the base stage of triode VT5,
P pole is connected with the negative input of amplifier P1, N pole after resistance R6 with the output of amplifier P1
The diode D1 being connected, negative pole be connected with the negative input of amplifier P1 after ground connection, positive pole through electricity
The polar capacitor C3 that is connected with diode D1N pole after resistance R7, and the REF of negative pole and process chip U
The polar capacitor C4 composition that pin is connected, positive pole is connected with the N pole of diode D1 after resistance R8；
The base stage of described triode VT2 is connected with the negative pole of polar capacitor C2；The negative pole of described polar capacitor C1
Input as signal noise control filter circuit；The colelctor electrode of described triode VT2 is after adjustable resistance R28
It is connected with the base stage of triode VT7.
Described signal amplification circuit be connected with the positive pole of polar capacitor C14 by amplifier P2, P pole after ground connection,
N pole and the diode D4 that is connected of AO pin processing chip U, the N pole phase of one end and diode D4
The resistance R14 that connection, the other end are connected with the electrode input end of amplifier P2, negative pole and amplifier P2
The polar capacitor C6 that electrode input end is connected, positive pole is connected with the DB2 pin of process chip U,
One end is connected with the electrode input end of amplifier P2, the other end is connected with the output with amplifier P2
Adjustable resistance R15, one end is connected with the negative pole of polar capacitor C6, the other end and process chip U
The resistance R13 that DB1 pin is connected, and one end is connected with the negative input of amplifier P2, another
The resistance R16 composition of end ground connection；The output of described amplifier P2 is as the output of signal amplification circuit.
For the practical effect of the present invention, described process chip U the most preferentially uses the integrated core of AD574A
Sheet realizes.
The present invention compared with prior art, has the following advantages and beneficial effect:
(1) the interference current wave during the present invention can effectively eliminate the picture signal of input, effectively eliminates
Garbage signal frequency in picture signal, makes picture signal to transmit smoothly, thus effectively ensure that this
Picture signal can be processed by invention accurately.
(2) present invention can being dynamically adjusted the different frequent points in picture signal, make in picture signal
The frequency of unlike signal frequency transmission keeps stable, thus the present invention improves process picture signal accurate
Property.
(3) present invention can effectively control the carrier signal in picture signal, makes the carrier frequency of carrier signal
Parameter can keep consistent with the frequency parameter of modulated signal, i.e. the transmission frequency held stationary of picture signal, from
And effectively guarantee that picture signal can accurately be processed by the present invention.
(4) present invention can export after the picture signal after processing being amplified, and makes the frequency band of picture signal
Wide change is big, so that input picture signal keeps consistent with sampled signal, is effectively prevented image and shows
The situation of distortion occurs.
(5) within image fault rate effectively can be dropped to 2% by the present invention, thus the present invention can meet people and exist
The field such as recognition of face, photography and vedio recording can obtain the demand of high-definition image.
(6) the integrated chip of AD574A that present invention employs stable performance is used as processing chip, effectively
Improve the stability that picture signal is processed by the present invention.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of the present invention.
Fig. 2 is the electrical block diagram of the signal synchronous demodulation circuit of the present invention.
Fig. 3 is the electrical block diagram of the signal buffer circuit of the present invention.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is described in further detail, but the enforcement of the present invention
Mode is not limited to this.
Embodiment
As it is shown in figure 1, the present invention is mainly by image acquisition device, process chip U, resistance R9, resistance R10,
Resistance R11, resistance R12, polar capacitor C5, diode D3, signal buffer circuit, signal synchronous demodulation
Circuit, signal noise control filter circuit, and signal amplification circuit composition.
During enforcement, the positive pole of polar capacitor C5 after resistance R9 with process chip U CS pin be connected,
Its minus earth.The P pole of diode D3 is connected with the RC pin processing chip U, its N pole is through electricity
It is connected with the negative pole of polar capacitor C5 after resistance R10.The N pole phase of one end of resistance R11 and diode D3
Connect, its other end is connected with the CE pin processing chip U.One end of resistance R12 and process chip
Ground connection after the AGND pin of U is connected, its other end is connected with the DGND pin processing chip U.
Signal noise control filter circuit is connected with the REF pin processing chip U and PIN2 pin respectively.Signal is same
Step demodulator circuit is serially connected between PIN2 pin and the signal noise control filter circuit processing chip U.Signal buffers
Circuit is serially connected between signal noise control filter circuit and signal amplification circuit.Signal amplification circuit respectively with place
The AO pin of reason chip U is connected with DB1 pin and DB2 pin.Described image acquisition device and letter
Number noise control filter circuit is connected.
Wherein, described signal noise control filtered electrical routing amplifier P1, triode VT1, triode VT2,
Resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8,
Polar capacitor C1, polar capacitor C2, polar capacitor C3, polar capacitor C4, diode D1, diode
D2, and inductance L1 composition.
During connection, the positive pole of polar capacitor C1 is connected with the base stage of triode VT1, its negative pole is through resistance
After R5, the electrode input end with amplifier P1 is connected.One end of resistance R1 and the base stage of triode VT1
Be connected, its other end is connected with the colelctor electrode of triode VT1.One end of resistance R4 and triode VT1
Colelctor electrode be connected, its other end is connected with the colelctor electrode of triode VT2.Polar capacitor C2's is negative
Pole emitter stage with triode VT1 after resistance R3 is connected, the base stage phase of its positive pole and triode VT5
Connect.The N pole of diode D2 is connected with the base stage of triode VT5, its P pole after resistance R2 with
The emitter stage of triode VT1 is connected.
Meanwhile, one end of inductance L1 be connected with the emitter stage of triode VT2, its other end and triode
The base stage of VT5 is connected.The P pole of diode D1 is connected with the negative input of amplifier P1, its N
Pole output with amplifier P1 after resistance R6 is connected.The negative pole of polar capacitor C3 and amplifier P1
Negative input be connected after ground connection, its positive pole be connected with diode D1N pole after resistance R7.Pole
Property electric capacity C4 negative pole with process chip U REF pin be connected, its positive pole after resistance R8 with two poles
The N pole of pipe D1 is connected.
The base stage of described triode VT2 is connected with the negative pole of polar capacitor C2；Described polar capacitor C1
Negative pole as the input of signal noise control filter circuit and be connected with image acquisition device；Described triode
The colelctor electrode of VT2 base stage with triode VT7 after adjustable resistance R28 is connected.
Meanwhile, described signal amplification circuit is by amplifier P2, resistance R13, resistance R14, adjustable resistance
R15, resistance R16, polar capacitor C6, and diode D4 form.
During connection, the P pole of diode D4 be connected with the positive pole of polar capacitor C14 after ground connection, its N pole
It is connected with the AO pin processing chip U.One end of resistance R14 is connected with the N pole of diode D4,
Its other end is connected with the electrode input end of amplifier P2.The negative pole of polar capacitor C6 is with amplifier P2's
Electrode input end is connected, its positive pole is connected with the DB2 pin processing chip U.
Wherein, one end of adjustable resistance R15 be connected with the electrode input end of amplifier P2, its other end
It is connected with the output with amplifier P2.One end of resistance R13 is connected with the negative pole of polar capacitor C6,
Its other end is connected with the DB1 pin processing chip U.One end of resistance R16 is negative with amplifier P2's
Pole input is connected, its other end ground connection.The output of described amplifier P2 is as signal amplification circuit
Output is also connected with image display device.
As in figure 2 it is shown, described signal synchronous demodulation circuit is by amplifier P3, triode VT3, triode
VT4, triode VT5, triode VT6, resistance R17, resistance R18, resistance R19, resistance R20,
Resistance R21, adjustable resistance R22, resistance R23, resistance R24, resistance R25, resistance R26, resistance
R27, polar capacitor C7, polar capacitor C8, polar capacitor C9, polar capacitor C10, polar capacitor C11,
Diode D5, and diode D6 composition.
During connection, the positive pole of polar capacitor C8 is connected with the base stage of triode VT4, its negative pole is through resistance
After R21, the emitter stage with triode VT5 is connected.The base stage phase of one end of resistance R19 and triode VT3
Connect, its other end is connected with the base stage of triode VT4.The N pole of diode D5 and triode VT4
Colelctor electrode be connected, its P pole emitter stage with triode VT3 after resistance R17 is connected.Polarity electricity
The positive pole colelctor electrode with triode VT4 after resistance R18 holding C9 is connected, its negative pole is through resistance R20
Electrode input end with amplifier P3 is connected afterwards.The positive pole of polar capacitor C10 after resistance R23 with three poles
The emitter stage of pipe VT6 is connected, its negative pole is connected with the electrode input end of amplifier P3.
Wherein, the positive pole of polar capacitor C11 is connected with the output of amplifier P3, its negative pole is as letter
The output of number synchronous demodulation circuit is also connected with the PIN2 pin processing chip U.The one of resistance R27
End is connected with the negative input of amplifier P3, its other end ground connection.One end of adjustable resistance R22 and three
The emitter stage of pole pipe VT4 is connected, its other end is connected with the base stage of triode VT6.Polar capacitor
The positive pole of C7 is connected with the colelctor electrode of triode VT5, its minus earth.The N pole of diode D6 is through electricity
Be connected with the colelctor electrode of triode VT6 after resistance R26, its P pole is sequentially through resistance R25 and resistance R24
Negative pole with polar capacitor C7 is connected afterwards.
The base stage of described triode VT5 as the input of signal synchronous demodulation circuit and is filtered with signal noise control
Wave circuit is connected, and its emitter stage is connected with the colelctor electrode of triode VT3；The N of described diode D6
Pole ground connection.
As it is shown on figure 3, described signal buffer circuit is by amplifier P4, triode VT7, adjustable resistance R28,
Resistance R29, resistance R30, resistance R31, resistance R32, resistance R33, resistance R34, resistance R35,
Resistance R36, resistance R37, resistance R38, resistance R39, adjustable resistance R40, polar capacitor C12, pole
Property electric capacity C13, polar capacitor C14, polar capacitor C15, diode D7, diode D8, diode
D9, and inductance L2 composition.
During connection, one end of adjustable resistance R28 is connected with the base stage of triode VT7, its other end is made
For the input of signal buffer circuit and it is connected with signal noise control filter circuit.The positive pole of polar capacitor C12
Sequentially be connected with the electrode input end of amplifier P4 after resistance R31 through resistance R29, its negative pole is with adjustable
The adjustable end of resistance R28 is connected.The N pole of diode D9 after resistance R39 with the base of triode VT7
Pole is connected, its P pole colelctor electrode with triode VT7 after adjustable resistance R40 is connected.Polar capacitor
The negative pole of C14 be connected with the P pole of diode D9 after resistance R38 after ground connection, its positive pole through resistance R33
Output with amplifier P4 is connected afterwards.
Meanwhile, the N pole of diode D8 positive pole with polar capacitor C14 after resistance R34 be connected, its
P pole with diode D9 after resistance R35, P pole is connected.The negative pole of polar capacitor C15 and diode
The P pole of D9 is connected, its positive pole N pole with diode D8 after resistance R37 is connected.Polar capacitor
The negative pole of C13 emitter stage with triode VT7 after resistance R36 is connected, its positive pole is sequentially through resistance R30
It is connected with positive pole with polar capacitor C14 after resistance R32.The P pole of diode D7 and polar capacitor C13
Positive pole be connected, its N pole positive pole with polar capacitor C14 after inductance L2 is connected.Described amplification
The negative input ground connection of device P4；The positive pole of described polar capacitor C14 is as the output of signal buffer circuit
And be connected with signal amplification circuit.
During operation, the present invention can export after the picture signal after processing being amplified simultaneously, makes picture signal
Frequency bandwidth become big so that input picture signal is consistent with sampled signal holding, be effectively prevented
Image shows situation distortion occur.Meanwhile, the present invention can dynamically entering the different frequent points in picture signal
Row regulation, the frequency making the unlike signal frequency in picture signal transmit keeps stable；And the present invention can also have
Carrier signal in the control picture signal of effect, the carrier frequency parameter making carrier signal can be with modulated signal
Frequency parameter keeps consistent, i.e. the transmission frequency held stationary of picture signal, thus effectively guarantees the present invention
Picture signal can accurately be processed.
Within image fault rate effectively can be dropped to 2% by the present invention, thus the present invention can effectively meet people
The demand of high-definition image can be obtained in the field such as recognition of face, photography and vedio recording.In order to preferably implement the present invention,
Described process chip U have employed the integrated chip of AD574A of stable performance and realizes, and effectively raises
The stability that picture signal is processed by the present invention.
According to above-described embodiment, can well realize the present invention.
Claims (6)
1. a signal buffers images signal processing system based on signal noise control filter circuit, its feature exists
In, mainly by image acquisition device, processing chip U, positive pole is managed with the CS processing chip U after resistance R9
Pin is connected, polar capacitor C5, the P pole of minus earth is connected with the RC pin processing chip U, N
The diode D3 that pole negative pole with polar capacitor C5 after resistance R10 is connected, one end and diode D3
The resistance R11 that N pole is connected, the other end is connected with the CE pin of process chip U, one end and place
After the AGND pin of reason chip U is connected, the other end is connected with the DGND pin of process chip U
The resistance R12 of ground connection, the signal being connected with the REF pin processing chip U and PIN2 pin respectively is prevented
Make an uproar filter circuit, the signal being serially connected between the PIN2 pin and the signal noise control filter circuit that process chip U with
Step demodulator circuit, respectively with process the AO pin of chip U and DB1 pin and DB2 pin is connected
Signal amplification circuit, and be serially connected in the signal between signal noise control filter circuit and signal amplification circuit delay
Rush circuit composition；Described image acquisition device is connected with signal noise control filter circuit.
A kind of signal buffers images based on signal noise control filter circuit the most according to claim 1 is believed
Number processing system, it is characterised in that described signal buffer circuit is by amplifier P4, triode VT7, one end
Be connected with the base stage of triode VT7, the other end as signal buffer circuit input and with signal noise control
The adjustable resistance R28 that filter circuit is connected, positive pole sequentially after resistance R29 and resistance R31 with amplifier
The polar capacitor C12 that the electrode input end of P4 is connected, negative pole is connected with the adjustable end of adjustable resistance R28,
N pole base stage with triode VT7 after resistance R39 is connected, P pole after adjustable resistance R40 with three poles
The diode D9 that the colelctor electrode of pipe VT7 is connected, negative pole after resistance R38 with the P pole phase of diode D9
The polar capacitor C14 that after connection, ground connection, positive pole output with amplifier P4 after resistance R33 is connected,
N pole positive pole with polar capacitor C14 after resistance R34 is connected, P pole after resistance R35 with diode
The diode D8 that the P pole of D9 is connected, negative pole is connected with the P pole of diode D9, positive pole is through resistance
The polar capacitor C15 being connected with the N pole of diode D8 after R37, negative pole after resistance R36 with three poles
The emitter stage of pipe VT7 is connected, positive pole sequentially after resistance R30 and resistance R32 with polar capacitor C14
The polar capacitor C13 that is connected of positive pole, and P pole is connected with the positive pole of polar capacitor C13, N pole
The diode D7 composition that positive pole with polar capacitor C14 is connected after inductance L2；Described amplifier P4
Negative input ground connection；The positive pole of described polar capacitor C14 as signal buffer circuit output and with
Signal amplification circuit is connected.
A kind of signal buffers images based on signal noise control filter circuit the most according to claim 2 is believed
Number processing system, it is characterised in that described signal synchronous demodulation circuit by amplifier P3, triode VT3,
Triode VT4, triode VT5, triode VT6, positive pole is connected with the base stage of triode VT4, bears
The polar capacitor C8 that pole emitter stage with triode VT5 after resistance R21 is connected, one end and triode
Resistance R19, the N pole and three that the base stage of VT3 is connected, the other end is connected with the base stage of triode VT4
The colelctor electrode of pole pipe VT4 is connected, P pole emitter stage with triode VT3 after resistance R17 is connected
Diode D5, positive pole colelctor electrode with triode VT4 after resistance R18 is connected, negative pole is through resistance R20
The polar capacitor C9 that electrode input end with amplifier P3 is connected afterwards, positive pole after resistance R23 with three poles
The polar capacitor C10 that the emitter stage of pipe VT6 is connected, negative pole is connected with the electrode input end of amplifier P3,
Positive pole is connected with the output of amplifier P3, negative pole as signal synchronous demodulation circuit output and with place
The polar capacitor C11 that the PIN2 pin of reason chip U is connected, one end and the negative input of amplifier P3
Be connected, the resistance R27 of other end ground connection, one end is connected with the emitter stage of triode VT4, the other end
The adjustable resistance R22 being connected with the base stage of triode VT6, positive pole is connected with the colelctor electrode of triode VT5
Connect, the polar capacitor C7 of minus earth, and N pole after resistance R26 with the colelctor electrode of triode VT6
Be connected, two poles that P pole is sequentially connected through resistance R25 negative pole with polar capacitor C7 after resistance R24
Pipe D6 forms；The base stage of described triode VT5 as signal synchronous demodulation circuit input and and signal
Noise control filter circuit is connected, and its emitter stage is connected with the colelctor electrode of triode VT3；Described diode D6
N pole ground connection.
A kind of signal buffers images based on signal noise control filter circuit the most according to claim 3 is believed
Number processing system, it is characterised in that described signal noise control filtered electrical routing amplifier P1, triode VT1,
Triode VT2, positive pole is connected with the base stage of triode VT1, negative pole after resistance R5 with amplifier P1
The polar capacitor C1 that is connected of electrode input end, one end is connected with the base stage of triode VT1, the other end
The resistance R1 being connected with the colelctor electrode of triode VT1, one end is connected with the colelctor electrode of triode VT1,
The resistance R4 that the other end is connected with the colelctor electrode of triode VT2, negative pole after resistance R3 with triode VT1
Polar capacitor C2, the N pole that emitter stage is connected, positive pole is connected with the base stage of triode VT5 and three poles
Two poles that the base stage of pipe VT5 is connected, P pole emitter stage with triode VT1 after resistance R2 is connected
Pipe D2, one end is connected with the emitter stage of triode VT2, the other end is connected with the base stage of triode VT5
Inductance L1, the P pole connect is connected with the negative input of amplifier P1, N pole after resistance R6 with amplification
The diode D1 that the output of device P1 is connected, negative pole is connected with the negative input of amplifier P1 and is followed by
Ground, the polar capacitor C3 that is connected with diode D1N pole after resistance R7 of positive pole, and negative pole and process
The pole that the REF pin of chip U is connected, positive pole is connected with the N pole of diode D1 after resistance R8
Property electric capacity C4 composition；The base stage of described triode VT2 is connected with the negative pole of polar capacitor C2；Described pole
The negative pole of property electric capacity C1 is as the input of signal noise control filter circuit；The colelctor electrode of described triode VT2
After adjustable resistance R28, the base stage with triode VT7 is connected.
A kind of signal buffers images based on signal noise control filter circuit the most according to claim 4 is believed
Number processing system, it is characterised in that described signal amplification circuit is by amplifier P2, P pole and polar capacitor C14
Positive pole be connected after ground connection, N pole and the diode D4 that is connected of AO pin processing chip U, one end
Be connected with the N pole of diode D4, resistance that the other end is connected with the electrode input end of amplifier P2
R14, negative pole is connected with the electrode input end of amplifier P2, the DB2 pin phase of positive pole and process chip U
Connect polar capacitor C6, one end is connected with the electrode input end of amplifier P2, the other end and with amplification
The adjustable resistance R15 that the output of device P2 is connected, one end is connected with the negative pole of polar capacitor C6, separately
One end and the resistance R13 that is connected of DB1 pin processing chip U, and one end and amplifier P2's is negative
Pole input is connected, the resistance R16 of other end ground connection composition；The output of described amplifier P2 is as letter
The output of number amplifying circuit.
A kind of signal buffers images based on signal noise control filter circuit the most according to claim 5 is believed
Number processing system, it is characterised in that described process chip U is the integrated chip of AD574A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610393501.XA CN105872314A (en) | 2016-06-02 | 2016-06-02 | Signal buffer image signal processing system based on signal anti-noising filtering circuit |
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