CN105847634A - Signal buffering circuit-based high-definition image signal processing system - Google Patents
Signal buffering circuit-based high-definition image signal processing system Download PDFInfo
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- CN105847634A CN105847634A CN201610390280.0A CN201610390280A CN105847634A CN 105847634 A CN105847634 A CN 105847634A CN 201610390280 A CN201610390280 A CN 201610390280A CN 105847634 A CN105847634 A CN 105847634A
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- polar capacitor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/148—Video amplifiers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
Abstract
The invention discloses a signal buffering circuit-based high-definition image signal processing system. The signal buffering circuit-based high-definition image signal processing system is characterized in that the signal buffering circuit-based high-definition image signal processing system is mainly composed of an image acquisition unit, a processing chip U, a signal amplifying circuit, a polar capacitor C5, a diode D3, a resistor R11, a resistor 12, a signal noise-resisting filtering circuit and a signal buffering circuit; one end of the resistor R11 is connected with the N pole of the diode D3, and the other end of the resistor R11 is connected with the CE pin of the processing chip U; one end of the resistor 12 is connected with the AGND pin of the processing chip U, and the other end of the resistor 12 is connected with the DGND pin of the processing chip U and thereafter is grounded; the signal noise-resisting filtering circuit is connected with the REF pin and PIN 2 pin of the processing chip U; and the signal buffering circuit is connected in series between the signal noise-resisting filtering circuit and the signal amplifying circuit. The signal buffering circuit-based high-definition image signal processing system of the invention can amplify processed image signals and then output the amplified image signals, so that the frequency bandwidth of the image signals can be increased, and therefore, image signals at an input end can be kept consistent with sampling signals, and distortion of image display can be effectively prevented.
Description
Technical field
The present invention relates to electronic applications, specifically, be a kind of high-definition image based on signal damping circuit letter
Number processing system.
Background technology
Along with the constantly development of society's science and technology, image processing system has been widely used in recognition of face, has taken the photograph
The fields such as shadow shooting；But, there is noise control poor performance in current image processing system, and to picture signal
Process inaccurate defect, thus cause image to show and distortion, unclear problem occur, it is impossible to meet people
Requirement.
Therefore it provides one can improve noise control performance, can ensure that again and picture signal is processed image accurately
Processing system is the task of top priority.
Summary of the invention
It is an object of the invention to overcome image processing system of the prior art to there is noise control poor performance, to figure
Image signal process inaccurate defect, it is provided that a kind of based on signal damping circuit high-definition image signal processing
System.
The present invention is achieved through the following technical solutions: a kind of high-definition image signal based on signal damping circuit
Processing system, mainly by image acquisition device, processes chip U, positive pole after resistance R9 with process chip U
CS pin is connected, polar capacitor C5, the P pole of minus earth is connected with the RC pin processing chip U,
The diode D3 that N pole negative pole with polar capacitor C5 after resistance R10 is connected, one end and diode D3
The resistance R11 that N pole is connected, the other end is connected with the CE pin of process chip U, one end and place
After the AGND pin of reason chip U is connected, the other end is connected with the DGND pin of process chip U
The resistance R12 of ground connection, the signal being connected with the REF pin processing chip U and PIN2 pin respectively is prevented
Make an uproar filter circuit, be connected with the AO pin processing chip U and DB1 pin and DB2 pin respectively
Signal amplification circuit, and be serially connected in the signal between signal noise control filter circuit and signal amplification circuit delay
Rush circuit composition；Described image acquisition device is connected with signal noise control filter circuit.
The base stage of described signal damping electricity routing amplifier P3, audion VT3, one end and audion VT3
Be connected, the other end as the input of signal damping circuit and be connected with signal noise control filter circuit can
Adjusting resistance R17, positive pole is sequentially connected through resistance R18 electrode input end with amplifier P3 after resistance R20
Connect, polar capacitor C7, N pole that negative pole is connected with the adjustable end of adjustable resistance R17 after resistance R28 with
The base stage of audion VT3 is connected, P pole colelctor electrode with audion VT3 after adjustable resistance R29 is connected
The diode D7 connect, negative pole be connected with the P pole of diode D7 after resistance R27 after ground connection, positive pole warp
Polar capacitor C9, the N pole that after resistance R22, outfan with amplifier P3 is connected after resistance R23 with
The positive pole of polar capacitor C9 is connected, P pole is connected with the P pole of diode D7 after resistance R24 two
Pole pipe D6, negative pole is connected with the P pole of diode D7, positive pole after resistance R26 with diode D6's
The polar capacitor C10 that N pole is connected, negative pole emitter stage with audion VT3 after resistance R25 is connected,
The polar capacitor C8 that positive pole is sequentially connected through resistance R19 positive pole with polar capacitor C9 after resistance R21,
And P pole is connected with the positive pole of polar capacitor C8, N pole after inductance L2 with polar capacitor C9 just
The diode D5 composition that pole is connected；The negative input ground connection of described amplifier P3；Described polar capacitor
The positive pole of C9 as the outfan of signal damping circuit and is connected with signal amplification circuit.
Described signal noise control filtered electrical routing amplifier P1, audion VT1, audion VT2, positive pole with
The base stage of audion VT1 is connected, negative pole electrode input end with amplifier P1 after resistance R5 is connected
Polar capacitor C1, one end is connected with the base stage of audion VT1, the collection of the other end and audion VT1
The resistance R1 that electrode is connected, one end is connected with the colelctor electrode of audion VT1, the other end and audion
The resistance R4 that the colelctor electrode of VT2 is connected, negative pole emitter stage with audion VT1 after resistance R3 is connected
Connect, polar capacitor C2, N pole that positive pole is connected with the PIN2 pin of process chip U with process chip U
The diode that PIN2 pin is connected, P pole emitter stage with audion VT1 after resistance R2 is connected
D2, one end is connected with the emitter stage of audion VT2, the PIN2 pin phase of the other end and process chip U
Connect inductance L1, P pole be connected with the negative input of amplifier P1, N pole after resistance R6 with put
The diode D1 that the outfan of big device P1 is connected, after negative pole is connected with the negative input of amplifier P1
The polar capacitor C3 that ground connection, positive pole are connected with diode D1N pole after resistance R7, and negative pole and place
The REF pin of reason chip U is connected, positive pole is connected with the N pole of diode D1 after resistance R8
Polar capacitor C4 forms；The base stage of described audion VT2 is connected with the negative pole of polar capacitor C2；Described
The negative pole of polar capacitor C1 is as the input of signal noise control filter circuit；The current collection of described audion VT2
Pole base stage with audion VT3 after adjustable resistance R17 is connected.
Described signal amplification circuit be connected with the positive pole of polar capacitor C9 by amplifier P2, P pole after ground connection,
N pole and the diode D4 that is connected of AO pin processing chip U, the N pole phase of one end and diode D4
The resistance R14 that connection, the other end are connected with the electrode input end of amplifier P2, negative pole and amplifier P2
The polar capacitor C6 that electrode input end is connected, positive pole is connected with the DB2 pin of process chip U,
One end is connected with the electrode input end of amplifier P2, the other end is connected with the outfan with amplifier P2
Adjustable resistance R15, one end is connected with the negative pole of polar capacitor C6, the other end and process chip U
The resistance R13 that DB1 pin is connected, and one end is connected with the negative input of amplifier P2, another
The resistance R16 composition of end ground connection；The outfan of described amplifier P2 is as the outfan of signal amplification circuit.
For the practical effect of the present invention, described process chip U the most preferentially uses the integrated core of AD574A
Sheet realizes.
The present invention compared with prior art, has the following advantages and beneficial effect:
(1) the interference current wave during the present invention can effectively eliminate the picture signal of input, effectively eliminates
Garbage signal frequency in picture signal, makes picture signal to transmit smoothly, ensures that energy of the present invention
Picture signal is processed accurately.
(2) present invention can being dynamically adjusted the different frequent points in picture signal, make in picture signal
The frequency of unlike signal frequency transmission keeps stable, thus the present invention improves process picture signal accurate
Property.
(3) present invention can export after the picture signal after processing being amplified, and makes the frequency band of picture signal
Wide change is big, so that input picture signal keeps consistent with sampled signal, is effectively prevented image and shows
The situation of distortion occurs.
(4) within image fault rate effectively can be dropped to 2% by the present invention, thus the present invention can meet people and exist
The field such as recognition of face, photography and vedio recording can obtain the demand of high-definition image.
(5) the integrated chip of AD574A that present invention employs stable performance is used as processing chip, effectively
Improve the stability that picture signal is processed by the present invention.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of the present invention.
Fig. 2 is the electrical block diagram of the signal damping circuit of the present invention.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is described in further detail, but the enforcement of the present invention
Mode is not limited to this.
Embodiment
As it is shown in figure 1, the present invention is mainly by image acquisition device, process chip U, resistance R9, resistance R10,
Resistance R11, resistance R12, polar capacitor C5, diode D3, signal damping circuit, signal noise control filters
Circuit, and signal amplification circuit composition.
During enforcement, the positive pole of polar capacitor C5 after resistance R9 with process chip U CS pin be connected,
Its minus earth.The P pole of diode D3 is connected with the RC pin processing chip U, its N pole is through electricity
It is connected with the negative pole of polar capacitor C5 after resistance R10.The N pole phase of one end of resistance R11 and diode D3
Connect, its other end is connected with the CE pin processing chip U.One end of resistance R12 and process chip
Ground connection after the AGND pin of U is connected, its other end is connected with the DGND pin processing chip U.
Signal damping circuit is serially connected between signal noise control filter circuit and signal amplification circuit.Signal noise control filtered electrical
Road is connected with the REF pin processing chip U and PIN2 pin respectively.Signal amplification circuit respectively with
The AO pin processing chip U is connected with DB1 pin and DB2 pin.Described image acquisition device with
Signal noise control filter circuit is connected.
Wherein, described signal noise control filtered electrical routing amplifier P1, audion VT1, audion VT2,
Resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8,
Polar capacitor C1, polar capacitor C2, polar capacitor C3, polar capacitor C4, diode D1, diode
D2, and inductance L1 composition.
During connection, the positive pole of polar capacitor C1 is connected with the base stage of audion VT1, its negative pole is through resistance
After R5, the electrode input end with amplifier P1 is connected.One end of resistance R1 and the base stage of audion VT1
Be connected, its other end is connected with the colelctor electrode of audion VT1.One end of resistance R4 and audion VT1
Colelctor electrode be connected, its other end is connected with the colelctor electrode of audion VT2.Polar capacitor C2's is negative
Pole emitter stage with audion VT1 after resistance R3 is connected, its positive pole and the PIN2 processing chip U
Pin is connected.The N pole of diode D2 is connected with the PIN2 pin processing chip U, its P pole is through electricity
It is connected with the emitter stage of audion VT1 after resistance R2.
Meanwhile, one end of inductance L1 be connected with the emitter stage of audion VT2, its other end with process core
The PIN2 pin of sheet U is connected.The P pole of diode D1 is connected with the negative input of amplifier P1,
Its N pole outfan with amplifier P1 after resistance R6 is connected.The negative pole of polar capacitor C3 and amplification
After the negative input of device P1 is connected, ground connection, its positive pole are connected with diode D1N pole after resistance R7.
The negative pole of polar capacitor C4 with process chip U REF pin be connected, its positive pole after resistance R8 with two
The N pole of pole pipe D1 is connected.
The base stage of described audion VT2 is connected with the negative pole of polar capacitor C2；Described polar capacitor C1
Negative pole as the input of signal noise control filter circuit and be connected with image acquisition device；Described audion
The colelctor electrode of VT2 base stage with audion VT3 after adjustable resistance R17 is connected.
Meanwhile, described signal amplification circuit is by amplifier P2, resistance R13, resistance R14, adjustable resistance
R15, resistance R16, polar capacitor C6, and diode D4 form.
During connection, the P pole of diode D4 be connected with the positive pole of polar capacitor C9 after ground connection, its N pole
It is connected with the AO pin processing chip U.One end of resistance R14 is connected with the N pole of diode D4,
Its other end is connected with the electrode input end of amplifier P2.The negative pole of polar capacitor C6 is with amplifier P2's
Electrode input end is connected, its positive pole is connected with the DB2 pin processing chip U.
Wherein, one end of adjustable resistance R15 be connected with the electrode input end of amplifier P2, its other end
It is connected with the outfan with amplifier P2.One end of resistance R13 is connected with the negative pole of polar capacitor C6,
Its other end is connected with the DB1 pin processing chip U.One end of resistance R16 is negative with amplifier P2's
Pole input is connected, its other end ground connection.The outfan of described amplifier P2 is as signal amplification circuit
Outfan is also connected with image display device.
As in figure 2 it is shown, described signal damping electricity routing amplifier P3, audion VT3, adjustable resistance R17,
Resistance R18, resistance R19, resistance R20, resistance R21, resistance R22, resistance R23, resistance R24,
Resistance R25, resistance R26, resistance R27, resistance R28, adjustable resistance R29, polar capacitor C7, pole
Property electric capacity C8, polar capacitor C9, polar capacitor C10, diode D5, diode D6, diode D7,
And inductance L2 composition.
During connection, one end of adjustable resistance R17 is connected with the base stage of audion VT3, its other end is made
For the input of signal damping circuit and it is connected with signal noise control filter circuit.The positive pole of polar capacitor C7 is suitable
Secondary be connected through resistance R18 electrode input end with amplifier P3 after resistance R20, its negative pole and adjustable electric
The adjustable end of resistance R17 is connected.The N pole of diode D7 after resistance R28 with the base stage of audion VT3
Be connected, its P pole colelctor electrode with audion VT3 after adjustable resistance R29 is connected.Polar capacitor
The negative pole of C9 be connected with the P pole of diode D7 after resistance R27 after ground connection, its positive pole through resistance R22
Outfan with amplifier P3 is connected afterwards.
Meanwhile, the N pole of diode D6 positive pole with polar capacitor C9 after resistance R23 be connected, its
P pole with diode D7 after resistance R24, P pole is connected.The negative pole of polar capacitor C10 and diode
The P pole of D7 is connected, its positive pole N pole with diode D6 after resistance R26 is connected.Polar capacitor
The negative pole of C8 emitter stage with audion VT3 after resistance R25 is connected, its positive pole is sequentially through resistance R19
It is connected with positive pole with polar capacitor C9 after resistance R21.The P pole of diode D5 and polar capacitor C8
Positive pole be connected, its N pole positive pole with polar capacitor C9 after inductance L2 is connected.Described amplifier
The negative input ground connection of P3；The positive pole of described polar capacitor C9 as signal damping circuit outfan also
It is connected with signal amplification circuit.
During operation, the present invention can export after the picture signal after processing being amplified simultaneously, makes picture signal
Frequency bandwidth becomes big, so that input picture signal keeps consistent with sampled signal, is effectively prevented figure
As the situation of distortion occurs in display.Meanwhile, the present invention can dynamically carrying out the different frequent points in picture signal
Regulation, the frequency making the unlike signal frequency in picture signal transmit keeps stable, thus the present invention is effective
Improve the accuracy that picture signal is processed.
Within image fault rate effectively can be dropped to 2% by the present invention, thus the present invention can effectively meet people
The demand of high-definition image can be obtained in the field such as recognition of face, photography and vedio recording.In order to preferably implement the present invention,
Described process chip U the most preferentially have employed the integrated chip of AD574A of stable performance and realizes, and effectively carries
The stability that picture signal is processed by the high present invention.
According to above-described embodiment, can well realize the present invention.
Claims (5)
1. a high-definition image signal processing system based on signal damping circuit, it is characterised in that main
By image acquisition device, process chip U, positive pole is connected with the CS pin processing chip U after resistance R9,
Polar capacitor C5, the P pole of minus earth is connected with the RC pin processing chip U, N pole is through resistance R10
The diode D3 that negative pole with polar capacitor C5 is connected afterwards, one end is connected with the N pole of diode D3,
The resistance R11 that the other end is connected with the CE pin processing chip U, one end and the AGND processing chip U
The resistance R12 of ground connection after pin is connected, the other end is connected with the DGND pin of process chip U, point
The signal noise control filter circuit not being connected with REF pin and the PIN2 pin of process chip U, respectively with
Process the signal amplification circuit that the AO pin of chip U is connected with DB1 pin and DB2 pin, with
And the signal damping circuit composition being serially connected between signal noise control filter circuit and signal amplification circuit；Described figure
As harvester is connected with signal noise control filter circuit.
A kind of high-definition image of based on signal damping circuit the most according to claim 1 signal processing system
System, it is characterised in that described signal damping electricity routing amplifier P3, audion VT3, one end and audion
The base stage of VT3 is connected, the other end as signal damping circuit input and with signal noise control filter circuit
The adjustable resistance R17 being connected, positive pole sequentially after resistance R18 and resistance R20 with the positive pole of amplifier P3
Polar capacitor C7, the N pole that input is connected, negative pole is connected with the adjustable end of adjustable resistance R17 is through electricity
Resistance R28 after be connected with the base stage of audion VT3, P pole after adjustable resistance R29 with audion VT3
The diode D7 that is connected of colelctor electrode, after negative pole is connected with the P pole of diode D7 after resistance R27
Polar capacitor C9, the N pole warp that ground connection, positive pole outfan with amplifier P3 after resistance R22 is connected
After resistance R23 the positive pole with polar capacitor C9 be connected, P pole after resistance R24 with the P of diode D7
The diode D6 that pole is connected, negative pole is connected with the P pole of diode D7, positive pole after resistance R26 with
The polar capacitor C10 that the N pole of diode D6 is connected, negative pole after resistance R25 with audion VT3's
Emitter stage is connected, positive pole is sequentially connected through resistance R19 positive pole with polar capacitor C9 after resistance R21
The polar capacitor C8 connect, and P pole is connected with the positive pole of polar capacitor C8, N pole after inductance L2 with
The diode D5 composition that the positive pole of polar capacitor C9 is connected；The negative input of described amplifier P3 connects
Ground；The positive pole of described polar capacitor C9 as the outfan of signal damping circuit and is connected with signal amplification circuit
Connect.
A kind of high-definition image of based on signal damping circuit the most according to claim 2 signal processing system
System, it is characterised in that described signal noise control filtered electrical routing amplifier P1, audion VT1, audion VT2,
Positive pole is connected with the base stage of audion VT1, negative pole after resistance R5 with the electrode input end of amplifier P1
The polar capacitor C1 being connected, one end is connected with the base stage of audion VT1, the other end and audion VT1
The resistance R1 that is connected of colelctor electrode, one end is connected with the colelctor electrode of audion VT1, the other end and three poles
The resistance R4 that the colelctor electrode of pipe VT2 is connected, negative pole after resistance R3 with the emitter stage phase of audion VT1
Polar capacitor C2, the N pole that connection, positive pole are connected with the PIN2 pin of process chip U and process chip
Two poles that the PIN2 pin of U is connected, P pole emitter stage with audion VT1 after resistance R2 is connected
Pipe D2, one end is connected with the emitter stage of audion VT2, the PIN2 pin of the other end and process chip U
Inductance L1, the P pole being connected is connected with the negative input of amplifier P1, N pole after resistance R6 with
The diode D1 that the outfan of amplifier P1 is connected, negative pole is connected with the negative input of amplifier P1
The polar capacitor C3 that rear ground connection, positive pole are connected with diode D1N pole after resistance R7, and negative pole with
The REF pin processing chip U is connected, positive pole N pole with diode D1 after resistance R8 is connected
Polar capacitor C4 composition；The base stage of described audion VT2 is connected with the negative pole of polar capacitor C2；Institute
State the negative pole input as signal noise control filter circuit of polar capacitor C1；The collection of described audion VT2
Electrode base stage with audion VT3 after adjustable resistance R17 is connected.
A kind of high-definition image of based on signal damping circuit the most according to claim 3 signal processing system
System, it is characterised in that described signal amplification circuit is by the positive pole phase of amplifier P2, P pole with polar capacitor C9
The diode D4 that after connection, ground connection, N pole are connected with the AO pin processing chip U, one end and diode
The resistance R14 that the N pole of D4 is connected, the other end is connected with the electrode input end of amplifier P2, negative pole
Be connected with the electrode input end of amplifier P2, pole that positive pole is connected with the DB2 pin of process chip U
Property electric capacity C6, one end is connected with the electrode input end of amplifier P2, defeated with amplifier P2 of the other end
Going out the adjustable resistance R15 that is connected of end, one end is connected with the negative pole of polar capacitor C6, the other end and process
The resistance R13 that the DB1 pin of chip U is connected, and the negative input phase of one end and amplifier P2
Connect, the resistance R16 of other end ground connection forms；The outfan of described amplifier P2 is as signal amplification circuit
Outfan.
A kind of high-definition image of based on signal damping circuit the most according to claim 4 signal processing system
System, it is characterised in that described process chip U is the integrated chip of AD574A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610390280.0A CN105847634A (en) | 2016-06-02 | 2016-06-02 | Signal buffering circuit-based high-definition image signal processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610390280.0A CN105847634A (en) | 2016-06-02 | 2016-06-02 | Signal buffering circuit-based high-definition image signal processing system |
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| Publication Number | Publication Date |
|---|---|
| CN105847634A true CN105847634A (en) | 2016-08-10 |
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ID=56575442
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|---|---|---|---|
| CN201610390280.0A Pending CN105847634A (en) | 2016-06-02 | 2016-06-02 | Signal buffering circuit-based high-definition image signal processing system |
Country Status (1)
| Country | Link |
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| CN (1) | CN105847634A (en) |
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2016
- 2016-06-02 CN CN201610390280.0A patent/CN105847634A/en active Pending
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