CN106131377A - Based on the polynary cruising device high performance signal processing system from cognition technology - Google Patents
Based on the polynary cruising device high performance signal processing system from cognition technology Download PDFInfo
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- CN106131377A CN106131377A CN201610769311.3A CN201610769311A CN106131377A CN 106131377 A CN106131377 A CN 106131377A CN 201610769311 A CN201610769311 A CN 201610769311A CN 106131377 A CN106131377 A CN 106131377A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
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Abstract
The invention discloses a kind of based on the polynary cruising device high performance signal processing system from cognition technology, mainly by processing chip U, infrared pick-up head WS, field effect transistor MOS1, audion VT3, polar capacitor C8, synchronizing signal adjusts circuit, the compositions such as differential amplifier circuit, picture signal pretreatment circuit, and the output signal amplification circuit being connected with the PIUT pin of process chip U and the emitter stage of audion VT3 respectively.Low-frequency interference signal in picture signal can be eliminated or suppress by the present invention, and the phase and frequency of the viewdata signal in viewdata signal can also be amplified by the present invention, thus improve the effect that picture signal is processed by the present invention, effectively ensure that the accuracy of the viewdata signal that global position system receives.
Description
Technical field
The present invention relates to a kind of processing system, specifically refer to a kind of based on the high property of the polynary cruising device from cognition technology
Can signal processing system.
Background technology
Vehicle is the vehicles that society is indispensable, and the vehicle grown with each passing day also brings the road become increasingly conspicuous
Block up, Frequent Accidents, energy waste, the problem such as air pollution.Along with the development of the technology such as the Internet, Internet of Things, polynary self-induction
Know arising at the historic moment of technology, its integrated application wisdom sensing, communication network, the technology such as embedded.This is polynary from cognition technology mesh
Before must be widely used in automobile vehicle condition and Traffic Information are carried out complete perception and process, it is achieved people and car, Che Yuyun,
The multidimensional such as car and car are mutual, make vehicle and traffic administration the most intelligent.Wherein, the polynary Cruising device for car from cognition technology is
Current high-end automobile uses most intelligent apparatus, and this intelligent apparatus can pass through the infrared pick-up head road to vehicle heading
Face situation is acquired, and uses after being processed picture signal by image-signal processing system Internet of Things to pass technical transmission
To global position system, global position system then provides automatic cruising by communication network for driver.
But, existing exist at signal based on the polynary cruising device high performance signal processing system from cognition technology
Reason weak effect, the viewdata signal causing global position system to obtain is inaccurate, and causing cruising device can not be well vapour
Car cruises, thus serious have impact on road traffic safety.
The high based on the polynary cruising device from cognition technology of picture signal treatment effect can be improved therefore it provides a kind of
Performance signals processing system then seems excellent for important.
Summary of the invention
It is an object of the invention to overcome existing based on polynary at the cruising device high performance signal of cognition technology
There is the defect of signal processing weak effect in reason system, the present invention provides a kind of based on polynary high from the cruising device of cognition technology
Performance signals processing system.
The present invention is achieved through the following technical solutions: based on the polynary cruising device high performance signal from cognition technology
Processing system, mainly by processing chip U, infrared pick-up head WS, field effect transistor MOS1, audion VT3, positive pole is after resistance R6
Be connected with the drain electrode of field effect transistor MOS1, polar capacitor C6, P pole that negative pole is connected with the SCLK pin of process chip U with
The diode D3 that the grid of field effect transistor MOS1 is connected, N pole is connected with the SCLK pin processing chip U after resistance R7,
Polar capacitor C7, the P pole that positive pole is connected with the source electrode of field effect transistor MOS1, negative pole is connected with the PIN pin of process chip U
Be connected with the SDI pin processing chip U, N pole after resistance R8 with the diode D4 that is connected of SHD pin processing chip U,
Negative pole and process chip U the polar capacitor C8 that SHP pin is connected, positive pole is connected with the base stage of audion VT3, respectively with
The picture signal pretreatment circuit that the VC pin of process chip U and infrared pick-up head WS are connected, is serially connected in picture signal
Synchronizing signal between pretreatment circuit and the PIN pin processing chip U adjusts circuit, respectively with the PIUT pipe processing chip U
The output signal amplification circuit that foot is connected with the emitter stage of audion VT3, and it is serially connected in output signal amplification circuit and place
Differential amplifier circuit composition between the SCLK pin of reason chip U；The SDI pin of described process chip U is also connected with PIN pin
Connect, its SHD pin be also connected with SHP pin after ground connection；The grounded drain of described field effect transistor MOS1；Described audion VT3
Colelctor electrode with process chip U RST pin be connected；The VC pin of described process chip U and outside 12V DC source phase
Connect.
Described synchronizing signal adjusts circuit by audion VT6, audion VT9, audion VT10, audion VT11, positive pole
After resistance R27 the base stage with audion VT8 be connected, the polar capacitor C18 of minus earth, positive pole after resistance R26 with pole
The negative pole of property electric capacity C18 is connected, the polar capacitor C19 of minus earth, N pole is connected with the colelctor electrode of audion VT8, P pole
The diode D11 that negative pole with polar capacitor C18 is connected after resistance R28, positive pole is connected with the base stage of audion VT8,
The polar capacitor C20 that negative pole emitter stage with audion VT8 after resistance R29 is connected, the P pole phase of positive pole and diode D11
Connect, polar capacitor C21, the P pole that is connected with the base stage of audion VT9 of negative pole after resistance R30 with the transmitting of audion VT9
The diode D12 that pole is connected, N pole is connected with the negative pole of polar capacitor C20, one end is connected with the N pole of diode D12,
The other end be connected with the emitter stage of audion VT10 after the resistance R31 of ground connection, positive pole after resistance R32 with audion VT11's
Polar capacitor C22, the P pole that colelctor electrode is connected, negative pole is connected with the colelctor electrode of audion VT10 and the collection of audion VT10
The diode D13 that electrode is connected, N pole is connected with the base stage of audion VT11, and the transmitting of one end and audion VT11
Pole is connected, the resistance R33 of other end ground connection composition；The positive pole of described polar capacitor C19 also base stage with audion VT8 is connected
Connect；The base stage of described audion VT8 is connected with picture signal pretreatment circuit；The colelctor electrode of described audion VT9 respectively with
The negative pole of polar capacitor C18 is connected with the positive pole of polar capacitor C22；The base stage of described audion VT10 and the P of diode D12
Pole is connected；The positive pole of described polar capacitor C22 is also connected with the PIN pin processing chip U.
Further, described differential amplifier circuit is by amplifier, and amplifier P4, audion VT7, after negative electrode resistance R16
Be connected with the positive pole of amplifier P3, polar capacitor C13 that positive pole is connected with the SCLK pin of process chip U, negative pole with put
The polarity that the negative pole of big device P3 is connected, positive pole is sequentially connected through resistance R19 outfan with amplifier P3 after resistance R17
Electric capacity C14, P pole negative pole with amplifier P3 after adjustable resistance R20 is connected, N pole is connected with the emitter stage of audion VT7
Diode D9, positive pole P pole with diode D9 after resistance R21 is connected, negative pole after resistance R22 with audion VT7's
The polar capacitor C16 that base stage is connected, one end is connected with the colelctor electrode of audion VT7, the resistance R23 of other end ground connection, just
The polar capacitor C17 that pole is connected with the negative pole of amplifier P4, negative pole base stage with audion VT7 after resistance R24 is connected,
P pole outfan with amplifier P4 after resistance R25 is connected, the output of diode D10, the P pole of N pole ground connection and amplifier P3
The diode D8 that end is connected, N pole outfan with amplifier P4 after resistance R18 is connected, and positive pole and diode D8
The polar capacitor C15 that N pole is connected, negative pole is connected with the positive pole of amplifier P4 composition；The negative pole of described polar capacitor C17
Ground connection；The outfan of described amplifier P4 is also connected with output signal amplification circuit.
Described picture signal pretreatment electricity routing amplifier P1, audion VT1, audion VT2, positive pole is with amplifier P1's
The polar capacitor C2 that positive pole is connected, negative pole is connected with the signal output stage of infrared pick-up head WS, one end and amplifier P1
The resistance R3 that negative pole is connected, the other end is connected with the base stage of audion VT1, positive pole is connected with the negative pole of amplifier P1
Connect, polar capacitor C4 that negative pole is connected with the base stage of audion VT1, negative pole is connected with the negative pole of amplifier P1, positive pole with
Polar capacitor C5, the N pole that the base stage of audion VT2 is connected negative pole with amplifier P1 after resistance R4 is connected, P pole is through electricity
The diode D2 being connected with the base stage of audion VT2 after resistance R5, positive pole is connected with the outfan of amplifier P1, negative pole and three
Polar capacitor C3, the P pole that the emitter stage of pole pipe VT2 is connected positive pole with amplifier P1 after resistance R2 is connected, N pole and pole
The diode D1 that the negative pole of property electric capacity C3 is connected, negative pole is connected with the positive pole of amplifier P1, positive pole is after adjustable resistance R1
The polar capacitor C1 being connected with the N pole of diode D1, and one end is connected with the anelectrode of amplifier P1, the other end and place
The inductance L1 composition that the VC pin of reason chip U is connected；The negative electrode ground connection of described amplifier P1；The collection of described audion VT1
Electrode ground connection, its emitter stage are connected with the N pole of diode D2；The grounded collector of described audion VT2, its emitter stage also with
The positive pole of polar capacitor C22 is connected.
Described signal output amplifier, by field effect transistor MOS2, audion VT4, audion VT5, audion VT6, amplifies
Device P2, positive pole emitter stage with audion VT6 after resistance R13 is connected, negative pole after inductance L2 with the positive pole of amplifier P2
Polar capacitor C11, the P pole being connected is connected with the base stage of audion VT6, N pole after resistance R14 with the negative pole of amplifier P2
The diode D7 being connected, positive pole colelctor electrode with audion VT6 after resistance R15 is connected, negative pole is negative with amplifier P2's
Pole be connected after the polar capacitor C12 of ground connection, positive pole emitter stage with audion VT4 after resistance R10 is connected, negative pole with put
The polar capacitor C10 that the outfan of big device P2 is connected, one end is connected with the outfan of amplifier P2, the other end is electric with polarity
Hold adjustable resistance R12, the P pole that is connected of negative pole of the C11 colelctor electrode with audion VT5 after resistance R11 be connected, N pole with
The diode D6 that the negative pole of polar capacitor C11 is connected, negative pole is connected with the source electrode of field effect transistor MOS2, positive pole and audion
Polar capacitor C9, the P pole that the base stage of VT4 is connected is connected with the outfan of amplifier P4, the source of N pole and field effect transistor MOS2
Pole be connected after the diode D5 of ground connection, and one end is connected with the colelctor electrode of audion VT4, the resistance R9 of other end ground connection
Composition；The drain electrode of described field effect transistor MOS2 is connected with the outfan of amplifier P4, the emitter stage of its grid and audion VT5
It is connected；The colelctor electrode of described audion VT5 also emitter stage with audion VT6 is connected, its base stage with process chip U's
POUT pin is connected；The emitter stage of described audion VT6 also emitter stage with audion VT3 is connected；Described audion VT4
Emitter stage be also connected with the N pole of diode D6；Defeated as signal output amplifier of the outfan of described amplifier P2
Go out end.
For the practical effect of the present invention, described process chip U the most preferentially have employed the integrated chip of XRD4460 and comes real
Existing.
The present invention compared with prior art has the following advantages and beneficial effect:
(1) low-frequency interference signal in picture signal can be eliminated or suppress by the present invention, and can be to anti-interference process
After image frequency be amplified, the frequency making image is more steady；And the present invention can also be to the image in viewdata signal
The phase and frequency of data signal is amplified, thus improves the effect that picture signal is processed by the present invention, effectively guarantees
The accuracy of the viewdata signal that global position system receives, makes the cruising device well cruise for automobile, from
And ensure that road traffic safety.
(2) the row vibration in picture signal and field oscillation and field fractional frequency signal can be adjusted by the present invention, make them
Frequency consistent with input signal with phase place, ensure that the accuracy that picture signal is processed by the present invention.
(3) resistance to pressure of the frequency of picture signal and dynamic range can be adjusted by the present invention, and can be believed by electric current
Number middle zero migration control within 0.5nA, make the quiescent point of signal keep stable, thus improve the present invention couple
The effect that picture signal processes.
(4) the process chip U of the present invention the most preferentially uses the integrated chip of the XRD4460 that knows clearly to realize, and this chip is with peripheral
Circuit combines, and can effectively improve stability and the reliability of the present invention.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of the present invention.
Fig. 2 is the electrical block diagram of the differential amplifier circuit of the present invention.
Fig. 3 is the electrical block diagram of the synchronizing signal adjustment circuit of the present invention.
Detailed description of the invention
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
As it is shown in figure 1, the present invention is mainly by processing chip U, infrared pick-up head WS, field effect transistor MOS1, audion
VT3, resistance R6, resistance R7, resistance R8, polar capacitor C6, polar capacitor C7, polar capacitor C8, diode D3, diode D4,
Synchronizing signal adjusts circuit, differential amplifier circuit, picture signal pretreatment circuit, and output signal amplification circuit composition.
During connection, the drain electrode with field effect transistor MOS1 after resistance R6 of the positive pole of polar capacitor C6 is connected, negative pole and place
The SCLK pin of reason chip U is connected.The P pole of diode D3 is connected with the grid of field effect transistor MOS1, and N pole is after resistance R7
It is connected with the SCLK pin processing chip U.The positive pole of polar capacitor C7 is connected with the source electrode of field effect transistor MOS1, negative pole with
The PIN pin processing chip U is connected.
Meanwhile, the P pole of diode D4 with process chip U SDI pin be connected, N pole after resistance R8 with process chip U
SHD pin be connected.The negative pole of polar capacitor C8 is connected with the SHP pin processing chip U, and positive pole is with audion VT3's
Base stage is connected.Picture signal pretreatment circuit is connected with the VC pin processing chip U and infrared pick-up head WS respectively.
Synchronizing signal adjusts circuit and is serially connected between picture signal pretreatment circuit and the PIN pin processing chip U.Output signal is amplified
Circuit is connected with the PIUT pin of process chip U and the emitter stage of audion VT3 respectively.Differential amplifier circuit is serially connected in output
Between signal amplification circuit and the SCLK pin processing chip U.
After the SDI pin of described process chip U is also connected with PIN pin, its SHD pin is also connected with SHP pin
Ground connection；The grounded drain of described field effect transistor MOS1；The colelctor electrode of described audion VT3 is connected with the RST pin processing chip U
Connect；The VC pin of described process chip U is connected with outside 12V DC source.
During enforcement, for the practical effect of the present invention, it is integrated that described process chip U the most preferentially have employed XRD4460
Chip realizes, and the integrated chip of this XRD4460 is image signal processing chip.Described infrared pick-up head WS the most preferentially uses
The STM-798 infrared pick-up head that Saite is beautiful realizes.Meanwhile, described field effect transistor MOS1, audion VT3, resistance R6,
Resistance R7, resistance R8, polar capacitor C6, polar capacitor C7, polar capacitor C8, diode D3 and diode D4 then define demagnetization
Circuit, this circuit can eliminate processing electromagnetic interference signal peripheral for chip U or suppress, make process chip U to image
The process chip U accuracy to signal processing will not be effectively raised by extraneous electromagnetic interference when signal processes.
The outfan of described output signal amplification circuit then passes through the wireless signal transmitter of data wire and cruising device when implementing
Signal input part be connected.
Further, described picture signal pretreatment electricity routing amplifier P1, audion VT1, audion VT2, adjustable electric
Resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, polar capacitor C1, polar capacitor C2, polar capacitor C3, polar capacitor C4,
Polar capacitor C5, diode D1, and diode D2 form.
During connection, the positive pole of polar capacitor C2 is connected with the positive pole of amplifier P1, and negative pole is with infrared pick-up head WS's
Signal output stage is connected.One end of resistance R3 is connected with the negative pole of amplifier P1, the base stage phase of the other end and audion VT1
Connect.The positive pole of polar capacitor C4 is connected with the negative pole of amplifier P1, and negative pole is connected with the base stage of audion VT1.Polarity
The negative pole of electric capacity C5 is connected with the negative pole of amplifier P1, and positive pole is connected with the base stage of audion VT2.The N pole of diode D2
After resistance R4, the negative pole with amplifier P1 is connected, and P pole base stage with audion VT2 after resistance R5 is connected.
Meanwhile, the positive pole of polar capacitor C3 is connected with the outfan of amplifier P1, negative pole and the emitter stage of audion VT2
It is connected.The P pole of diode D1 positive pole with amplifier P1 after resistance R2 is connected, the negative pole phase of N pole and polar capacitor C3
Connect.The negative pole of polar capacitor C1 is connected with the positive pole of amplifier P1, positive pole after adjustable resistance R1 with the N pole of diode D1
It is connected.One end of inductance L1 is connected with the anelectrode of amplifier P1, and the other end is connected with the VC pin processing chip U.
The negative electrode ground connection of described amplifier P1；The grounded collector of described audion VT1, its emitter stage and diode D2
N pole be connected；The grounded collector of described audion VT2, its emitter stage also positive pole with polar capacitor C22 is connected.
Further, described signal output amplifier by field effect transistor MOS2, audion VT4, audion VT5, three
Pole pipe VT6, amplifier P2, resistance R9, resistance R10, resistance R11, adjustable resistance R12, resistance R13, resistance R14, resistance R15,
Polar capacitor C9, polar capacitor C10, polar capacitor C11, polar capacitor C12, diode D5, diode D6, diode D7, with
And inductance L2 composition.
During connection, the positive pole of polar capacitor C11 emitter stage with audion VT6 after resistance R13 is connected, and negative pole is through electricity
It is connected with the positive pole of amplifier P2 after sense L2.The P pole of diode D7 is connected with the base stage of audion VT6, and N pole is through resistance
After R14, the negative pole with amplifier P2 is connected.The positive pole of polar capacitor C12 after resistance R15 with the colelctor electrode phase of audion VT6
Connect, negative pole be connected with the negative pole of amplifier P2 after ground connection.The positive pole of polar capacitor C10 after resistance R10 with audion VT4
Emitter stage be connected, negative pole is connected with the outfan of amplifier P2.
Meanwhile, one end of adjustable resistance R12 is connected with the outfan of amplifier P2, and the other end is with polar capacitor C11's
Negative pole is connected.The P pole of diode D6 colelctor electrode with audion VT5 after resistance R11 is connected, N pole and polar capacitor C11
Negative pole be connected.The negative pole of polar capacitor C9 is connected with the source electrode of field effect transistor MOS2, positive pole and the base stage of audion VT4
It is connected.The P pole of diode D5 is connected with the outfan of amplifier P4, after N pole is connected with the source electrode of field effect transistor MOS2
Ground connection.One end of resistance R9 is connected with the colelctor electrode of audion VT4, other end ground connection.
The drain electrode of described field effect transistor MOS2 is connected with the outfan of amplifier P4, and its grid is sent out with audion VT5's
Emitter-base bandgap grading is connected；The colelctor electrode of described audion VT5 also emitter stage with audion VT6 is connected, its base stage with process chip U
POUT pin be connected；The emitter stage of described audion VT6 also emitter stage with audion VT3 is connected；Described audion
The emitter stage of VT4 is also connected with the N pole of diode D6；The outfan of described amplifier P2 is as signal output amplifier
Outfan is also then connected by the signal input part of data wire with the wireless signal transmitter of cruising device.
As in figure 2 it is shown, described differential amplifier circuit is by amplifier, amplifier P4, audion VT7, resistance R16, resistance
R17, resistance R18, resistance R19, adjustable resistance R20, resistance R21, resistance R22, resistance R23, resistance R24, resistance R25, polarity
Electric capacity C13, polar capacitor C14, polar capacitor C15, polar capacitor C16, polar capacitor C17, diode D8, diode 9, and
Diode D10 forms.
During connection, it is connected with the positive pole of amplifier P3 after the negative electrode resistance R16 of polar capacitor C13, positive pole and process
The SCLK pin of chip U is connected.The negative pole of polar capacitor C14 is connected with the negative pole of amplifier P3, and positive pole is sequentially through resistance
After R19 and resistance R17, the outfan with amplifier P3 is connected.The P pole of diode D9 after adjustable resistance R20 with amplifier P3
Negative pole be connected, N pole is connected with the emitter stage of audion VT7.
Wherein, the positive pole of polar capacitor C16 P pole with diode D9 after resistance R21 is connected, and negative pole is through resistance R22
Base stage with audion VT7 is connected afterwards.One end of resistance R23 is connected with the colelctor electrode of audion VT7, other end ground connection.
The positive pole of polar capacitor C17 is connected with the negative pole of amplifier P4, and negative pole base stage with audion VT7 after resistance R24 is connected
Connect.The P pole of diode D10 outfan with amplifier P4 after resistance R25 is connected, N pole ground connection.
Meanwhile, the P pole of diode D8 is connected with the outfan of amplifier P3, N pole after resistance R18 with amplifier P4's
Outfan is connected.The positive pole of polar capacitor C15 is connected with the N pole of diode D8, and negative pole is connected with the positive pole of amplifier P4
Connect.The minus earth of described polar capacitor C17；The outfan of described amplifier P4 is also connected with output signal amplification circuit.
As it is shown on figure 3, described synchronizing signal adjusts circuit by audion VT8, audion VT9, audion VT10, audion
VT11, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, resistance R32, resistance R33, polar capacitor
C18, polar capacitor C19, polar capacitor C20, polar capacitor C21, polar capacitor C22, diode D11, diode D12, and
Diode D13 forms.
During connection, the positive pole of polar capacitor C18 base stage with audion VT8 after resistance R27 is connected, minus earth.
The positive pole of polar capacitor C19 negative pole with polar capacitor C18 after resistance R26 is connected, minus earth.The N pole of diode D11
Being connected with the colelctor electrode of audion VT8, P pole negative pole with polar capacitor C18 after resistance R28 is connected.Polar capacitor C20
Positive pole be connected with the base stage of audion VT8, negative pole emitter stage with audion VT8 after resistance R29 is connected.
Wherein, the positive pole of polar capacitor C21 is connected with the P pole of diode D11, the base stage phase of negative pole and audion VT9
Connect.The P pole of diode D12 emitter stage with audion VT9 after resistance R30 is connected, and N pole is negative with polar capacitor C20's
Pole is connected.One end of resistance R31 is connected with the N pole of diode D12, and the other end is connected with the emitter stage of audion VT10
Rear ground connection.
Meanwhile, the positive pole of polar capacitor C22 colelctor electrode with audion VT11 after resistance R32 is connected, negative pole and three
The colelctor electrode of pole pipe VT10 is connected.The P pole of diode D13 is connected with the colelctor electrode of audion VT10, N pole and audion
The base stage of VT11 is connected.One end of resistance R33 is connected with the emitter stage of audion VT11, other end ground connection.
The positive pole of described polar capacitor C19 also base stage with audion VT8 is connected；The base stage of described audion VT8 with
Picture signal pretreatment circuit is connected；The colelctor electrode of described audion VT9 is electric with the negative pole of polar capacitor C18 and polarity respectively
The positive pole holding C22 is connected；The base stage of described audion VT10 is connected with the P pole of diode D12；Described polar capacitor C22
Positive pole also with process chip U PIN pin be connected.
During operation, the polar capacitor C1 in the picture signal pretreatment circuit of this image-signal processing system, polar capacitor
Low-frequency interference signal in picture signal can be carried out by the filter circuit that C2, adjustable resistance R1, resistance R2 and diode D1 are formed
Eliminate or suppression；Filtered image is then believed by the three fortune amplifying circuits that amplifier P1, audion VT1 and audion VT2 are formed
Number image frequency be amplified, the frequency making image is more steady.Meanwhile, the signal output of this image-signal processing system is amplified
The low frequency that audion VT4, polar capacitor C9, polar capacitor C10, diode D6 and audion VT5 in circuit is formed amplifies electricity
Road, the low-frequency amplifier circuit that amplifier P2, polar capacitor C11, audion VT6 and polar capacitor C12 are formed, low frequency amplifies electricity
Road and low-frequency amplifier circuit together form signal output amplifier, and this signal output amplifier can be to viewdata signal
In the phase and frequency of viewdata signal be amplified, thus improve the effect that picture signal is processed by the present invention, have
The accuracy that ensure that viewdata signal that global position system receives of effect, makes cruising device well to carry out for automobile
Cruise, ensures that road traffic safety.
Meanwhile, the present invention is provided with differential amplification between output signal amplification circuit and the SCLK pin processing chip U
Circuit, the tune resistance R20 in this differential amplifier circuit is the emitter resistance of audion VT7, or claims emitter resistance, adjustable resistance
R20 effect is stable quiescent point, does drift and further faces upward system, and can the middle zero migration of current signal be controlled
Within 0.5nA, the quiescent point of signal is made to keep stable.Audion VT7 commonly uses the great amplifier of equivalent internal resistance and carrys out generation
Replace, in order to more effectively improve the effect of suppression drift.Polar capacitor C14 is used for compensating the direct current pressure at adjustable resistance R20 two ends
Fall, and the scope of output current signal can be expanded, the resting potential making two base stages is zero.Meanwhile, amplifier P3 and amplifier P4
Defining second order amplifier, the resistance to pressure of the frequency of picture signal and dynamic range can be adjusted by this second order amplifier, make
The frequency of picture signal is more stable, thus this this differential amplifier circuit can effectively improve the effect that picture signal is processed by the present invention
Really.
Wherein, in order to enable that the row vibration in picture signal and field oscillation and field fractional frequency signal are adjusted, them are made
Frequency consistent with input signal with phase place, the present invention picture signal pretreatment circuit and process chip U PIN pin between
It is provided with synchronizing signal and adjusts circuit.This synchronizing signal adjusts the picture signal of circuit reception by isolation resistance R26, polarity electricity
Hold C18, diode D11 to be added in the base stage of audion VT8.When non-plus signal, audion VT8 ends, when lock-out pulse arrives
When coming, diode D11, audion VT8 are both turned on, and polar capacitor C18 is electrically charged, owing to charge constant is little, and polar capacitor
The voltage close to lock-out pulse amplitude it is filled with on C18.After the synchronous head past, polar capacitor C18 discharges through resistance R27, the time
Constant is relatively big and electric discharge is very slow, so there is a reverse bias for audion VT8 on polar capacitor C18.It makes three
Pole pipe VT8 keeps cut-off during scan(ing) stroke, thus audion VT8 colelctor electrode isolates the row of negative polarity, field composite signal
Lock-out pulse, and automatically the row vibration in signal and field oscillation and field fractional frequency signal being adjusted, make they frequency and
Phase place is consistent with input signal.
Meanwhile, the process chip U of the present invention the most preferentially uses the integrated chip of the XRD4460 that knows clearly to realize, and this chip is with outer
Enclose circuit to combine, can effectively improve stability and the reliability of the present invention.As it has been described above, just can well be realized this
Bright.
Claims (6)
1. based on the polynary cruising device high performance signal processing system from cognition technology, mainly by processing chip U, infrared ray
Photographic head WS, field effect transistor MOS1, audion VT3, positive pole drain electrode with field effect transistor MOS1 after resistance R6 is connected, negative pole
Be connected with the grid of field effect transistor MOS1 with polar capacitor C6, the P pole that is connected of SCLK pin processing chip U, N pole is through electricity
The diode D3 being connected with the SCLK pin processing chip U after resistance R7, positive pole is connected with the source electrode of field effect transistor MOS1, bears
Polar capacitor C7, the P pole that pole is connected with the PIN pin processing chip U is connected with the SDI pin processing chip U, N pole warp
With the diode D4 that is connected of SHD pin processing chip U after resistance R8, negative pole is connected with the SHP pin of process chip U,
The polar capacitor C8 that positive pole is connected with the base stage of audion VT3, respectively with VC pin and the infrared pick-up processing chip U
The head picture signal pretreatment circuit that is connected of WS, be serially connected in picture signal pretreatment circuit with the PIN pin processing chip U it
Between synchronizing signal adjust circuit, the output being connected respectively with the emitter stage processing the PIUT pin of chip U and audion VT3
Signal amplification circuit, and the differential amplification electricity being serially connected between output signal amplification circuit and the SCLK pin processing chip U
Road forms；The SDI pin of described process chip U is also connected with PIN pin, its SHD pin is also connected with SHP pin is followed by
Ground；The grounded drain of described field effect transistor MOS1；The colelctor electrode of described audion VT3 is connected with the RST pin processing chip U
Connect；The VC pin of described process chip U is connected with outside 12V DC source.
The most according to claim 1 based on the polynary cruising device high performance signal processing system from cognition technology, its
Being characterised by, described synchronizing signal adjusts circuit by audion VT6, audion VT9, audion VT10, audion VT11, positive pole
After resistance R27 the base stage with audion VT8 be connected, the polar capacitor C18 of minus earth, positive pole after resistance R26 with pole
The negative pole of property electric capacity C18 is connected, the polar capacitor C19 of minus earth, N pole is connected with the colelctor electrode of audion VT8, P pole
The diode D11 that negative pole with polar capacitor C18 is connected after resistance R28, positive pole is connected with the base stage of audion VT8,
The polar capacitor C20 that negative pole emitter stage with audion VT8 after resistance R29 is connected, the P pole phase of positive pole and diode D11
Connect, polar capacitor C21, the P pole that is connected with the base stage of audion VT9 of negative pole after resistance R30 with the transmitting of audion VT9
The diode D12 that pole is connected, N pole is connected with the negative pole of polar capacitor C20, one end is connected with the N pole of diode D12,
The other end be connected with the emitter stage of audion VT10 after the resistance R31 of ground connection, positive pole after resistance R32 with audion VT11's
Polar capacitor C22, the P pole that colelctor electrode is connected, negative pole is connected with the colelctor electrode of audion VT10 and the collection of audion VT10
The diode D13 that electrode is connected, N pole is connected with the base stage of audion VT11, and the transmitting of one end and audion VT11
Pole is connected, the resistance R33 of other end ground connection composition；The positive pole of described polar capacitor C19 also base stage with audion VT8 is connected
Connect；The base stage of described audion VT8 is connected with picture signal pretreatment circuit；The colelctor electrode of described audion VT9 respectively with
The negative pole of polar capacitor C18 is connected with the positive pole of polar capacitor C22；The base stage of described audion VT10 and the P of diode D12
Pole is connected；The positive pole of described polar capacitor C22 is also connected with the PIN pin processing chip U.
The most according to claim 2 based on the polynary cruising device high performance signal processing system from cognition technology, its
Being characterised by, described differential amplifier circuit is by amplifier, and amplifier P4, audion VT7, with amplifier after negative electrode resistance R16
The polar capacitor C13 that the positive pole of P3 is connected, positive pole is connected with the SCLK pin of process chip U, negative pole is with amplifier P3's
The polar capacitor C14 that negative pole is connected, positive pole is sequentially connected through resistance R19 outfan with amplifier P3 after resistance R17,
P pole diode that negative pole is connected, N pole is connected with the emitter stage of audion VT7 with amplifier P3 after adjustable resistance R20
D9, positive pole P pole with diode D9 after resistance R21 is connected, negative pole base stage with audion VT7 after resistance R22 is connected
The polar capacitor C16 connect, one end is connected with the colelctor electrode of audion VT7, the resistance R23 of other end ground connection, positive pole and amplification
Polar capacitor C17, the P pole that the negative pole of device P4 is connected, negative pole base stage with audion VT7 after resistance R24 is connected is through electricity
Be connected with the outfan of amplifier P4 after resistance R25, diode D10, the P pole of N pole ground connection is connected with the outfan of amplifier P3
Connect, diode D8 that N pole outfan with amplifier P4 after resistance R18 is connected, and the N pole phase of positive pole and diode D8
The polar capacitor C15 composition that connection, negative pole are connected with the positive pole of amplifier P4；The minus earth of described polar capacitor C17；Institute
The outfan stating amplifier P4 is also connected with output signal amplification circuit.
The most according to claim 3 based on the polynary cruising device high performance signal processing system from cognition technology, its
It is characterised by, described picture signal pretreatment electricity routing amplifier P1, audion VT1, audion VT2, positive pole and amplifier P1
The polar capacitor C2 that positive pole is connected, negative pole is connected with the signal output stage of infrared pick-up head WS, one end and amplifier
The resistance R3 that the negative pole of P1 is connected, the other end is connected with the base stage of audion VT1, positive pole is connected with the negative pole of amplifier P1
Connect, polar capacitor C4 that negative pole is connected with the base stage of audion VT1, negative pole is connected with the negative pole of amplifier P1, positive pole with
Polar capacitor C5, the N pole that the base stage of audion VT2 is connected negative pole with amplifier P1 after resistance R4 is connected, P pole is through electricity
The diode D2 being connected with the base stage of audion VT2 after resistance R5, positive pole is connected with the outfan of amplifier P1, negative pole and three
Polar capacitor C3, the P pole that the emitter stage of pole pipe VT2 is connected positive pole with amplifier P1 after resistance R2 is connected, N pole and pole
The diode D1 that the negative pole of property electric capacity C3 is connected, negative pole is connected with the positive pole of amplifier P1, positive pole is after adjustable resistance R1
The polar capacitor C1 being connected with the N pole of diode D1, and one end is connected with the anelectrode of amplifier P1, the other end and place
The inductance L1 composition that the VC pin of reason chip U is connected；The negative electrode ground connection of described amplifier P1；The collection of described audion VT1
Electrode ground connection, its emitter stage are connected with the N pole of diode D2；The grounded collector of described audion VT2, its emitter stage also with
The positive pole of polar capacitor C22 is connected.
The most according to claim 4 based on the polynary cruising device high performance signal processing system from cognition technology, its
Being characterised by, described signal output amplifier, by field effect transistor MOS2, audion VT4, audion VT5, audion VT6, is put
Big device P2, positive pole emitter stage with audion VT6 after resistance R13 is connected, negative pole after inductance L2 with amplifier P2 just
Polar capacitor C11, the P pole that pole is connected is connected with the base stage of audion VT6, N pole negative with amplifier P2 after resistance R14
The diode D7 that pole is connected, positive pole colelctor electrode with audion VT6 after resistance R15 is connected, negative pole is with amplifier P2's
Negative pole be connected after the polar capacitor C12 of ground connection, positive pole emitter stage with audion VT4 after resistance R10 is connected, negative pole with
The polar capacitor C10 that the outfan of amplifier P2 is connected, one end is connected with the outfan of amplifier P2, the other end and polarity
Adjustable resistance R12, the P pole that the negative pole of electric capacity C11 is connected colelctor electrode with audion VT5 after resistance R11 is connected, N pole
The diode D6 being connected with the negative pole of polar capacitor C11, negative pole is connected with the source electrode of field effect transistor MOS2, positive pole and three poles
Polar capacitor C9, the P pole that the base stage of pipe VT4 is connected is connected with the outfan of amplifier P4, N pole and field effect transistor MOS2
Source electrode be connected after the diode D5 of ground connection, and one end is connected with the colelctor electrode of audion VT4, the resistance of other end ground connection
R9 forms；The drain electrode of described field effect transistor MOS2 is connected with the outfan of amplifier P4, the transmitting of its grid and audion VT5
Pole is connected；The colelctor electrode of described audion VT5 also emitter stage with audion VT6 is connected, its base stage with process chip U's
POUT pin is connected；The emitter stage of described audion VT6 also emitter stage with audion VT3 is connected；Described audion VT4
Emitter stage be also connected with the N pole of diode D6；Defeated as signal output amplifier of the outfan of described amplifier P2
Go out end.
The most according to claim 5 based on the polynary cruising device high performance signal processing system from cognition technology, its
Being characterised by, described process chip U is the integrated chip of XRD4460.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610769311.3A CN106131377A (en) | 2016-08-30 | 2016-08-30 | Based on the polynary cruising device high performance signal processing system from cognition technology |
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| CN201610769311.3A CN106131377A (en) | 2016-08-30 | 2016-08-30 | Based on the polynary cruising device high performance signal processing system from cognition technology |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109802748A (en) * | 2019-03-18 | 2019-05-24 | 延锋伟世通电子科技（上海）有限公司 | A kind of highly resistance immunity difference camera signals processing circuit |
-
2016
- 2016-08-30 CN CN201610769311.3A patent/CN106131377A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109802748A (en) * | 2019-03-18 | 2019-05-24 | 延锋伟世通电子科技（上海）有限公司 | A kind of highly resistance immunity difference camera signals processing circuit |
| CN109802748B (en) * | 2019-03-18 | 2023-08-25 | 延锋伟世通电子科技（上海）有限公司 | High-immunity differential camera signal processing circuit |
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