CN205681612U - A kind of signal band gain formula audio signal processing - Google Patents
A kind of signal band gain formula audio signal processing Download PDFInfo
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- CN205681612U CN205681612U CN201620514069.0U CN201620514069U CN205681612U CN 205681612 U CN205681612 U CN 205681612U CN 201620514069 U CN201620514069 U CN 201620514069U CN 205681612 U CN205681612 U CN 205681612U
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Abstract
The utility model discloses a kind of signal band gain formula audio signal processing, it is characterized in that, mainly by process chip U, triode VT2, amplifier P2, polar capacitor C4, diode D3, positive pole is connected with the negative input of amplifier P2, the polar capacitor C5 of minus earth, the signal amplification circuit being connected with the N pole processing chip U and diode D3 respectively, the linear filtering circuit being connected with electrode input end and the signal amplification circuit of amplifier P2 respectively, and the FET squelch circuit composition being connected with emitter stage and the process chip U of triode VT2 respectively.The utility model can not only effectively eliminate the interference signal in audio signal, and the frequency bandwidth of audio signal can be adjusted, when being effectively prevented audio signal output, distortion occurs, thus the noise that the utility model is when having effectively eliminated audio signal transmission, it is ensured that the audibility of user.
Description
Technical field
The utility model relates to electronic applications, specifically, is a kind of signal band gain formula audio signal processing.
Background technology
Audio reception device has been daily life, study, indispensable instrument in work, and audio reception device
Working stability be otherwise depending on audio frequency processing system.But existing audio frequency processing system cannot be to doing in audio signal
Disturb signal to eliminate, it is impossible to be adjusted the frequency bandwidth of audio signal, thus cause audio reception device output signal
When there will be the situation of noise, distortion, have a strong impact on the audibility of user.
Therefore it provides a kind of interference signal that can eliminate in audio signal, again can be to the width of the frequency band of audio signal
The audio frequency processing system being adjusted is the task of top priority.
Utility model content
The purpose of this utility model is that the signal processing system overcoming face identification system of the prior art is anti-interference
Ability, it is impossible to the defect that the frequency bandwidth of audio signal is adjusted, a kind of signal band gain formula audio frequency letter of offer
Number processing system.
The utility model is achieved through the following technical solutions: a kind of signal band gain formula audio signal processing,
It mainly by processing chip U, triode VT2, amplifier P2, is connected with the SADN pin processing chip U after positive electrode resistance R9, bears
The polar capacitor C4 that pole is connected with the base stage of triode VT2 after resistance R11, N pole is connected with the FB pin processing chip U
Connect, diode D3 that P pole is connected with the output of amplifier P2, positive pole is connected with the negative input of amplifier P2, negative
The polar capacitor C5 of pole ground connection, respectively with the signal amplification circuit that is connected of N pole processing chip U and diode D3, respectively with
The linear filtering circuit that the electrode input end of amplifier P2 is connected with signal amplification circuit, and respectively with triode VT2's
The FET squelch circuit composition that emitter stage is connected with process chip U；The colelctor electrode of described triode VT2 and process chip
The GND pin of U is all grounded；The REF pin of described process chip U is connected with LBI pin.
Described linear filtering electricity routing amplifier P1, negative pole is as the input of linear filtering circuit, positive pole and amplifier
The polar capacitor C1 that the electrode input end of P1 is connected, N pole is connected with the output of amplifier P1 after resistance R3, P pole warp
The diode D1 being connected with the electrode input end of amplifier P1 after resistance R1, negative pole is connected with the output of amplifier P1,
The negative pole of the polar capacitor C2 that positive pole is connected with the negative input of amplifier P1 after resistance R4, one end and polar capacitor C2
Be connected, inductance L that the other end is connected with the negative input of amplifier P1, and the negative pole input of one end and amplifier P1
End is connected, other end earth resistance R5 composition；The negative pole of described polar capacitor C2 is connected with the electrode input end of amplifier P2
Connect；The output of described amplifier P1 is connected with signal amplification circuit.
Described signal amplification circuit is by triode VT1, and P pole is connected with the LBI pin processing chip U, N pole is sequentially through electricity
Resistance R7 and after resistance R8 with the diode D2 that is connected of LX pin processing chip U, one end is connected with the N pole of diode D2,
The resistance R6 that the other end is connected with the colelctor electrode of triode VT1, negative pole is connected with the base stage of triode VT1, positive pole with put
The polar capacitor C3 that the output of big device P1 is connected, and one end is connected with the emitter stage of triode VT1, the other end and place
The adjustable resistance R10 composition that the FB pin of reason chip U is connected；The emitter stage of described triode VT1 after adjustable resistance R10 with
The N pole of diode D3 is connected.
Described FET squelch circuit is by FET MOS, and N pole is connected with the grid of FET MOS, P pole warp
The diode D4 being connected with the emitter stage of triode VT2 after resistance R12, negative pole is connected with the drain electrode of FET MOS, just
The polar capacitor C6 that pole is grounded after being connected with the GND pin processing chip U after resistance R13, positive pole is with process chip U's
The polar capacitor C8 that VOUT pin is connected, negative pole is connected with the source electrode of FET MOS after resistance R14, P pole is through resistance
After R15 with process chip U LBO pin be connected, the diode D5 of the output as FET squelch circuit for the N pole, just
N pole with diode D5 after resistance R17, pole is connected, the polar capacitor C7 of minus earth, and one end and FET MOS
Drain electrode be connected, the resistance R16 composition being connected of the other end and polar capacitor C7；The negative pole and two of described polar capacitor C8
The P pole of pole pipe D5 is connected.
For practical effect of the present utility model, described process chip U preferentially have employed as the integrated chip of IW1761
Realize.
The utility model compared with prior art, has the following advantages and beneficial effect:
(1) the utility model can not only effectively eliminate the interference signal in audio signal, and can effectively reduce sound
Frequently the noise of signal, meanwhile, the frequency bandwidth of audio signal can be adjusted by the utility model, is effectively prevented audio frequency letter
During number output distortion occurs, thus noise when the utility model has effectively eliminated audio signal transmission, it is ensured that user's
Audibility.
(2) the frequency bandwidth increase of audio signal can be led the 2 of the frequency bandwidth of existing audio signal by the utility model
More than Bei, thus effectively raise audio signal components, it is ensured that the tonequality of audio reception device output.
(3) the utility model can make the frequency range of audio signal be maintained at 10HZ-22HZ, thus effectively raises sound
Frequency receive equipment output tonequality, it is ensured that during audio signal transmission without noise.
Brief description
Fig. 1 is overall structure schematic diagram of the present utility model.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing thereof, the utility model is described in further detail, but reality of the present utility model
The mode of executing is not limited to this.
Embodiment
As it is shown in figure 1, the utility model is mainly by process chip U, triode VT2, amplifier P2, resistance R9, resistance
R11, polar capacitor C4, polar capacitor C5, diode D3, signal amplification circuit, linear filtering circuit, and FET noise elimination
Circuit forms.
During enforcement, be connected with the SADN pin processing chip U after positive electrode resistance R9 of polar capacitor C4, negative pole is through resistance
It is connected with the base stage of triode VT2 after R11.The N pole of diode D3 is connected with the FB pin processing chip U, P pole and amplification
The output of device P2 is connected.The positive pole of polar capacitor C5 is connected with the negative input of amplifier P2, minus earth.Signal
Amplifying circuit is connected with the N pole processing chip U and diode D3 respectively.The linear filtering circuit positive pole with amplifier P2 respectively
Input is connected with signal amplification circuit.FET squelch circuit emitter stage and the process chip U with triode VT2 respectively
It is connected.The colelctor electrode of described triode VT2 is all grounded with the GND pin processing chip U；The REF pin of described process chip U
It is connected with LBI pin.
Wherein, described linear filtering electricity routing amplifier P1, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, pole
Property electric capacity C1, polar capacitor C2, inductance L, regulation diode D1 composition.
During connection, the negative pole of polar capacitor C1 is as the input of linear filtering circuit and is connected with audio signal sample device
Connect, its positive pole is connected with the electrode input end of amplifier P1.The output with amplifier P1 after resistance R3 of the N pole of diode D1
End is connected, its P pole is connected with the electrode input end of amplifier P1 after resistance R1.The negative pole of polar capacitor C2 and amplifier
The output of P1 is connected, its positive pole is connected with the negative input of amplifier P1 after resistance R4.One end of inductance L and pole
The negative pole of property electric capacity C2 is connected, its other end is connected with the negative input of amplifier P1.One end of resistance R5 and amplification
The negative input of device P1 is connected, its other end ground connection.The negative pole of described polar capacitor C2 inputs with the positive pole of amplifier P2
End is connected；The output of described amplifier P1 is connected with signal amplification circuit.
Further, described signal amplification circuit is by triode VT1, resistance R6, resistance R7, resistance R8, adjustable resistance
R10, polar capacitor C3, and diode D2 form.
During connection, the P pole of diode D2 is connected with the LBI pin processing chip U, its N pole is sequentially through resistance R7 and electricity
It is connected with the LX pin processing chip U after resistance R8.One end of resistance R6 is connected with the N pole of diode D2, its other end with
The colelctor electrode of triode VT1 is connected.The negative pole of polar capacitor C3 is connected with the base stage of triode VT1, its positive pole and amplification
The output of device P1 is connected.One end of adjustable resistance R10 is connected with the emitter stage of triode VT1, its other end and process
The FB pin of chip U is connected.The emitter stage of described triode VT1 is extremely connected with the N of diode D3 after adjustable resistance R10
Connect.
Further, described FET squelch circuit is by FET MOS, resistance R12, resistance R13, resistance R14,
Resistance R15, resistance R16, resistance R17, polar capacitor C6, polar capacitor C7, polar capacitor C8, diode D4, and diode
D5 forms.
During connection, the N pole of diode D4 is connected with the grid of FET MOS, its P pole after resistance R12 with three poles
The emitter stage of pipe VT2 is connected.The negative pole of polar capacitor C6 is connected with the drain electrode of FET MOS, its positive pole is through resistance R13
Ground connection after being connected with the GND pin processing chip U afterwards.The positive pole of polar capacitor C8 is connected with the VOUT pin processing chip U
Connect, its negative pole is connected with the source electrode of FET MOS after resistance R14.
Wherein, the P pole of diode D5 is connected with the LBO pin processing chip U after resistance R15, its N pole is imitated as field
Should the output of pipe squelch circuit being connected with exterior broadcaster.The positive pole of polar capacitor C7 after resistance R17 with diode
The N pole of D5 is connected, its minus earth.One end of resistance R16 is connected with the drain electrode of FET MOS, its other end and pole
Property electric capacity C7 is connected.The negative pole of described polar capacitor C8 is connected with the P pole of diode D5.
During operation, the utility model can not only effectively eliminate the interference signal in audio signal, and can effectively drop
The noise of bass signal, meanwhile, the frequency bandwidth of audio signal can be adjusted by the utility model, is effectively prevented sound
During signal output frequently distortion occurs, thus noise when the utility model has effectively eliminated audio signal transmission, it is ensured that use
The audibility at family.
The utility model the frequency bandwidth increase of audio signal can be led 2 times of the frequency bandwidth of existing audio signal with
On, thus effectively raise audio signal components, it is ensured that the tonequality of audio reception device output.The utility model can make sound
Frequently the frequency range of signal is maintained at 10HZ-22HZ, thus effectively raises the tonequality of audio reception device output, it is ensured that
During audio signal transmission without noise.For practical effect of the present utility model, described process chip U preferentially have employed for
The integrated chip of IW1761 realizes.
According to above-described embodiment, can well realize the utility model.
Claims (5)
1. a signal band gain formula audio signal processing, it is characterised in that mainly by process chip U, triode
VT2, amplifier P2, after positive electrode resistance R9 with process chip U SADN pin be connected, negative pole after resistance R11 with triode
The polar capacitor C4 that the base stage of VT2 is connected, N pole is connected with the FB pin processing chip U, the output of P pole and amplifier P2
The diode D3 that end is connected, positive pole is connected with the negative input of amplifier P2, the polar capacitor C5 of minus earth, respectively
The signal amplification circuit being connected with the N pole processing chip U and diode D3, electrode input end and the letter with amplifier P2 respectively
Number linear filtering circuit that amplifying circuit is connected, and be connected with the emitter stage of triode VT2 and process chip U respectively
FET squelch circuit forms；The colelctor electrode of described triode VT2 is all grounded with the GND pin processing chip U；Described process
The REF pin of chip U is connected with LBI pin.
2. a kind of signal band gain formula audio signal processing according to claim 1, it is characterised in that described line
Property filtered electrical routing amplifier P1, negative pole is as the electrode input end of the input of linear filtering circuit, positive pole and amplifier P1
The polar capacitor C1 being connected, N pole is connected with the output of amplifier P1 after resistance R3, P pole after resistance R1 with amplification
The diode D1 that the electrode input end of device P1 is connected, negative pole is connected with the output of amplifier P1, positive pole is after resistance R4
The polar capacitor C2 being connected with the negative input of amplifier P1, one end is connected with the negative pole of polar capacitor C2, the other end
The inductance L being connected with the negative input of amplifier P1, and one end is connected with the negative input of amplifier P1, another
Termination earth resistance R5 composition；The negative pole of described polar capacitor C2 is connected with the electrode input end of amplifier P2；Described amplifier
The output of P1 is connected with signal amplification circuit.
3. a kind of signal band gain formula audio signal processing according to claim 2, it is characterised in that described letter
Number amplifying circuit is by triode VT1, and P pole is connected with the LBI pin processing chip U, N pole is sequentially after resistance R7 and resistance R8
With the diode D2 that is connected of LX pin processing chip U, one end is connected with the N pole of diode D2, the other end and triode
The resistance R6 that the colelctor electrode of VT1 is connected, negative pole is connected with the base stage of triode VT1, the output of positive pole and amplifier P1
The polar capacitor C3 being connected, and one end is connected with the emitter stage of triode VT1, the FB of the other end and process chip U pipe
The adjustable resistance R10 composition that pin is connected；The emitter stage of described triode VT1 N pole with diode D3 after adjustable resistance R10
It is connected.
4. a kind of signal band gain formula audio signal processing according to claim 3, it is characterised in that described field
Effect pipe squelch circuit by FET MOS, N pole is connected with the grid of FET MOS, P pole after resistance R12 with three poles
The diode D4 that the emitter stage of pipe VT2 is connected, negative pole is connected with the drain electrode of FET MOS, positive pole after resistance R13 with
The polar capacitor C6 that the GND pin of process chip U is grounded after being connected, positive pole is connected with the VOUT pin processing chip U, bears
The polar capacitor C8 that pole is connected with the source electrode of FET MOS after resistance R14, P pole after resistance R15 with process chip U
LBO pin be connected, the diode D5 of the output as FET squelch circuit for the N pole, positive pole after resistance R17 with two
The N pole of pole pipe D5 is connected, the polar capacitor C7 of minus earth, and one end is connected with the drain electrode of FET MOS, another
End forms with the resistance R16 being connected of polar capacitor C7；The negative pole of described polar capacitor C8 is extremely connected with the P of diode D5
Connect.
5. a kind of signal band gain formula audio signal processing according to claim 4, it is characterised in that described place
Reason chip U is the integrated chip of IW1761.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620514069.0U CN205681612U (en) | 2016-05-28 | 2016-05-28 | A kind of signal band gain formula audio signal processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620514069.0U CN205681612U (en) | 2016-05-28 | 2016-05-28 | A kind of signal band gain formula audio signal processing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205681612U true CN205681612U (en) | 2016-11-09 |
Family
ID=57437733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620514069.0U Expired - Fee Related CN205681612U (en) | 2016-05-28 | 2016-05-28 | A kind of signal band gain formula audio signal processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205681612U (en) |
-
2016
- 2016-05-28 CN CN201620514069.0U patent/CN205681612U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161109 Termination date: 20170528 |