CN106030799B - 具有soi上横向集电极的hv互补双极型晶体管 - Google Patents

具有soi上横向集电极的hv互补双极型晶体管 Download PDF

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CN106030799B
CN106030799B CN201580010179.1A CN201580010179A CN106030799B CN 106030799 B CN106030799 B CN 106030799B CN 201580010179 A CN201580010179 A CN 201580010179A CN 106030799 B CN106030799 B CN 106030799B
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阿列克谢·萨多夫尼科夫
杰弗里·A·巴布科克
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Abstract

在绝缘体上硅SOI集成电路中的互补高电压双极型晶体管(100)的所描述实例中，集电极区域(104)形成在安置于掩埋绝缘体层BOX(103)上方的外延硅层中。基极区域(113)及发射极(108)安置于所述集电极区域(104)上方。通过穿过衬底的有源区域及BOX(103)将施主杂质植入p型衬底(101)而在所述BOX(103)下方形成n型区域(106)。稍后在工艺流程中，此n型区域(106)通过经掺杂的多晶硅插塞(110)从顶部连接且以Vcc被偏置。在此情况中，其将耗尽PNP集电极区域的横向部分且将增加其BV。

Description

具有SOI上横向集电极的HV互补双极型晶体管
技术领域
本发明涉及双极型晶体管制造，且更特定来说，本发明涉及根据绝缘体上硅(SOI)技术的具有普通衬底上的变化特性的晶体管的制造。
背景技术
集成电路已使用双极结型晶体管许多年，利用其高增益特性来满足高性能及高电流驱动需求。举例来说，双极型晶体管尤其适合于高频率应用，例如在无线通信中。
此外，绝缘体上硅(SOI)技术提供高频率电子装置的重要优点。如在SOI技术中为基本的，有源装置(例如晶体管)形成在形成于绝缘体层(例如通常被称作掩埋氧化物(BOX)的二氧化硅层)上方的单晶硅层中。掩埋氧化物层将有源装置与下伏衬底隔离，有效地消除到衬底的寄生非线性结电容且减少集电极到衬底电容。就块体晶体管的高频率性能受衬底电容限制来说，SOI技术提供显著改进。
此外，SOI装置在高电压应用中是稳健的。掩埋氧化物层有效地消除到衬底的结击穿的任何合理的可能性。
然而，从高偏置电压的观点来看，促进高频率性能的那些晶体管特征倾向于削弱装置，反之亦然。通常已通过单独制造高电压集成电路及高性能集成电路来解决此折衷，其中每一集成电路具有针对其特定实施而经优化的晶体管。这是因为源于将高电压装置及高性能装置两者集成在同一SOI集成电路中的工艺复杂性增添显著成本且施加制造良率压力。
常规SOI双极型晶体管经设计为高性能装置。然而，从击穿电压及性能两者的观点来看，高性能晶体管在某种程度上受其构造限制。集电极-发射极击穿电压(BVCEO)取决于集电极区域的厚度及集电极区域的掺杂浓度。集电极区域的较轻掺杂及较厚集电极区域将增大此击穿电压。
在真实电路中，PNP的发射极及基极大约在最高电势Vcc下被偏置(相对于接地衬底)，同时集电极在Vcc与0之间切换。高B-C偏置对应于在集电极处具有零电势。在此条件下，接地p型衬底未耗尽集电极区域的横向部分，且因此不能有助于增加BV。
NPN的发射极及基极大约在最低电势GND下被偏置(相对于接地衬底)，同时集电极在Vcc与0之间切换。高B-C偏置对应于在集电极处具有VCC电势。在此条件下，接地p型衬底耗尽集电极区域的横向部分，且因此有助于增加BV。
发明内容
需要一种在不降低集电极掺杂浓度或增加PNP的集电极区域厚度的情况下增加PNP BV同时在同一电路/衬底上包含高电压NPN的方法。
在所描述的实例中，一种集成电路结构包含NPN高电压晶体管及PNP高电压晶体管两者。所述集成电路结构包含互补PNP及NPN结构。所述PNP及NPN结构包含SOI半导体结构。所述SOI半导体结构包含：p型区域；有源PNP及NPN装置区域；及位于其间、接触并将所述p型区域与所述有源PNP及NPN区域电隔离的掩埋绝缘体层BOX。使用单晶硅实施p型区域以及有源装置PNP及NPN区域两者。n型区域包含于PNP晶体管的掩埋绝缘体层BOX的下方，这通过穿过SOI晶片的有源装置区域及BOX将施主杂质植入p型区域来进行。
在其它所描述的实例中，一种集成电路结构包含NPN高电压晶体管及PNP高电压晶体管两者。所述集成电路结构包含互补PNP及NPN结构。所述PNP及NPN结构包含SOI半导体结构。所述SOI半导体结构包含：n型区域；有源PNP及NPN装置区域；及位于其间、接触并将所述n型区域与所述有源PNP及NPN装置区域电隔离的掩埋绝缘体层BOX。使用单晶硅实施n型区域以及有源PNP及NPN装置区域两者。n型区域包含于PNP晶体管的掩埋绝缘体层BOX的下方，这通过穿过SOI晶片的有源装置区域及BOX将施主原子植入n型区域来进行。p型区域包含于NPN晶体管的掩埋绝缘体层BOX的下方，这通过穿过SOI晶片的有源装置区域及BOX将受主杂质植入n型区域来进行。
附图说明
图1是实例实施例的横截面图。
图1A说明详细描述NPN晶体管的图1的放大部分。
图1B说明详细描述PNP晶体管的图1的放大部分。
图2是另一实例实施例的横截面图。
图2A说明详细描述NPN晶体管的图2的放大部分。
图2B说明详细描述PNP晶体管的图2的放大部分。
图3是BVCER对不具有降低表面电场(resurf)的结构及包含降低表面电场的结构的经计算的相依性的图。
具体实施方式
在图1、1A及1B中所展示的实例中，互补PNP 100及NPN 200结构包含SOI半导体结构，其具有：p型区域101；相应有源装置区域104及204；及位于其间、接触并将p型区域101与有源装置区域104及204电隔离的掩埋绝缘体层(BOX)103。有源装置区域104及204的初始掺杂水平可为n型、～1e14 1/cm3。在此实例中，使用单晶硅实施p型区域101及有源装置区域104及204。为形成具有较高PNP BV的结构，将n型区域106包含于PNP晶体管100的掩埋绝缘体层(BOX)下方，这通过穿过SOI晶片的有源装置区域及BOX 103(总共1.5到2um)将具有约1e13到1e14 1/cm2的剂量的施主杂质植入p型区域101中来进行。稍后在此工艺流程中，此n型区域106及p型区域101通过经掺杂的多晶硅插塞从顶部连接且分别以Vcc及GND被偏置。因为衬底为p型材料，所以可将GND施加到p型区域101或顶部触点GND。在此情况中，其将耗尽PNP集电极区域及NPN集电极区域两者的横向部分且将增加其BV。
以下描述提供具有较高BV(图1B)的PNP晶体管100的结构。
首先，如所描述及图1、1A及1B中展示那样提供SOI晶片。
接下来，完成第一遮蔽及植入步骤以在PNP区域中的BOX 103下方形成经高度(～1e17 1/cm3)掺杂的n型层106。经高度掺杂的n型层106位于PNP区域的垂直下方且朝向n型多晶硅插塞110延伸且耦合到所述插塞。
在垫氧化之后氮化物沉积之前执行第二遮蔽及植入步骤以形成有源装置区域104中的3e14到3e16之间的均匀集电极掺杂。
完成第三遮蔽及蚀刻步骤以提供硬掩模用于在有源装置区域104中界定绝缘体层STI 105且用于在有源装置区域104中沉积绝缘体层STI 105。
形成深沟槽109以围绕PNP晶体管100及n型多晶硅插塞110。所述沟槽从裸片的顶部延伸到BOX 103的底部，且n型多晶硅插塞从裸片的顶部延伸到BOX 103且穿过BOX 103延伸到BOX 103下方的经高度掺杂的n型层106中。n型多晶硅插塞接触BOX 103下方的经植入的n型层且延伸到裸片的顶部从而提供到经植入的n型层的顶部触点。
在外延层112之内沉积基极外延半导体层113，在有源装置区域104的顶部上界定且使用具有相反导电类型的杂质掺杂基极外延半导体层113，其中基极触点111耦合到基极外延半导体层113。
且最后，发射极区域108覆盖基极外延半导体层113的一部分。发射极区域108使用与有源装置区域104相同的导电类型高度掺杂。
以下描述提供具有图1A中的高BV的NPN晶体管200的结构。
首先，如所描述及在图1、1A及1B中展示那样提供SOI晶片。
在垫氧化之后氮化物沉积之前执行第一遮蔽及植入步骤以形成有源装置区域204中的介于3e14到3e16/cm3之间的均匀集电极掺杂。
完成第二遮蔽及蚀刻步骤以提供硬掩模用于在有源装置区域204中界定绝缘体层STI 105且用于在有源装置区域204中沉积绝缘体层STI 105。
深沟槽109经形成以围绕NPN晶体管200及p型多晶硅插塞210。沟槽从裸片的顶部延伸到BOX 103的底部，且p型多晶硅插塞从裸片的顶部延伸到BOX 103且穿过BOX 103延伸到BOX 103下方的p型层101中。p型多晶硅插塞接触BOX 103下方的p型层且延伸到裸片的顶部从而提供到p型层101的顶部触点。
在有源装置区域204的顶部上沉积、界定且使用具有相反导电类型的杂质掺杂基极外延半导体层213，其中基极触点211耦合到基极外延半导体层213。
且最后，发射极区域208覆盖基极外延半导体层213的一部分。发射极区域208使用与第一外延层204相同的导电类型高度掺杂。
用于NPN及PNP的基极外延半导体可为SiGe或硅。也可在两个操作中沉积基极外延半导体，一者用于NPN且一者用于PNP。
在图2、2A及2B中所展示的另一实例中，互补PNP 300及NPN 400结构包含SOI半导体结构，其具有：n型区域301；相应有源装置区域104及204；及位于其间、接触并将n型区域301与有源装置区域104及204电隔离的掩埋绝缘体层(BOX)103。有源装置区域104及204的初始掺杂水平可为n型、～1e14 1/cm3。在此实例中，使用单晶硅实施n型区域301及有源装置区域104及204。为形成具有较高PNP BV的结构，n型区域106包含于PNP 300晶体管的掩埋绝缘体层(BOX)103下方，这通过穿过SOI晶片的有源装置区域及BOX 103(总共1.5到2um)将约2e15到1e17的施主杂质植入n型区域301中来进行。此外，产生较高NPN 400BV的结构包含位于NPN晶体管的掩埋绝缘体层(BOX)103下方的p型区域406，这通过穿过SOI晶片的有源装置区域204及BOX 103(总共1.5到2um)将约2e15到1e17的受主杂质植入n型区域301中来进行。稍后在此工艺流程中，n型区域106及p型区域406通过经掺杂的多晶硅插塞从顶部连接且分别在Vcc及GND处偏置。因为衬底为n型材料，所以可将Vcc施加到n型区域301或顶部触点Vcc。在此情况中，其将耗尽PNP集电极区域及NPN集电极区域两者的横向部分且将增加其BV。
以下描述提供具有图2B中的较高BV的NPN晶体管300的结构。
首先，如所描述及在图2、2A及2B中展示那样提供SOI晶片。
接下来，完成第一遮蔽及植入步骤以在PNP区域中的BOX 103下方形成经高度(～1e17 1/cm3)掺杂的n型层106。经高度掺杂的n型层106位于PNP区域的垂直下方且延伸朝向n型多晶硅插塞110且耦合到所述插塞。
在垫氧化之后氮化物沉积之前执行第二新遮蔽及植入步骤以形成有源装置区域104中的3e14到3e16之间的均匀集电极掺杂。
完成第三遮蔽及蚀刻步骤以提供硬掩模用于在有源装置区域104中界定浅沟槽绝缘层STI 105且用于在有源装置区域104中沉积浅沟槽绝缘层STI 105。
深沟槽109经形成以围绕PNP晶体管300及n型多晶硅插塞110。沟槽从裸片的顶部延伸到BOX 103的底部，且n型多晶硅插塞110从裸片的顶部延伸到BOX 103且穿过BOX 103延伸到BOX 103下方的经高度掺杂的n型层106中。n型多晶硅插塞110接触BOX 103下方的经植入的n型层且延伸到裸片的顶部从而提供到经植入的n型层106的顶部触点。
在有源装置区域104的顶部上沉积、界定及且使用具有相反导电类型的杂质掺杂基极外延半导体层113，其中基极触点111耦合到基极外延半导体层113。
且最后，发射极区域108覆盖基极外延半导体层113的一部分。发射极区域108使用与第一外延层104相同的导电类型高度掺杂。
以下描述提供具有图1B中的高BV的NPN晶体管400的结构。
首先，如所描述及在图2、2A及2B中展示那样提供SOI晶片。
接下来，完成第一遮蔽及植入步骤以在NPN区域中的BOX 103下方形成经高度(～1e17 1/cm3)掺杂的p型层406。经高度掺杂的p型层406位于NPN区域的垂直下方且延伸朝向p型多晶硅插塞210且耦合到所述插塞。
在垫氧化之后氮化物沉积之前执行第二新遮蔽及植入步骤以形成有源装置区域204中的3e14到3e16 1/cm3之间的均匀集电极掺杂。
完成第三遮蔽及蚀刻步骤以提供硬掩模用于在有源装置区域204中界定绝缘体层STI 105且用于在有源装置区域204中沉积绝缘体层STI 105。
深沟槽109经形成以围绕NPN晶体管400及p型多晶硅插塞210。沟槽从裸片的顶部延伸到BOX 103的底部，且p型多晶硅插塞210从裸片的顶部延伸到BOX 103且穿过BOX 103延伸到BOX 103下方的经高度掺杂的p型层406中。p型多晶硅插塞210接触BOX 103下方的经植入的p型层406且延伸到裸片的顶部从而提供到经植入的p型层406的顶部触点。
在有源装置区域204的顶部上沉积、界定且使用具有相反导电类型的杂质掺杂基极外延半导体层213，其中基极触点211耦合到基极外延半导体层213。
且最后，发射极区域208覆盖基极外延半导体层213的一部分。发射极区域108使用与第一外延层204相同的导电类型高度掺杂。
用于NPN及PNP的基极外延半导体可为SiGe或硅。也可在两个操作中沉积基极外延半导体，一者用于NPN且一者用于PNP。
图3展示BVCER fT对降低表面电场n型层的相依性。针对具有横向集电极的PNP在具有降低表面电场N型层的情况下(菱形)及不具有降低表面电场N型层的情况下(三角形)计算BVCER的相依性(实线)及在VCE＝10V下的fTpeak(虚线)。在不具有N型区域的情况下，PNPBV在～38V下饱和。通过比较，在具有N区域的情况下，PNP BV在100V以上饱和。
在所描述的实例中修改是可能的，且在权利要求书范围内的其它实施例是可能的。

Claims (7)

1.一种集成电路，其包括：
PNP结构，其包含第一p型层、位于所述第一p型层之下的n型层以及位于所述n型层之下的第二p型层；
绝缘体层，其位于所述第二p型层之下；
n型掩埋区域，其位于所述PNP结构以及所述绝缘体层之下；以及
导电插塞，其从与所述第二p型层对准的表面延伸以达到所述n型掩埋区域。
2.根据权利要求1所述的集成电路，其中所述导电插塞包含n型多晶硅插塞。
3.根据权利要求1所述的集成电路，其进一步包括：
NPN结构，其具有第一n型层、位于所述第一n型层之下的p型层以及位于所述p型层之下的第二n型层；
深沟槽结构，其从所述表面延伸到所述绝缘体层并将所述NPN结构与所述PNP结构分隔开。
4.根据权利要求3所述的集成电路，其中所述n型掩埋区域被终止而不延伸于所述NPN结构之下。
5.根据权利要求1所述的集成电路，其进一步包括：
深沟槽结构，其从所述表面延伸到所述绝缘体层并侧向地围绕所述PNP结构的所述第二p型层。
6.根据权利要求1所述的集成电路，其进一步包括：
第二导电插塞，其从所述表面延伸到位于所述n型掩埋层之下的p型衬底，所述第二导电插塞经配置以将接地电压转移到所述p型衬底。
7.根据权利要求6所述的集成电路，其中所述第二导电插塞包含p型多晶硅插塞。
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