CN106024864A - P沟碳化硅静电感应晶闸管及其制造方法 - Google Patents
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Abstract
本发明公开了一种P沟碳化硅静电感应晶闸管及其制造方法,目的在于,降低器件开态电阻、提升功率特性,所采用的技术方案为:包括自下而上依次设置的第二N型欧姆接触电极、N型SiC衬底、P型SiC缓冲层、P型SiC漂移层和P型SiC电流增强层,P型SiC电流增强层上刻蚀形成有若干个台阶,相邻台阶之间设有沟槽,台阶顶部设置有P型SiC欧姆接触层,P型SiC欧姆接触层上部设置有P型欧姆接触电极,P型欧姆接触电极的形状与P型SiC欧姆接触层相同,沟槽内设置有N型SiC欧姆接触区,N型SiC欧姆接触区与台阶侧面、沟槽底部和P型SiC欧姆接触层均接触,位于沟槽底部的N型SiC欧姆接触区的上部设置有第一N型欧姆接触电极,P型欧姆接触电极、第一N型欧姆接触电极和第二N型欧姆接触电极均包括依次沉积的Ni层和Pt层。
Description
技术领域
本发明涉及半导体器件以及半导体工艺技术领域,具体涉及一种P沟碳化硅静电感应晶闸管及其制造方法。
背景技术
随着科学技术的迅猛发展,对功率半导体器件的性能提出了越来越高的要求。目前使用的功率器件主要由硅等传统半导体材料制成,由于受材料性能的限制,器件的电学性能已经难以持续的大幅提高;而且用这些材料制成的器件不能在高温强辐射等恶劣环境下长期工作,特别是在新能源、汽车电子、航空航天等领域中,传统的硅功率器件已经逐渐难以胜任。
在众多新型半导体材料中,碳化硅(SiC)材料以其良好的物理和电学性能成为制造新一代半导体功率器件和电路的首选材料。尤其是高温、高压和高频电力电子应用领域,SiC功率器件更具有硅功率器件难以比拟的优势和潜力。
近年来,SiC器件的商用化有了很大的进展,包括Cree、英飞凌、罗姆等多家公司可以提供包括SiC SBD、JFET、MOSFET商用产品,但是SiC功率器件的广泛应用还面临着很多的挑战。特别是SiC全控型功率器件的发展相对较慢,目前市场上只有少数国外公司可以提供种类比较单一的SiC全控型功率器件,而且价格高昂,难以广泛应用于民用领域。
在众多的SiC功率器件类型中,SiC JFET是电压控制的单极型器件,具有单步制备工艺相对成熟且不存在MOS界面层质量问题等优点,一直是中等额度电压SiC功率器件的研究热点,并成为了首款商用的SiC全控型功率器件,但至今未能广泛推广。其中最大的问题是SiCJFET的正、反向特性都同时敏感的依赖于沟道区域的结构和工艺参数,这给高功率常关型SiCJFET的结构设计和工艺研制带来了困难,提高了器件制备成本,影响了器件的应用。
为了解决常关型SiC JFET折中开态电阻和关态特性困难的问题,引入电导调制效应是比较理想的选择,常见的方案有两种:一是将SiC JFET工作于双极模式下(BJFET/BMFET),让栅源PN结正偏向沟道内注入的少数载流子以调制开态电阻;二是采用类似于SITH(静电感应晶闸管)的结构,在漏极引入一个PN结。
其中第一种方案虽然不增加工艺难度,但需要栅极由电压驱动转变为电流驱动,不仅会增大驱动功率、增加驱动电路复杂度;同时由于栅极注入只能调制沟道低掺杂区的电导率,所以该方案的应用价值有限。
而静电感应晶闸管可以看出JFET与PIN的串联,即具有SiC JFET工艺成熟、易驱动的优点,又具有更强烈的电导调制效应。与BJFET相比,SITH漏端PN结注入的少子可以有效的调制整个漂移区的电导率,有效降低器件的开态电阻。
发明内容
为了解决现有技术中的问题,本发明提出一种有利于降低器件开态电阻、提升功率特性的P沟碳化硅静电感应晶闸管及其制造方法。
为了实现以上目的,本发明所采用的技术方案为:
一种P沟碳化硅静电感应晶闸管,包括自下而上依次设置的第二N型欧姆接触电极、N型SiC衬底、P型SiC缓冲层、P型SiC漂移层和P型SiC电流增强层,所述P型SiC电流增强层上刻蚀形成有若干个台阶,相邻台阶之间设有沟槽,所述台阶顶部设置有P型SiC欧姆接触层,P型SiC欧姆接触层上部设置有P型欧姆接触电极,P型欧姆接触电极的形状与P型SiC欧姆接触层相同,所述沟槽内设置有N型SiC欧姆接触区,N型SiC欧姆接触区与台阶侧面、沟槽底部和P型SiC欧姆接触层均接触,位于沟槽底部的N型SiC欧姆接触区的上部设置有第一N型欧姆接触电极,所述P型欧姆接触电极、第一N型欧姆接触电极和第二N型欧姆接触电极均包括依次沉积的Ni层和Pt层。
所述N型SiC衬底的掺杂浓度为1×1018~1×1019cm-3。
所述P型SiC缓冲层的厚度为0.5~2.0μm,掺杂浓度为1×1016~5×1017cm-3。
所述P型SiC漂移层的厚度为材料中空穴扩散长度的0.4~0.9倍,掺杂浓度Ndrift为1×1014~8×1015cm-3。
所述P型电流增强层的掺杂浓度NCSL为1×1016~1×1017cm-3,沟槽底部的P型电流增强层的厚度为0.5~2μm。
所述台阶高度为1.5~3.5μm,台阶宽度为的1.0~2.0倍。
所述P型欧姆接触层的掺杂浓度为1×1018~1×1019cm-3,厚度为0.2~0.5μm。
一种P沟碳化硅静电感应晶闸管的制备方法,包括以下步骤:
步骤一、由SiC基片构成N型SiC衬底;
步骤二、采用化学气相沉积法在N型SiC衬底的上表面上依次外延生长P型SiC缓冲层、P型SiC漂移层、P型SiC电流增强层和P型SiC欧姆接触层;
步骤三、通过SF6气体,采用反应离子干法刻蚀法在P型SiC电流增强层和P型SiC欧姆接触层上刻蚀出若干个台阶,相邻台阶之间设沟槽;
步骤四、采用离子注入法在P型SiC电流增强层的台阶侧面和沟槽底部形成N型SiC欧姆接触区,并在惰性气体气氛下进行温度为1650℃~1700℃的热退火;
步骤五、在P型SiC欧姆接触层上部、N型SiC衬底下方以及沟槽底部的N型SiC欧姆接触区上部依次淀积Ni层和Pt层,并在N2气氛下进行温度为950℃~1050℃的热退火,在P型SiC欧姆接触层的上部形成P型欧姆接触电极;在沟槽底部的N型SiC欧姆接触区上部形成第一N型欧姆接触电极;在N型SiC衬底下部形成N型欧姆接触电极,即得到P沟碳化硅静电感应晶闸管。
所述P型SiC欧姆接触层上部淀积的Ni层厚度为200nm~400nm,Pt层厚度为50nm~200nm;在N型SiC衬底下部淀积的Ni层厚度为200nm~400nm,Pt层的厚度为50nm~200nm;沟槽底部的N型SiC欧姆接触区上部淀积的Ni层厚度为200nm~400nm,Pt层的厚度为50nm~200nm。
与现有技术相比,本发明采用N型SiC衬底,通过与P型SiC漂移层形成PN结提供少子注入以获得电导调制效应,并在N型SiC衬底与P型SiC漂移层之间设置P型SiC缓冲层以避免穿通,在P型SiC漂移层与P型SiC欧姆接触层之间设置P型SiC电流增强层以降低沟道区的阻抗。对于常规结构的SiC JFET,器件的开态电阻和击穿电压都敏感依赖于沟道区的材料参数,难以折中。尤其是对于常关型器件,很难同时获得低开态电阻和高击穿电压。本发明的P沟碳化硅静电感应晶闸管通过采用N型SiC衬底,形成的少子注入调制低掺杂的P型SiC漂移层,通过对结构参数的优化设计让电导调制效应可以覆盖整个漂移区,即少子扩散长度大于漂移区厚度,即可显著削弱漂移区掺杂对开态电阻的影响。对于这种类型的器件,理论上有N沟,即采用N型的沟道和漂移层和P沟,即P型的沟道和漂移层两种技术方案,即分别采用采用空穴和电子作为衬底注入的少子以调制沟道区的电导率。一般情况下电子的扩散长度要比空穴的扩散长度长,比如SiC中电子的少子扩散长度Ln为10~25μm,而空穴的扩散长度Lp为5~12μm。因此,采用P型沟道可以获得更强的电导调制效应,从而可以进一步降低漂移区厚度和掺杂浓度,从而获得高击穿电压。本发明提出的结构能够有效解决传统SiC JFET存在的问题,同时获得低开态电阻和高击穿电压,提高设计灵活度,降低工艺难度,新颖合理,实用性强。
进一步,为了获得高的击穿电压,需要降低漂移区掺杂浓度和增加漂移区的厚度,但这都会显著增大开态电阻。由于漂移层的厚度由电导调制效应决定,且开态电阻不再受漂移区掺杂浓度的影响,本发明通过采用低掺杂的漂移区以获得高击穿电压。采用本方案的设计后,开态电阻和击穿电压分别由两个参数决定,大大增加了设计灵活度。
进一步,器件关态时,栅耗尽区很容易延伸到衬底,即发生穿通,这会导致器件的击穿特性变差。本发明在N型衬底和P型漂移层之间设置P型缓冲层,以避免穿通的发生,有利于提升击穿电压。
进一步,由于采用了低掺杂的漂移层,沟道区的阻抗会显著上升,本发明在P型漂移层与欧姆接触层之间设置P型电流增强层以降低沟道区的阻抗,从而降低漂移层低掺杂对开态电阻的影响,提升器件性能,提高设计的灵活度。
进一步,采用了本发明的结构后,设计和研制开态电阻低的常关型器件更为容易,设计方法是沟道宽度(即台阶宽度去掉掺杂深度)小于等于2倍栅耗尽层厚度,根据器件物理的知识,耗尽层厚度为其中VD为自建电势,对于SiC材料和本结构的特点,约等于
本发明的制备方法制备的P沟碳化硅静电感应晶闸管能够有效的降低器件开态电阻,提升功率特性,工艺方法难度较低,设计合理,实用性高。
附图说明
图1为本发明的结构示意图;
图2为本发明制造方法的流程图;
图3a为本发明制造方法步骤一完成后的器件结构示意图,图3b为步骤二完成后的器件结构示意图,图3c为步骤三完成后的器件结构示意图,图3d为步骤四完成后的器件结构示意图;
其中,1-N型SiC衬底;2-P型SiC缓冲层;3-P型SiC漂移层;4-P型SiC电流增强层;5-P型SiC欧姆接触层;6-N型欧姆接触区;7-P型欧姆接触电极;8-第一N型欧姆接触电极;9-第二N型欧姆接触电极。
具体实施方式
下面结合具体的实施例和说明书附图对本发明作进一步的解释说明。
参见图1,本发明结构包括由N型SiC衬底1和设置在N型SiC衬底1上部的P型SiC缓冲层2,P型SiC缓冲层2上设置P型SiC漂移层3,P型SiC漂移层3上设置P型SiC电流增强层4,P型SiC电流增强层4上设置P型SiC欧姆接触层5,P型电流增强层4和P型SiC欧姆接触层5上刻蚀形成有多个台阶,相邻台阶之间设有沟槽,在台阶侧面和沟槽底部设置有N型SiC欧姆接触区6,P型SiC欧姆接触层5上部设置有形状与P型SiC欧姆接触层5形状相同的P型欧姆接触电极7,台阶底部的N型SiC欧姆接触区6上部设置有N型欧姆接触电极8;N型SiC衬底1下部设置有N型欧姆接触电极9。
N型SiC衬底1掺杂浓度为1×1018~1×1019cm-3;P型SiC缓冲层2的厚度为0.5~2.0μm,掺杂浓度为1×1016~5×1017cm-3;P型SiC漂移层3的厚度为材料中空穴扩散长度的0.4~0.9倍,掺杂浓度Ndrift为1×1014~8×1015cm-3;台阶高度1.5~3.5μm,台阶宽度为的1.0~2.0倍;P型电流增强层4的掺杂浓度NCSL为1×1016~1×1017cm-3,其下边界延伸到沟槽底部下方0.5~2μm,即位于沟槽底部的P型电流增强层4的厚度为0.5~2μm;P型欧姆接触层5掺杂浓度1×1018~1×1019cm-3,厚度0.2~0.5μm。
参见图2,本发明的制造方法,包括以下步骤:
步骤一、提供由SiC基片构成的N型SiC衬底1;
步骤二、采用化学气相沉积法在N型SiC衬底1的上表面上依次外延生长厚度为0.5~2.0μm,掺杂浓度为1×1016~5×1017cm-3的P型SiC缓冲层2;厚度为材料中空穴扩散长度的0.4~0.9倍,掺杂浓度Ndrift为1×1014~8×1015cm-3的P型SiC漂移层3;掺杂浓度NCSL为1×1016~1×1017cm-3,其下边界延伸到沟槽底部下方0.5~2μm的P型SiC电流增强层4;掺杂浓度1×1018~1×1019cm-3,厚度0.2~0.5μm的P型SiC欧姆接触层5;
步骤三、通过SF6气体,采用反应离子干法刻蚀法在P型SiC电流增强层4和P型SiC欧姆接触层5上刻蚀出高度1.5~3.5μm,宽度为的1.0~2.0倍,间距为2~5μm的若干个台阶,相邻台阶之间设沟槽;
步骤四、采用离子注入法在P型SiC电流增强4的台阶侧面和沟槽底部形成掺杂浓度为1×1018~5×1018cm-3的N型SiC欧姆接触区6,并在惰性气体气氛下进行温度为1650℃~1700℃的热退火;
步骤五、在P型SiC欧姆接触层5上方依次淀积Ni层和Pt层,Ni层的厚度为200nm~400nm,Pt层的厚度为50nm~200nm;
步骤六、在N型SiC衬底1下方依次淀积Ni层和Pt层,Ni层的厚度为200nm~400nm,Pt层的厚度为50nm~200nm;
步骤七、在沟槽底部的N型SiC欧姆接触区6上方依次淀积Ni层和Pt层,Ni层的厚度为200nm~400nm,Pt层的厚度为50nm~200nm;
步骤八、在N2气氛下进行温度为950℃~1050℃的热退火,在P型SiC欧姆接触层5的上部形成由Ni层和Pt层构成的P型欧姆接触电极7;在沟槽底部的上部形成由Ni层和Pt层构成的N型欧姆接触电极8;在N型SiC衬底1下方形成由Ni层和Pt层构成的N型欧姆接触电极9,即得到P沟碳化硅静电感应晶闸管。
静电感应晶闸管,是一种典型的复合型功率半导体器件,从技术上可以理解为单极型器件(静电感应晶体管,SIT)加上了少子调制效应。从材料角度,其性能由单极型器件的体材料和少子的性能决定。对于N沟型器件,是N型体材料(电子导电)和P型少子(空穴);对于P沟器件,是P型体材料(空穴导电)和N型少子(电子)。
对于大部分半导体材料,N型材料的性能(包括体材料和少子性能)都优于P型材料,因此,类似静电感应晶闸管这样的复合型器件,难以同时获得高的体材料和少子性能,即只能采用N型体材料加P型少子(N沟)或者P型体材料加N型少子(P沟)。
对于半导体材料,N型和P型体材料和少子特性,在数值上往往差了两三倍甚至更多,而工艺上也有很大的差别。以SiC材料为例,N型和P型材料的掺杂元素、杂质激活温度、杂质激活率、杂质离化率、迁移率、扩散系数、少子寿命等,以及研制欧姆接触所采用的金属类型、退火温度,研制肖特基接触的工艺参数,以及最后的工艺效果等,都有较大的差别。N沟和P沟SiC器件不仅仅是掺杂类型的转换,而且是在器件特性和设计方法上有较大的区别。
参照目前研究较多的另外一款SiC复合型功率半导体器件——SiC IGBT,与本专利涉及的理论思想类似,也是单极型器件(MOSFET)加上少子调制效应,目前学术界对于其N沟和P沟的研究都较为重视,研究发现这两种器件的特性各有优劣。同时开展这两种类型器件的研究将有助于这一类器件更快更好的发展。本发明提出的结构和工艺方案,可以有效解决传统SiCJFET存在的问题,同时获得低开态电阻和高击穿电压,提高设计灵活度,降低工艺难度,新颖合理,实用性强。
Claims (9)
1.一种P沟碳化硅静电感应晶闸管,其特征在于,包括自下而上依次设置的第二N型欧姆接触电极(9)、N型SiC衬底(1)、P型SiC缓冲层(2)、P型SiC漂移层(3)和P型SiC电流增强层(4),所述P型SiC电流增强层(4)上刻蚀形成有若干个台阶,相邻台阶之间设有沟槽,所述台阶顶部设置有P型SiC欧姆接触层(5),P型SiC欧姆接触层(5)上部设置有P型欧姆接触电极(7),P型欧姆接触电极(7)的形状与P型SiC欧姆接触层(5)相同,所述沟槽内设置有N型SiC欧姆接触区(6),N型SiC欧姆接触区(6)与台阶侧面、沟槽底部和P型SiC欧姆接触层(5)均接触,位于沟槽底部的N型SiC欧姆接触区(6)的上部设置有第一N型欧姆接触电极(8),所述P型欧姆接触电极(7)、第一N型欧姆接触电极(8)和第二N型欧姆接触电极(9)均包括依次沉积的Ni层和Pt层。
2.根据权利要求1所述的一种P沟碳化硅静电感应晶闸管,其特征在于,所述N型SiC衬底(1)的掺杂浓度为1×1018~1×1019cm-3。
3.根据权利要求1所述的一种P沟碳化硅静电感应晶闸管,其特征在于,所述P型SiC缓冲层(2)的厚度为0.5~2.0μm,掺杂浓度为1×1016~5×1017cm-3。
4.根据权利要求1所述的一种P沟碳化硅静电感应晶闸管,其特征在于,所述P型SiC漂移层(3)的厚度为材料中空穴扩散长度的0.4~0.9倍,掺杂浓度Ndrift为1×1014~8×1015cm-3。
5.根据权利要求1所述的一种P沟碳化硅静电感应晶闸管,其特征在于,所述P型电流增强层(4)的掺杂浓度NCSL为1×1016~1×1017cm-3,沟槽底部的P型电流增强层(4)的厚度为0.5~2μm。
6.根据权利要求5所述的一种P沟碳化硅静电感应晶闸管,其特征在于,所述台阶高度为1.5~3.5μm,台阶宽度为的1.0~2.0倍。
7.根据权利要求1所述的一种P沟碳化硅静电感应晶闸管,其特征在于,所述P型欧姆接触层(5)的掺杂浓度为1×1018~1×1019cm-3,厚度为0.2~0.5μm。
8.一种P沟碳化硅静电感应晶闸管的制备方法,其特征在于,包括以下步骤:
步骤一、由SiC基片构成N型SiC衬底(1);
步骤二、采用化学气相沉积法在N型SiC衬底(1)的上表面上依次外延生长P型SiC缓冲层(2)、P型SiC漂移层(3)、P型SiC电流增强层(4)和P型SiC欧姆接触层(5);
步骤三、通过SF6气体,采用反应离子干法刻蚀法在P型SiC电流增强层(4)和P型SiC欧姆接触层(5)上刻蚀出若干个台阶,相邻台阶之间设沟槽;
步骤四、采用离子注入法在P型SiC电流增强层(4)的台阶侧面和沟槽底部形成N型SiC欧姆接触区(6),并在惰性气体气氛下进行温度为1650℃~1700℃的热退火;
步骤五、在P型SiC欧姆接触层(5)上部、N型SiC衬底(1)下方以及沟槽底部的N型SiC欧姆接触区(6)上部依次淀积Ni层和Pt层,并在N2气氛下进行温度为950℃~1050℃的热退火,在P型SiC欧姆接触层(5)的上部形成P型欧姆接触电极(7);在沟槽底部的N型SiC欧姆接触区(6)上部形成第一N型欧姆接触电极(8);在N型SiC衬底(1)下部形成N型欧姆接触电极(9),即得到P沟碳化硅静电感应晶闸管。
9.根据权利要求8所述的一种P沟碳化硅静电感应晶闸管的制备方法,其特征在于,所述P型SiC欧姆接触层(5)上部淀积的Ni层厚度为200nm~400nm,Pt层厚度为50nm~200nm;在N型SiC衬底(1)下部淀积的Ni层厚度为200nm~400nm,Pt层的厚度为50nm~200nm;沟槽底部的N型SiC欧姆接触区(6)上部淀积的Ni层厚度为200nm~400nm,Pt层的厚度为50nm~200nm。
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