CN106024722B - 具有使用导电片段的集成输出电感器的半导体封装体 - Google Patents

具有使用导电片段的集成输出电感器的半导体封装体 Download PDF

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CN106024722B
CN106024722B CN201610146762.1A CN201610146762A CN106024722B CN 106024722 B CN106024722 B CN 106024722B CN 201610146762 A CN201610146762 A CN 201610146762A CN 106024722 B CN106024722 B CN 106024722B
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transistor
semiconductor package
output inductor
conductive segment
integrated output
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CN106024722A (zh
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曹应山
D·加利波
D·克拉韦特
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Infineon Technologies North America Corp
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Infineon Technologies North America Corp
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Abstract

提供了具有使用导电片段的集成输出电感器的半导体封装体。一种半导体封装体，包括：具有控制晶体管和同步晶体管的半导体裸片、具有在芯周围的绕组并且耦合至半导体裸片的集成输出电感器，其中绕组包括被连接到多个底部导电片段的多个顶部导电片段。控制晶体管和同步晶体管被配置作为半桥。该集成输出电感器被耦合至半桥的切换节点。多个顶部导电片段和多个底部导电片段中的至少一项包括部分刻蚀部分和非刻蚀部分。半导体裸片通过裸片贴装材料被附接到集成输出电感器。半导体裸片和集成输出电感器被封装在模制化合物中。

Description

具有使用导电片段的集成输出电感器的半导体封装体
背景技术
本申请要求于2015年3月25日提交的序列号为62/137,967，标题为“Dual GaugeLeadframe with Embedded Inductor”的临时专利申请的权益和优先权。在此通过引用将该临时申请中的公开内容完全并入本申请中。
诸如电压调节器(voltage regulator)之类的功率转换器被用在各种电子电路和系统中。例如，集成电路(IC)应用可以需要将直流电流(DC)输入转换成较低或较高的DC输出。作为示例，降压转换器可以被实现为用以将较高的电压DC输入转换成较低的电压DC输出以供在低压应用中使用的电压调节器。用于功率转换器的半导体封装解决方案可以被配置为容纳功率晶体管和输出电感器。
在传统的半导体封装体中，在功率转换器中使用的输出电感器与功率转换器中的诸如功率晶体管之类的部件并排放置。输出电感器与其他部件的侧向放置增大了半导体封装体的总体尺寸。另外，在传统的半导体封装体中，输出电感器为具有相对大的外形规格和不良热性能的预成型(pre-formed)电感器。将预成型电感器与功率晶体管集成可能进一步增大半导体封装体的总体尺寸并且劣化热性能。
因此，有需要通过提供有着减小的外形规格和加强的热耗散的、具有集成输出电感器的半导体封装体来克服现有技术中的缺点和缺陷。
发明内容
本公开针对集成输出电感器的半导体器件，其基本上关于在附图中的至少一个中被示出和/或描述并且在权利要求书中阐述。
附图说明
图1图示了根据本公开的一个实现方式的适于用作功率转换器的示例性电路的示图。
图2图示了根据本公开的一个实现方式的集成输出电感器的顶视图。
图3A图示了根据本公开的一个实现方式的具有集成输出电感器的半导体封装体的顶视图。
图3B图示了根据本公开的一个实现方式的具有集成输出电感器的半导体封装体的截面图。
图3C图示了根据本公开的一个实现方式的具有集成输出电感器的半导体封装体的截面图。
具体实施方式
以下描述包含有关本公开的实现方式的具体信息。本申请中的附图及其所附的具体描述仅针对示例性实现方式。除非另外指明，附图中类似或对应的元件可以用类似或对应的数字来指示。此外，本申请中的附图和图示一般不是按比例的，并且不旨在于对应于实际的相对尺寸。
参照图1，图1图示了根据本公开的一个实现方式的适于用作功率转换器的示例性电路的示图。功率转换器电路100包括功率转换器封装体102和输出电容器160。功率转换器封装体102包括功率级110和输出电感器158。如图1所示，功率级110包括在切换节点156(Q1)处被耦合至低侧或同步晶体管154(Q2)的高侧或控制晶体管152(Q1)，以及被耦合至控制晶体管152和同步晶体管154的脉宽调制(PWM)控制和驱动器150。注意PWM控制和驱动器150可以被实现为PWM和控制驱动器IC，并且被配置为向控制晶体管152和同步晶体管154的相应栅极提供驱动信号。如图1中进一步示出的，功率转换器电路100被配置为接收输入电压VIN，并且在输出节点162处提供经转换的电压(例如，经整流和/或经降压的(steppeddown)电压)作为VOUT。
在本实现方式中，功率级110的控制晶体管152和同步晶体管154可以采取例如被配置作为半桥的金属氧化物半导体场效应晶体管(MOSFET)的形式。也就是说，控制晶体管152可以在切换节点156处被耦合至同步晶体管154，并且转而可以通过输出电感器158被耦合至输出节点162。在一些实现方式中，控制晶体管152和同步晶体管154可以被实现为基于IV族的功率晶体管，诸如具有例如垂直或侧向设计的硅功率MOSFET。在其他实现方式中，控制晶体管152和同步晶体管154例如可以被实现为场效应晶体管(FET)、绝缘栅极双极性晶体管(IGBT)、或高电子迁移率晶体管(HEMT)。一般而言，控制晶体管152和同步晶体管154可以被实现为诸如硅功率晶体管之类的IV族功率晶体管，或者诸如氮化镓(GaN)功率晶体管之类的III-V族功率晶体管。在一些实现方式中，有利或可取的是使控制晶体管152和同步晶体管154中的至少一个被实现为例如诸如GaN功率晶体管之类的III-V族功率晶体管。功率转换器电路100可以有利地在各种汽车、工业、家电和照明应用中被用作例如降压转换器。
注意为了说明书的简单和简明起见，本具备创造性的原理将在一些实例中通过参考包括一个或多个基于硅的功率FET的降压转换器的具体实现方式来描述。然而，要强调的是这样的实现方式仅是示例性的，并且这里所公开的具备创造性的原理宽泛地适用于广泛的应用，包括使用其他基于IV族材料或者基于III-V族半导体来实现的功率晶体管的降压和升压转换器。
还注意，如这里所使用的用语“III-V族”指的是包括至少一种III族元素和至少一种IV族元素的化合物半导体。作为示例，III-V族半导体可以采取包括氮和至少一种III族元素的III-氮半导体的形式。例如，III-氮功率晶体管可以使用氮化镓(GaN)来制作，其中一种或多种III族元素包括少量或大量的镓，但是也可以除了镓之外还包括其他III族元素。
参照本申请的附图应当注意到本公开的实现方式关于在功率半导体封装体内的输出电感器和功率级进行描述，诸如在图3A、3B和3C的功率半导体封装体302内的半导体裸片310和集成输出电感器358。图3A、3B和3C中的每个半导体裸片310可以对应于图1的功率级110并且每个集成输出电感器358可以对应于图1的输出电感器158。在一些实现方式中，与功率级110对应的半导体裸片310和与输出电感器158对应的输出电感器358可以按图1的功率转换器电路100中所示的方式彼此电耦合。
随着电子设备和系统朝着甚至更小的外形规格发展，容纳输出电感器(诸如图1中的输出电感器158)所仍需的大的电路板面积变得更加昂贵。因而，本申请公开了一种利用堆叠架构的封装解决方案，该堆叠架构使得能够制作包括集成输出电感器的功率半导体封装体却需要基本上不比仅仅包封功率晶体管和驱动器电路装置的封装体更大的面积。此外，根据本公开的实现方式，利用具有非刻蚀部分和部分刻蚀部分的导电片段(clip)来形成连续的线绕组(wire winding)并且在通过导电片段的部分刻蚀部分形成的内部空间内嵌入芯(core)，由此进一步减小封装高度或厚度。
现在参照图2，图2图示了根据本公开的一个实现方式的集成输出电感器的顶视图。如图2所示，集成输出电感器258包括芯222、顶部导电片段224a、224b、224c、224d、224e、224f和224g(统称为“顶部导电片段224”)，底部导电片段226a、226b、226c、226d、226e、226f、226g和226h(统称为“底部导电片段226”)。如图2所示，顶部导电片段224位于芯222上方，而底部导电片段226位于芯222之下，其中顶部导电片段224被连接到底部导电片段226以形成缠绕在芯222周围并且基本上嵌入芯222的连续的线绕组。
在本实现方式中，集成输出电感器258可以对应于图1中的输出电感器158。如图2中所示，集成输出电感器258的一端被耦合至与图1中的切换节点156对应的切换节点焊盘256，而集成输出电感器258的另一端被耦合至与图1中的输出节点162对应的输出节点焊盘262。
如图2中所示，顶部导电片段224a、224b、224c、224d、224e、224f和224g在芯222之上彼此基本上平行并且间隔开，而底部导电片段226a、226b、226c、226d、226e、226f、226g和226h在芯22之下彼此基本上平行并且间隔开。如图2进一步示出的，顶部导电片段224a、224b、224c、224d、224e、224f和224g以与底部导电片段226a、226b、226c、226d、226e、226f、226g和226h呈略微倾斜的角度被布置。作为这一布置的结果，顶部导电片段224a将底部导电片段226a连接到底部导电片段226b。顶部导电片段224b将底部导电片段226b连接到底部导电片段226c。顶部导电片段224c将底部导电片段226c连接到底部导电片段226d。顶部导电片段224d将底部导电片段226d连接到底部导电片段226e。顶部导电片段224e将底部导电片段226e连接到底部导电片段226f。顶部导电片段224f将底部导电片段226f连接到底部导电片段226g。顶部导电片段224g将底部导电片段226g连接到底部导电片段226h。
在本实现方式中，芯222包括铁氧体芯。在其他实现方式中，芯222可以包括其他适合的材料，诸如塑料、铁磁或陶瓷材料。在本实现方式中，顶部导电片段224a、224b、224c、224d、224e、224f和224g可以各自包括具有部分刻蚀部分和至少一个非刻蚀部分的导电片段，其在图2中未明示。类似地，底部导电片段226a、226b、226c、226d、226e、226f、226g和226h可以各自还包括具有部分刻蚀部分和至少一个非刻蚀部分的导电片段，其在图2中未明示。
如图2所示，如以下参考图3A、3B和3C的详细说明，I/O焊盘230被形成在集成输出电感器258的周边的周围以用于功率转换器封装体的电连接。在一些实现方式中，顶部导电片段224a、224b、224c、224d、224e、224f和224g，底部导电片段226a、226b、226c、226d、226e、226f、226g和226h及I/O焊盘230可以各自包括具有高载流能力和适当低的电阻的任何导电材料。例如，顶部导电片段224、底部导电片段226和I/O焊盘230可以各自包括铜、铝或金属合金。集成输出电感器258的厚度、长度和深度可以改变以适合特定应用的需要。
现在参考图3A，图3A图示了根据本公开的一个实现方式的具有集成输出电感器的半导体封装体的顶视图。如图3A所示，半导体封装体302包括叠放在集成输出电感器358之上的半导体裸片310，其中集成输出电感器358包括芯322，顶部导电片段324a、324b、324c、324d、324e、324f和324g(统称为“顶部导电片段324”)和底部导电片段326a、326b、326c、326d、326e、326f、326g和326h(统称为“底部导电片段326”)。半导体裸片310被叠放在集成输出电感器358之上并且通过裸片贴装材料(在图3A中未明示)耦合至集成输出电感器358。
在本实现方式中，半导体裸片310可以包括功率级(在图3A中未明示)，其可以对应于图1中的功率级110。半导体裸片310可以包括在切换节点(例如图1中的切换节点156)处耦合至低侧或同步晶体管(例如图1中的同步晶体管154)的高侧或控制晶体管(例如图1中的控制晶体管152)。半导体裸片310还可以包括被耦合至控制晶体管和同步晶体管的PWM控制和驱动器(例如图1中的PWM控制和驱动器150)。在一个实现方式中，PWM控制和驱动器可以被实现为PWM和控制驱动器IC，并且被配置为向控制晶体管和同步晶体管相应的栅极提供驱动信号。在一个实现方式中，具有控制晶体管和同步晶体管的功率级被单片集成在半导体裸片310上。注意PWM控制和驱动器、控制晶体管和同步晶体管未在图3A中明示,但可以用任何本领域中已知的适合的方法和/或方式被单片集成在半导体裸片310上。
在本实现方式中，半导体裸片310可以包括IV族材料，诸如硅。在另一实现方式中，半导体裸片310可以包括III-V族材料，诸如氮化镓(GaN)。例如，在一些实现方式中，控制晶体管和同步晶体管中的至少一个被实现为III-V族功率晶体管(诸如GaN功率晶体管)可以是有利或可取的。
在本实现方式中，集成输出电感器358可以对应于在图2中的集成输出电感器258，集成输出电感器258可以对应于在图1中的输出电感器158。集成输出电感器358包括切换节点焊盘356和输出节点焊盘362，其可以对应于图1中的相应的切换节点156和输出节点162。如图3A所示，切换节点焊盘356在集成输出电感器358的一端处被耦合至底部导电片段326a，并且输出节点焊盘362在集成输出电感器358的另一端处被耦合至底部导电片段326h。在一个实现方式中，顶部导电片段324和底部导电片段326可以各自包括具有高载流能力和适当低的电阻的任何导电材料。例如，顶部导电片段324和底部导电片段326可以各自包括铜、铝或金属合金。集成输出电感器358的厚度、长度和深度可以改变以适合特定应用的需要。
如图3A所示，顶部导电片段324a、324b、324c、324d、324e、324f和324g在芯322之上彼此基本上平行并且间隔开，而底部导电片段326a、326b、326c、326d、326e、326f、326g和326h在芯322之下彼此基本上平行并且间隔开。如图3A中进一步所示出的，顶部导电片段324a、324b、324c、324d、324e、324f和324g以与底部导电片段326a、326b、326c、326d、326e、326f、326g和326h呈略微倾斜的角度被布置。作为这一布置的结果，顶部导电片段324a将底部导电片段326a连接到底部导电片段326b。顶部导电片段324b将底部导电片段326b连接到底部导电片段326c。顶部导电片段324c将底部导电片段326c连接到底部导电片段326d。顶部导电片段324d将底部导电片段326d连接到底部导电片段326e。顶部导电片段324e将底部导电片段326e连接到底部导电片段326f。顶部导电片段324f将底部导电片段326f连接到底部导电片段326g。顶部导电片段324g将底部导电片段326g连接到底部导电片段326h。结果是，顶部导电片段324和底部导电片段326被连接以形成在芯322周围的连续的线绕组。
由顶部导电片段324a、324b、324c、324d、324e、324f和324g和底部导电片段326a、326b、326c、326d、326e、326f、326g和326h形成的线绕组的绕组的数量可以在从几个到几百个线绕组的范围上。顶部导电片段324a、324b、324c、324d、324e、324f和324g通过使用电连接件(在图3A中未明示)被连接到底部导电片段326a、326b、326c、326d、326e、326f、326g和326h。电连接件可以包括焊接体(solder body)，如焊膏,例如。在其他实现方式中，电连接件可以采取导电的裸片贴装材料的形式。例如，导电的裸片贴装材料可以包括导电环氧树脂、导电烧结材料或扩散接合材料。例如，导电的裸片贴装材料可以包括导电环氧树脂、导电烧结材料或扩散接合材料。
在本实现方式中，芯322包括铁氧体芯。在其他实现方式中，芯322可以包括其他适合的材料，如塑料、铁磁或陶瓷材料。在本实现方式中，顶部导电片段324a、324b、324c、324d、324e、324f和324g可以各自包括具有部分刻蚀部分和至少一个非刻蚀部分的导电片段，其在图3A中未明示。同样地，底部导电片段326a、326b、326c、326d、326e、326f、326g和326h还可以各自包括具有部分刻蚀部分和至少一个非刻蚀部分导电片段，其在图3A中未明示。
例如，半导体封装体302还包括在集成输出电感器358周边的周围的I/O焊盘330，其中I/O焊盘330通过接线键合328被电耦合至半导体裸片310。如图3A所示，接线键合328被配置为将在半导体裸片310的顶表面处的各个端子(在图3A中未明示)电耦合到相应的I/O焊盘330。另外，一个或多个接线键合328被配置为将半导体裸片310的切换节点(例如图中的切换节点156)电耦合到在底部导电片段326a上的切换节点焊盘356。在一些实现方式中，接线键合328可以各自包括铜、金或另一适合的导电材料，例如。在其他实现方式中，接线键合328可以被包括诸如Al、Au、Cu和/或其他金属或复合材料的导电材料的导电带(conductive ribbon)或者其他连接件所替代。
封装外壳(在图3A中未明示)被配置为将半导体裸片310、裸片贴装材料312、集成输出电感器358、接线键合328和I/O焊盘330封装以形成封闭的封装体。封装外壳334可以包括任何适合的物质，如封装剂和/或模制化合物，用于为半导体封装体302提供机械和/或环境的保护。在一些实现方式中，半导体封装体302可以为四方扁平无引线(quad-flat no-leads,QFN)封装体，如功率QFN(PQFN)封装体。
现在参考图3B，图3B图示了根据本公开的一个实现方式的具有集成输出电感器的半导体封装体的截面图。特别地，图3B图示了半导体封装体302沿着图3A中线380-380的截面图。以相似的附图标记表示图3A中相似的特征，在图3B中的半导体封装体302包括叠放在集成输出电感器358之上并且通过裸片贴装材料312附接到集成输出电感器358的半导体裸片310。集成输出电感器358部分地包括，芯322和具有被连接到底部导电片段326d的顶部导电片段324c的绕组。如图3B所示，半导体封装体302还包括在集成输出电感器358周边上并且通过接线键合328耦合至半导体裸片310的I/O焊盘330。封装外壳334被配置为将半导体裸片310、裸片贴装材料312、集成输出电感器358、接线键合328、I/O焊盘330和电连接件372封装以形成封闭的封装体。
如图3B所示，顶部导电片段324c包括非刻蚀部分323a和323c及部分刻蚀部分323b。非刻蚀部分323a和323c保持顶部导电片段324c的全厚度，而部分刻蚀部分323b具有为顶部导电片段324c全厚度的一部分(例如一半)的厚度。在本实现方式中，非刻蚀部分323a和323c具有为顶部导电片段324c的全厚度的基本上均匀的厚度。部分刻蚀部分323b也具有为顶部导电片段324c全厚度的一部分的基本上均匀的厚度。底部导电片段326d包括非刻蚀部分325a和325c以及部分刻蚀部分325b。非刻蚀部分325a和325c保持底部导电片段326d的全厚度，而部分刻蚀部分325b具有为底部导电片段326d全厚度的一部分(例如一半)的厚度。在本实现方式中，非刻蚀部分325a和325c具有为底部导电片段326d的全厚度的基本上均匀的厚度。部分刻蚀部分325b也具有为底部导电片段326d全厚度的一部分的基本上均匀的厚度。
如图3B所示，顶部导电片段324c和底部导电片段326d形成在芯322周围的绕组，其中顶部导电片段324c的非刻蚀部分323a在集成输出电感器358的一端处通过使用电连接件372(如焊膏)被电和机械地耦合至底部导电片段326d的非刻蚀部分325a。顶部导电片段324c的部分刻蚀部分323b在顶部导电片段324c中形成凹部(recess)。在由顶部导电片段324c的部分刻蚀部分323b形成的凹部下面，底部导电片段326d的部分刻蚀部分325b在底部导电片段326d中形成凹部。因此，在顶部导电片段324c和底部导电片段326d中的凹部一起形成用于收容和嵌入芯322的内部空间。
注意在图3B中所示的截面图中，顶部导电片段324c和底部导电片段326d只在集成输出电感器358的一端处被连接。这是因为顶部导电片段324c位于底部导电片段326d上方且被以与底部导电片段326d(如图3A中所示)呈略微倾斜的角度被布置。作为这一布置的结果，底部导电片段326d的非刻蚀部分325c被连接到顶部导电片段324d(在图3B中未明示)的非刻蚀部分(例如图3C中的非刻蚀部分327c)，而顶部导电片段324c的非刻蚀部分323c被连接到底部导电片段326c(在图3B中未明示)的非刻蚀部分。因此，顶部导电片段324和底部导电片段326以这样的方式被连接以在芯322周围形成连续的线绕组，如图3A中所示。
如图3B所示，接线键合328被配置为将在半导体裸片310的顶表面处的各个端子(在图3B中未明示)电耦合到相应的I/O焊盘330。在本实现方式中，I/O焊盘330各自包括使用电连接件372(如焊膏)连接到底部焊盘332的顶部焊盘331。在本实现方式中，顶部焊盘331和底部焊盘332可以各自包括非刻蚀部分和部分刻蚀部分，如图3B中所示。在本实现方式中，底部导电片段326d和I/O焊盘330的底部焊盘332可以在单次加工动作中形成，而顶部导电片段324c和I/O焊盘330的顶部焊盘331可以在单次加工动作中形成。在本实现方式中，顶部导电片段324c、底部导电片段326d和I/O焊盘330可以各自包括具有高载流能力和适当低的电阻的任何导电材料，如铜、铝、钨或金属合金。
如图3B所示，封装外壳334将半导体裸片310、裸片贴装材料312、集成输出电感器358、接线键合328、I/O焊盘330和电连接件372封装以形成封闭的封装体。封装外壳334可以包括任何适合的物质，诸如封装剂和/或模制化合物，用于为半导体封装体302提供机械和/或环境的保护。
现在参考图3C，图3C图示了根据本公开的一个实现方式的具有集成输出电感器的半导体封装体的截面图。特别地，图3C示出半导体封装体302沿着图3A中线390-390的断面。以相似的附图标记表示图3A中类似的特征，在图3C中的半导体封装体302包括被叠放在集成输出电感器358之上并且通过裸片贴装材料312附接到集成输出电感器358的半导体裸片310。集成输出电感器358部分地包括，芯322和具有被连接到底部导电片段326d的顶部导电片段324d的线绕组。如图3C所示，半导体封装体302还包括在集成输出电感器358周边的I/O焊盘330。封装外壳334被配置为将半导体裸片310、裸片贴装材料312、集成输出电感器358、I/O焊盘330和电连接件372封装以形成封闭的封装体。
如图3C所示，顶部导电片段324d与图3B中的顶部导电片段324c相似，包括非刻蚀部分327a和327c以及部分刻蚀部分327b。非刻蚀部分327a和327c保持顶部导电片段324d的全厚度，而部分刻蚀部分327b具有为顶部导电片段324d全厚度的一部分(例如一半)的厚度。在本实现方式中，非刻蚀部分327a和327c具有为顶部导电片段324d的全厚度的基本上均匀的厚度。部分刻蚀部分327b也具有为顶部导电片段324d全厚度的一部分的基本上均匀的厚度。底部导电片段326d包括非刻蚀部分325a和325c以及部分刻蚀部分325b。非刻蚀部分325a和325c保持底部导电片段326d的全厚度，而部分刻蚀部分325b具有为底部导电片段326d全厚度的一部分(例如一半)的厚度。在本实现方式中，非刻蚀部分325a和325c具有为底部导电片段326d的全厚度的基本上均匀的厚度。部分刻蚀部分325b也具有为底部导电片段326d全厚度的一部分的基本上均匀的厚度。
如图3C所示，顶部导电片段324d和底部导电片段326d形成在芯322周围的绕组，其中通过使用电连接件372(如焊膏)将顶部导电片段324d的非刻蚀部分327c在集成输出电感器358的一端处电和机械地耦合至底部导电片段326d的非刻蚀部分325c。顶部导电片段324d的部分刻蚀部分327b在顶部导电片段324d中形成凹部。在由顶部导电片段324d的部分刻蚀部分327b形成的凹部下面，底部导电片段326d的部分刻蚀部分325b在底部导电片段326d中形成凹部。因此，在顶部导电片段324d和底部导电片段326d中的凹部一起形成用于收容或嵌入芯322的内部空间。
注意,在图3C中的截面图中，顶部导电片段324d和底部导电片段326d只在集成输出电感器358的一端处被连接。这是因为顶部导电片段324d位于底部导电片段326d上方并且以与底部导电片段326d(如3A中所示)呈略微倾斜的角度被布置。作为这一布置的结果，底部导电片段326d的非刻蚀部分325a被连接到顶部导电片段324c的非刻蚀部分(例如图3B中的非刻蚀部分323a)(在图3B中未明示)，而顶部导电片段324d的非刻蚀部分327a被连接到底部导电片段326e的非刻蚀部分(在图3B中未明示)。因此，顶部导电片段324和底部导电片段326被以这样的方式连接以形成在芯322周围的连续的线绕组，如3A中所示。
如图3C所示，I/O焊盘330各自包括通过使用电连接件372(如焊膏)连接到底部焊盘332的顶部焊盘331。在本实现方式中，顶部焊盘331和底部焊盘332可以各自包括非刻蚀部分和部分刻蚀部分，如图3C中所示。在本实现方式中，底部导电片段326d和I/O焊盘330的底部焊盘332可以在单次加工动作中形成，而顶部导电片段324d和I/O焊盘330的顶部焊盘331可以在单次加工动作中形成。在本实现方式中，顶部导电片段324d、底部导电片段326d和I/O焊盘330可以各自包括具有高载流能力和适当低的电阻的任何导电材料，诸如铜、铝、钨或金属合金。
如图3C所示，封装外壳334将半导体裸片310、裸片贴装材料312、集成输出电感器358、I/O焊盘330和电连接件372封装以形成封闭的封装体。封装外壳334可以包括任何适合的物质，如封装剂和/或模制化合物，用于为半导体封装体302提供机械和/或环境的保护。
如图3A、3B和3C所示，因为集成输出电感器358的芯322被嵌入由顶部导电片段324和底部导电片段326的部分刻蚀部分形成的内部空间中，集成输出电感器358的总体高度可以被大幅降低，其转而降低半导体封装体302外形规格。与将个体半导体裸片与输出电感器并排布置的的传统的功率半导体封装体对比，依照本实现方式，因为半导体裸片310位于集成输出电感器358之上，半导体封装体302可以有利地具有降低的覆盖区(footprint)，由此进一步降低半导体封装体302的外形规格。
并且，通过采用顶部导电片段324和底部导电片段326以形成在芯322周围的连续的线绕组，在每个相邻的顶部导电片段324和底部导电片段326对之间留有空间，封装外壳334可以占据顶部导电片段324和底部导电片段326之间并且在芯322周围的内部空间以提供机械支撑并且将芯322保持在适当位置。另外，封装外壳334可以在单次封装动作中封装半导体裸片310和集成输出电感器358，由此降低制造时间和成本。封装外壳334可以具有出色的导热性，将热从半导体裸片310和集成输出电感器358转移走。此外，例如，由于底部导电片段326在半导体封装体302的底表面处被暴露，因此底部导电片段326可以起散热其的作用以通过将热直接辐射到环境空气而提供增强的热耗散。此外，由于底部导电片段326在半导体封装体302的底表面处被暴露，因此半导体封装体302可以被表面安装到衬底，诸如印刷电路板。
从以上说明显而易见地，在不脱离那些理念的范围的前提下，各种技术均可以被用于实施本申请所说明的理念。此外，虽然理念是特定参考某些实现方式而进行的说明，但本领域普通技术人员会认识到在形式和细节上可以改变而不脱离那些理念的范围。正因如此，在各个方面，所述的实现方式被认为是是示例说明的而不是限制性的。还应理解，本申请不限于以上说明的具体实现方式，在不脱离本公开的范围的前提下很多重新布置、修改和替代都是可能的。

Claims (18)

1.一种半导体封装体，包括：
半导体裸片，其包括控制晶体管和同步晶体管；
集成输出电感器，其包括在芯周围的绕组并且耦合至所述半导体裸片；
其中所述绕组包括被连接到多个底部导电片段的多个顶部导电片段，
其中所述半导体裸片通过裸片贴装材料被非电地附接到所述集成输出电感器的所述多个顶部导电片段，并且所述半导体裸片直接电耦合到所述多个底部导电片段。
2.根据权利要求1所述的半导体封装体，其中所述控制晶体管和所述同步晶体管被配置作为半桥，并且其中所述控制晶体管在切换节点处耦合到所述同步晶体管。
3.根据权利要求2所述的半导体封装体，其中所述集成输出电感器被耦合至所述半桥的所述切换节点。
4.根据权利要求1所述的半导体封装体，其中所述多个顶部导电片段和所述多个底部导电片段中的至少一项包括部分刻蚀部分和非刻蚀部分。
5.根据权利要求1所述的半导体封装体，其中所述半导体裸片进一步包括耦合到所述控制晶体管和所述同步晶体管的驱动器集成电路。
6.根据权利要求1所述的半导体封装体，其中所述控制晶体管和所述同步晶体管中的至少一个包括III-V族晶体管。
7.根据权利要求1所述的半导体封装体，其中所述控制晶体管和所述同步晶体管中的至少一个包括IV族晶体管。
8.根据权利要求1所述的半导体封装体，其中所述芯为铁氧体芯。
9.根据权利要求1所述的半导体封装体，其中所述半导体裸片和所述集成输出电感器被封装在模制化合物中。
10.一种半导体封装体，包括:
集成输出电感器，其包括在芯周围的绕组；
叠放在所述集成输出电感器之上的功率级,所述功率级包括按半桥方式连接的控制晶体管和同步晶体管；
其中所述绕组包括连接到多个底部导电片段的多个顶部导电片段，
其中所述功率级通过裸片贴装材料被非电地附接到所述集成输出电感器的所述多个顶部导电片段，并且所述功率级直接电耦合到所述多个底部导电片段。
11.根据权利要求10所述的半导体封装体，其中所述多个顶部导电片段和所述多个底部导电片段中的至少一个包括部分刻蚀部分和非刻蚀部分。
12.根据权利要求10所述的半导体封装体，其中所述集成输出电感器被耦合至所述半桥的切换节点。
13.根据权利要求10所述的半导体封装体，其中所述功率级进一步包括耦合至所述控制晶体管和所述同步晶体管的驱动器集成电路。
14.根据权利要求10所述的半导体封装体，其中所述芯为铁氧体芯。
15.根据权利要求10所述的半导体封装体，其中所述控制晶体管和所述同步晶体管中的至少一个包括III-V族晶体管。
16.根据权利要求10所述的半导体封装体，其中所述控制晶体管和所述同步晶体管中的至少一个包括IV族晶体管。
17.根据权利要求10所述的半导体封装体，其中所述控制晶体管和所述同步晶体管被单片集成在半导体裸片上。
18.根据权利要求10所述的半导体封装体，其中所述功率级和所述集成输出电感器被封装在模制化合物中。
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