CN1058808C - 半导体器件隔离膜的制造方法 - Google Patents

半导体器件隔离膜的制造方法 Download PDF

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CN1058808C
CN1058808C CN96110757A CN96110757A CN1058808C CN 1058808 C CN1058808 C CN 1058808C CN 96110757 A CN96110757 A CN 96110757A CN 96110757 A CN96110757 A CN 96110757A CN 1058808 C CN1058808 C CN 1058808C
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silicon substrate
trap
semiconductor device
groove
forming
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CN1147148A (zh
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李敬馥
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种半导体器件隔离膜的制造方法，它包括下列步骤：在硅衬底上形成晶体管；通过腐蚀硅衬底的选定部分，形成沟槽；及在形成所述沟槽后，在获得的结构上形成层间绝缘膜，由此在沟槽中形成器件隔离膜。

Description

半导体器件隔离膜的制造方法
本发明涉及制造半导体器件的方法，特别涉及制造在形成晶体管后形成器件隔离膜的半导体器件。
通常，在制造半导体器件过程中，在形成器件隔离膜后，再形成晶体管。为了隔离有源区和场区，而广泛地利用场氧化膜，其中利用LOCOS(硅的局部氧化)或者PBL(多晶硅层缓冲LOCOS)方法，形成场氧化膜。一种制造场氧化膜的常规方法，包括下列步骤：在硅衬底上形成耐氧化的掩模；通过高温氧化处理在硅衬底上生长氧化膜；除掉耐氧化的掩模。上述方法存在的缺点是由于在场氧化膜的边缘部分产生乌嘴，有源区减少。由上述方法形成的场氧化膜具有高的拓朴结构。因此，不可能制造大规模集成器件。
因此，本发明的目的是提供一种半导体器件隔离膜的制造方法，它能制造大规模集成器件，并改进制造半导体器件的方法。
本发明另一目的是提供一种沟槽型器件隔离膜。
为实现上述目的，按照本发明的一种半导体器件隔离膜的制造方法包括下列步骤：在硅衬底中形成阱；在阱中形成源区和漏区；依次在源区和漏区之间的阱上形成栅氧化层和栅电极；由此形成晶体管；通过腐蚀硅衬底的选定部分形成沟槽；及在形成沟槽后在所获得的结构上形成层间绝缘膜，由此在沟槽中形成器件隔离膜。
为了比较充分地了解本发明的特征和目的，下面参照附图进行详细的说明，其中：
图1A到图1E表示解释按照本发明的半导体器件隔离膜的制造方法的器件的剖视图。
各附图中相同的部分用相同的标记表示。
下面参考附图详细地说明本发明。
图1A到图1E表示解释按照本发明的半导体器件隔离膜的制造方法的器件的剖视图。
参看图1A，在硅衬底1上面、形成第1光致抗蚀剂图形10。利用第1光致抗蚀剂图形10作掩模，通过离子注入工艺，在硅衬底1中形成阱2。
参看图1B，除掉第1光致抗蚀剂图形10。然后在形成阱2的硅衬底1上，形成第2光致抗蚀图形20。利用第2光致抗蚀剂图形20作掩模，通过离子注入工艺，在阱2中形成源区3A和漏区3B。
参看图1C，除掉第2光致抗蚀剂图形20。通过氧化处理在硅衬底1上形成氧化膜，通过淀积多晶硅工艺在氧化膜上形成多晶硅层，依次把多晶硅层和氧化膜层刻成图形，由此，在源区3A和漏区3B之间的阱2上面形成栅氧化层4和栅电极5。于是制成含有栅电极5，源区3A和漏区3B的晶体管。
参看图1D，在形成晶体管的硅衬底1上形成第3光致抗蚀剂图形30。利用第3光致抗蚀剂图形30作掩模，通过各向异性腐蚀工艺，腐蚀硅衬底1的选定部分，形成沟槽6。在邻接阱2的硅衬底1中形成沟槽6。
如上所述，以获得特殊器件的特性，能够改变沟槽6的深度和尺寸。
参看图1E，除掉第3光致抗蚀剂图形30。在腐蚀掉第3光致抗蚀剂图形30以后，在获得的结构上形成层间绝缘膜7，由此，在沟槽6中形成器件隔离膜7A。
如上所述，本发明通过形成沟槽型器件隔离膜能够制造大规模集成器件，通过同时形成层间绝缘膜和器件隔离膜，提高器件的生产率。
如前所述，虽然叙述了具有一定特殊性的优选实施例，但那仅仅是为了说明本发明的原理，应当了解，本发明不限于上述公开和说明的优选实施例。因此，在本发明的范围和精神实质内，可以作各种适当的变化，它们皆包括在本发明的进一步实施例中。

Claims (3)

1.一种半导体器件隔离膜的制造方法，其特征在于，该方法包括下列步骤：
在硅衬底中形成阱；
在所述阱中形成源区和漏区；
在所述源区和所述漏区之间的所述阱上面，依次形成栅氧化层和栅电极，由此，形成晶体管；
通过腐蚀所述硅衬底的选定部分，形成沟槽；以及
在形成所述沟槽后，在获得的结构上面形成层间绝缘膜，由此在所述沟槽中形成器件隔离膜。
2.按照权利要求1的方法，其特征是，在与所述阱相邻接的所述硅衬底中，形成所述沟槽。
3.按照权利要求1的方法，其特征是，通过各向异性腐蚀处理，形成所述沟槽。
CN96110757A 1995-06-24 1996-06-24 半导体器件隔离膜的制造方法 Expired - Fee Related CN1058808C (zh)

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KR1019950017290A KR100208449B1 (ko) 1995-06-24 1995-06-24 반도체 소자의 제조방법
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KR17290/95 1995-06-24

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KR20010066141A (ko) * 1999-12-31 2001-07-11 황인길 반도체 소자의 제조 방법
US7279397B2 (en) * 2004-07-27 2007-10-09 Texas Instruments Incorporated Shallow trench isolation method

Citations (1)

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EP0399066A1 (en) * 1988-03-24 1990-11-28 Seiko Epson Corporation Method of manufacturing a semiconductor device comprising an isolation region and a well region

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US4661202A (en) * 1984-02-14 1987-04-28 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JPH01125971A (ja) * 1987-11-11 1989-05-18 Seiko Instr & Electron Ltd Ｃ−ｍｉｓ型半導体装置とその製造方法
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0399066A1 (en) * 1988-03-24 1990-11-28 Seiko Epson Corporation Method of manufacturing a semiconductor device comprising an isolation region and a well region

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US5830796A (en) 1998-11-03
CN1147148A (zh) 1997-04-09
TW296465B (en) 1997-01-21
KR970003801A (ko) 1997-01-29

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