CN105870095B - 在短边缘处具有接触销的半导体芯片封装结构 - Google Patents

在短边缘处具有接触销的半导体芯片封装结构 Download PDF

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CN105870095B
CN105870095B CN201610082035.3A CN201610082035A CN105870095B CN 105870095 B CN105870095 B CN 105870095B CN 201610082035 A CN201610082035 A CN 201610082035A CN 105870095 B CN105870095 B CN 105870095B
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semiconductor chip
electrical contact
contact element
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chip
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CN105870095A (zh
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C·M·庄
R·T·科罗科特谢
T·S·李
S·K·穆鲁甘
R·奥特伦巴
K·席斯
C·V·陈
W·B·郑
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Infineon Technologies Austria AG
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Abstract

一种半导体芯片封装结构包括：半导体芯片；包封半导体芯片的包封体；芯片垫；以及电接触元件，所述电接触元件与半导体芯片连接，且向外延伸，其中，包封体包括六个侧面，电接触元件仅延伸穿过两个相反的侧面，所述两个相反的侧面在所有侧面中具有最小的表面积；其中，半导体芯片设置在所述芯片垫上，且芯片垫的远离半导体芯片的主面至少部分暴露于外。

Description

在短边缘处具有接触销的半导体芯片封装结构
技术领域
本公开涉及半导体芯片封装结构的领域。
背景技术
半导体封装结构可包括半导体芯片、包封半导体芯片的包封体以及电接触元件，所述电接触元件与半导体芯片连接，且以侧向方向延伸穿过包封体。电接触元件可根据用户侧的不同的用途需求或要求以不同的方式形成。根据一个变型，半导体封装结构被形成为通孔装置，其中，电接触元件可被形成为要插入用户侧的通孔插座内的接触销。根据另一个变型，半导体封装结构被形成为表面贴装装置，其中，电接触元件形成有要附连在用户侧的合适的接触表面上的平坦共面下表面。为了制作半导体芯片封装结构和它们的电接触元件，也必须考虑其他方面。一个方面可能是，半导体芯片可在操作过程中产生热量，且半导体芯片封装结构的整个设计可能需要被优化，以便于最高效的热消散。另一方面涉及半导体芯片封装结构的制作过程，特别是如何增大制作过程的引线框架密度、从而降低每个半导体芯片封装结构的制作成本的问题。
附图说明
所包括的附图用于提供对实施例的进一步理解，且被包括在该说明书中并构成说明书的一部分。附图示出了实施例，且与说明书一起用于解释实施例的原理。其他实施例和实施例的许多期望优点在参看了以下详细的描述之后会变得更好理解，从而也容易理解。
附图中的元件不必彼此成比例绘制。相同的附图标记指代相应的类似部件。
图1包括图1A和图1B，示出了半导体芯片封装结构的一个例子的示意性剖视侧视图(A)和顶视图(B)，根据一个例子，所述半导体芯片封装结构包括外露芯片垫和销状电接触元件。
图2包括图2A和图2B，示出了半导体芯片封装结构的示意性剖视侧视图(A)和示意性透视顶视图，根据一个示例，所述半导体芯片封装结构被设计用于表面贴装技术且包括外露芯片垫和电接触元件。
图3示出了示例性组件的示意性透视仰视图，该组件将要被包封以形成半导体芯片封装结构。
具体实施方式
在以下的详细描述中，将会参看构成说明书的一部分的附图，在附图中，示出了可以实施本发明的示例说明性的特定实施例。在这点上，方向术语，例如“上”、“下”、“前”、“后”、“前导”、“尾后”等相对于正在描述的附图的方位使用。由于各个实施例的构件可以以多种不同的方位定位，因此，方向术语用于说明目的，而不是限制目的。应当理解，也可以使用其他实施例，而且也可在不脱离本发明的范围的情况下进行结构上或逻辑上的改变。因此，下面的详细描述不应认为是限制性的，本发明的范围由所附的权利要求限定。
应当理解，在此描述的各种示例性实施例的特征可以彼此组合，除非明确指出不可组合。
该说明书中所采用的术语“结合”、“附连”、“连接”、“耦合”和/或“电连接/电耦合”不是意味着，元件或层必须直接接触在一起；中间元件或层可以相应地设置在“结合”、“附连”、“连接”、“耦合”和/或“电连接/电耦合”的元件之间。然而，根据本公开，上述术语也可以可选地具有元件或层直接接触在一起的特定含义，即，没有中间元件或层相应地设置在“结合”、“附连”、“连接”、“耦合”和/或“电连接/电耦合”的元件之间。
而且，可在此相对于形成或位于某一表面“上方”的部件、元件或材料层使用的术语“上方”来表示，所述部件、元件或材料层“间接地”位于(例如，放置、形成、沉积等)所述表面上，所述表面与所述部件、元件或材料层之间设置一个或多个附加部件、元件或层。然而，在此相对于形成或位于某一表面“上方”的部件、元件或材料层使用的术语“上方”也可以可选地具有以下特定的技术含义：所述部件、元件或材料层“直接地”位于(例如，放置、形成、沉积等)所述表面上、例如直接接触所述表面。
下面，将描述包含半导体芯片的装置或半导体封装结构。半导体芯片可以为不同类型，可以通过不同的技术制造且可以包括例如集成电路、光电或机电式电路和/或无源器件。半导体芯片可例如被设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、存储电路或集成无源器件。它们可包括控制电路、微处理器或微机电构件。而且，它们可被构造成功率半导体芯片、例如功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极型晶体管)、JFET(面结型栅场效应晶体管)、功率双极型晶体管或功率二极管。特别地，可以包括具有竖直结构的半导体芯片，换言之，半导体芯片可以以使电流沿垂直于半导体芯片的主面的方向流动的方式制作。具有竖直结构的半导体芯片可以特别是在其两个主面上、即其上侧和下侧具有接触元件。特别地，功率半导体芯片可具有竖直结构。示例性地，功率MOSFET的源极和栅极可以坐落在一个主面上，而功率MOSFET的漏极设置在另一个主面上。而且，下面描述的电子模块可包括用于控制其他半导体芯片的集成电路、例如功率半导体芯片的集成电路的集成电路。半导体芯片可以基于特定的半导体材料、例如Si、SiC、SiGe、GaAs、GaN、AlGaAs制造，也可基于任何其他的半导体材料制造，而且可包含不是半导体而例如是绝缘体、塑料或金属的无机和/或有机材料。
半导体芯片或半导体芯片的至少一些部件覆盖有包封材料以形成包封结构(例如，模制体)，其可以是电绝缘的。所述包封结构可以是介电材料，且可由任何合适的脲醛、热塑料或热固性材料或层叠物(半固化片)制成。包封物可包含填充材料。在其沉积之后，包封物可仅部分硬化，且可以在施加能量(例如，热量、UV光线等)之后完全硬化，以形成包封物。可以采用各种技术来将半导体芯片覆盖上包封物，例如可以采用压模法、注射成型、粉料模塑、液体成型、分配或层压。
图1以示意性剖视侧视图(A)和顶视图(B)示出了根据一个示例的半导体芯片封装结构的例子。图1A的剖视图是沿着图1B中的线A-A表示的平面所作的。半导体芯片封装结构10包括半导体芯片11、包封半导体芯片11的包封体12、上面设置有半导体芯片11的芯片垫13.2以及电接触元件13.1，所述电接触元件13.1与半导体芯片11连接且以向外的方向延伸穿过包封体12。包封体12包括六个侧面12A-12F。电接触元件13.1仅延伸通过两个相反的侧面12C和12D，所述两个相反的侧面12C和12D在所有侧面12A-12F中具有最小的表面积。芯片垫13.2的远离半导体芯片11的主面至少部分地暴露于外。
根据图1的半导体芯片封装结构10的一个例子，所述六个侧面12A-12F包括在所有侧面12A-12F中具有最大的表面积的两个相反的主面12E和12F。半导体芯片11可以以使芯片的主平面与两个主面12E和12F平行的方式设置在包封体12内。
根据图1的半导体芯片封装结构10的一个例子，半导体芯片封装结构10包括引线框架13，所述引线框架13包括电接触元件13.1和芯片垫13.2。在图1所示的例子中，芯片垫13.2的整个上主面暴露于外。然而，也可以是这种情况：芯片垫13.2的上主面的仅一部分暴露于外。无论如何，这种结构使得用户可将散热装置附连到半导体芯片封装结构10上，使得由半导体芯片11产生的过多的热量可被有效地消散。通过这种方式，可在空间上有效地将电路径和热路径彼此分离，因为大部分热量将通过芯片垫13.2和散热装置消散。
根据图1的半导体芯片封装结构10的一个例子，芯片垫13.2与电接触元件13.1中的一个或多个连接。它可例如与电接触元件13.1中的一个或多个续连，特别是由引线框架的一部分形成。根据另一个例子，芯片垫不与电接触元件中的任何一个连接。
根据图1的半导体芯片封装结构10的一个例子，电接触元件13.1被构造成如图1A所示的接触销，使得封装结构被构造为通孔装置。根据另一个例子，半导体芯片封装结构也可被构造为表面贴装装置。下面，将会示出其一个实施例。
根据图1的半导体芯片封装结构10的一个例子，电接触元件13.1包括第一电接触元件和第二电接触元件13.1，所述第一电接触元件设置在侧面12D处且与芯片垫13.2续连，所述第二电接触元件13.1设置在侧面12C处而不与芯片垫13.2续连。更具体地，可以是这种情况：半导体芯片11包括绝缘栅双极型晶体管(IGBT)，其具有位于所述半导体芯片的上表面处的漏极接触垫和设置在下表面上的栅极接触垫；设置在下表面上的源极接触垫；以及设置在下表面上的源极感测(source sense)接触垫。在这种情况下，设置在侧面12D处的第一电接触元件13.1均与芯片垫13.2电连接，因此与漏极接触元件连接，从而，在图1B中被标记为“D”。第二电接触元件13.1在图1B中被标记为“S”和“G”，这意味着，它们通过连接线14连接到半导体芯片11的下表面上的栅极垫、源极垫或源极感测接触垫中的任一个。其特定的实施例将在图3中示出，且下面将结合图3更详细地解释。
根据图1的半导体芯片封装结构10的一个例子，半导体芯片封装结构10如图1所示地包括一个且仅包括一个半导体芯片11，或者它也可包含一个以上的半导体芯片。它也可包含一个或多个半导体芯片，且还可附加地包括一个或多个也可设置在引线框架的多个部分上的无源装置，例如电阻器、电感器或电容器。根据一个示例，半导体芯片11包括电阻器、金属氧化物半导体晶体管、竖直晶体管、绝缘栅双极型晶体管和功率晶体管中的一个或多个。
根据图1的半导体芯片封装结构10的一个例子，包封体12如图1A所示地具有矩形横截面，且电接触元件13.1仅延伸通过矩形的两个相对的短边，所述两个相对的短边与图1A中以附图标记12C和12D标记的侧面对应。根据其一个示例，矩形的长边的长度、即侧面12E和12F中的一个的长度与矩形的短边的长度、即侧面12C和12D中的一个的长度之间的比值在2-3之间或大于3。
根据图1的半导体芯片封装结构10的一个例子，半导体芯片封装结构10具有矩形体的形式。半导体芯片封装结构10的长度可以定义为侧面12C和12D之间的距离，半导体芯片封装结构10的宽度可以被定义为侧面12A和12B之间的距离，半导体芯片封装结构10的高度可以被定义为侧面12E和12F之间的距离。根据一个示例，半导体芯片封装结构10的长度可以处于10mm-25mm的范围内，半导体芯片封装结构10的宽度可以在4mm-10mm的范围内，半导体芯片封装结构10的高度可以在1mm-4mm的范围内。
图2以剖视图(A)和透视顶视图(B)示出了被构造为表面贴装装置的半导体芯片封装结构的一个例子。图2的半导体芯片封装结构20包括半导体芯片(未示出)、包封体22和电接触元件23.1，所述电接触元件23.1与半导体芯片连接，且以向外的方向延伸穿过包封体22。电接触元件23.1首先以侧向方向延伸(例如图1的例子的电接触元件13.1)，然后以使它们的下表面共面的方式弯曲，使得半导体芯片封装结构20可用作用户侧的表面贴装装置。
图2的半导体芯片封装结构20的其他细节可以类似于图1中所示的例子的相应细节。特别地，电接触元件23.1可以是引线框架23的一部分，其中，引线框架23进一步包括芯片垫23.2，半导体芯片附连到所述芯片垫23.2。
图3示出了包括引线框架33和连接到引线框架33的半导体芯片31的组件。如图3所示的组件示出了图2的半导体芯片封装结构20在将包封体22施加到它之前的透视仰视图。半导体芯片31可由绝缘栅双极型(IGB)晶体管构成，所述绝缘栅双极型(IGB)晶体管以漏极垫表面附连到芯片垫33.2。右上方的电接触元件33.1与芯片垫33.2续连，从而与漏极接触部位于相同的电势下。半导体芯片31的上表面包括大的源极垫区域和小的栅极垫区域和源极感测区域。大的源极垫区域借助于均连接到大的源极接触垫的两个不同的接触区域的两个连接线34连接到左下方的电接触元件33.1中的三个。其他两个左下方的电接触元件33.1利用连接线连接到栅极垫和源极感测垫。
尽管在此已经示出了和描述了特定的实施例，但本领域的技术人员应该理解，在不脱离本发明的范围的情况下也可为所述特定的实施例使用各种替代和/或等同实施方式。本申请意欲覆盖在此讨论的特定实施例的任何调整或变型。因此，本发明应仅由权利要求书及其等同方案限制。

Claims (15)

1.一种半导体芯片封装结构，包括：
导电引线框架，所述导电引线框架包括芯片垫、与芯片垫续连的多个第一电接触元件和与芯片垫电隔离的多个第二电接触元件，所述多个第二电接触元件中的第一子组彼此续连，所述多个第二电接触元件中的第二子组彼此分离且与第一子组的电接触元件分离；
半导体芯片，所述半导体芯片附连到芯片垫，且包括设置在半导体芯片的远离芯片垫的主面上的源极接触垫；
多个连接线，所述多个连接线将所述多个第二电接触元件中的第一子组连接到源极接触垫，其中，所述连接线连接到源极接触垫的至少两个不同的接触区域；以及
包封半导体芯片的包封体；
其中，包封体包括六个侧面，所述多个第一电接触元件和所述多个第二电接触元件均与半导体芯片连接，且向外仅延伸穿过两个相反的侧面，所述两个相反的侧面在所有侧面中具有最小的表面积；
其中，芯片垫具有远离半导体芯片且在包封体的具有最大的表面积的第一侧面处至少部分暴露于外的主面；以及
其中，所述多个第一电接触元件和所述多个第二电接触元件向包封体的与第一侧面相反的第二侧面延伸，使得半导体芯片封装结构具有安装结构，在所述安装结构中，芯片垫的至少部分外露的主面背向所述多个第一电接触元件和所述多个第二电接触元件所要附连到的接触表面。
2.如权利要求1所述的半导体芯片封装结构，其特征在于，
所述多个第一电接触元件设置在所述两个相反的侧面的第一侧处；以及
所述多个第二电接触元件设置在所述两个相反的侧面的第二侧处。
3.如前面权利要求中任一所述的半导体芯片封装结构，其特征在于，
半导体芯片包括晶体管、金属氧化物半导体晶体管、竖直晶体管、绝缘栅双极型晶体管和功率晶体管中的一个或多个。
4.如权利要求1或2所述的半导体芯片封装结构，其特征在于，
包封体具有矩形形状，且所述多个第一电接触元件和所述多个第二电接触元件仅延伸穿过矩形的两个相反的短边。
5.如权利要求4所述的半导体芯片封装结构，其特征在于，
矩形的长边的长度与矩形的短边的长度之间的比值在2-3之间或大于3。
6.如权利要求1-2、5中任一所述的半导体芯片封装结构，其特征在于，
半导体芯片包括多个电装置。
7.如权利要求1-2、5中任一所述的半导体芯片封装结构，其特征在于，
半导体封装结构包括多个半导体芯片。
8.如权利要求1-2、5中任一所述的半导体芯片封装结构，其特征在于，
半导体封装结构被构造为表面贴装装置。
9.一种半导体芯片封装结构，包括：
导电引线框架，所述导电引线框架包括芯片垫、与芯片垫续连的多个第一电接触元件和与芯片垫电隔离的多个第二电接触元件，所述多个第二电接触元件中的第一子组彼此续连，所述多个第二电接触元件中的第二子组彼此分离且与第一子组的电接触元件分离；
半导体芯片，所述半导体芯片设置在芯片垫上，且包括设置在半导体芯片的远离芯片垫的主面上的源极接触垫；
多个连接线，所述多个连接线将所述多个第二电接触元件中的第一子组连接到源极接触垫，其中，所述连接线连接到源极接触垫的至少两个不同的接触区域；以及
包封半导体芯片的包封体；
其中，包封体具有矩形形状，且所述多个第一电接触元件和所述多个第二电接触元件与半导体芯片连接且向外仅延伸穿过矩形的两个相反的短边；
其中，芯片垫的远离半导体芯片的主面在矩形的横向于矩形的所述两个相反的短边的第一长边处至少部分暴露于外；以及
其中，所述多个第一电接触元件和所述多个第二电接触元件向所述矩形的与第一长边相反的第二长边延伸，使得半导体芯片封装结构具有安装结构，在所述安装结构中，芯片垫的至少部分外露的主面背向所述多个第一电接触元件和所述多个第二电接触元件所要附连到的接触表面。
10.如权利要求9所述的半导体芯片封装结构，其特征在于，
矩形的第一和第二长边的长度与矩形的两个相反的短边的长度之间的比值在2-3之间或大于3。
11.如权利要求9或10所述的半导体芯片封装结构，其特征在于，
矩形的第一和第二长边的长度在10mm-25mm的范围内，且矩形的两个相反的短边的长度在4mm-10mm的范围内。
12.如权利要求9或10所述的半导体芯片封装结构，其特征在于，
所述多个第一电接触元件和所述多个第二电接触元件然后以使它们的下表面共面的方式弯曲。
13.一种半导体芯片封装结构，包括：
引线框架，所述引线框架包括芯片垫、与芯片垫续连的多个第一电接触元件和与芯片垫电隔离的多个第二电接触元件，所述多个第二电接触元件中的第一子组彼此续连，所述多个第二电接触元件中的第二子组彼此分离且与第一子组的电接触元件分离；
设置在芯片垫上的半导体芯片，所述半导体芯片包括设置在半导体芯片的远离芯片垫的主面上的源极接触垫；
多个连接线，所述多个连接线将所述多个第二电接触元件中的第一子组连接到源极接触垫，其中，所述连接线连接到源极接触垫的至少两个不同的接触区域；以及
包封半导体芯片和引线框架的一部分的包封体，使得芯片垫的远离半导体芯片的主面在包封体的第一长边处至少部分暴露于外；
其中，电接触元件与半导体芯片连接且向外延伸穿过包封体的横向于第一长边的两个相反的短边；以及
其中，所述多个第一电接触元件和所述多个第二电接触元件向所述包封体的与第一长边相反的第二长边延伸，使得半导体芯片封装结构具有安装结构，在所述安装结构中，芯片垫的至少部分外露的主面背向所述多个第一电接触元件和所述多个第二电接触元件所要附连到的接触表面。
14.如权利要求13所述的半导体芯片封装结构，其特征在于，
半导体芯片包括晶体管、金属氧化物半导体晶体管、竖直晶体管、绝缘栅双极型晶体管和功率晶体管中的一个或多个。
15.如权利要求13或14所述的半导体芯片封装结构，其特征在于，
半导体芯片封装结构的主面包括由芯片垫的至少部分外露的主面形成的中心部分和在包封体的第一长边处由包封体的一部分形成的边缘部分。
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