CN105846801B - Switching circuit, analog-digital converter and integrated circuit - Google Patents
Switching circuit, analog-digital converter and integrated circuit Download PDFInfo
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- CN105846801B CN105846801B CN201511020634.4A CN201511020634A CN105846801B CN 105846801 B CN105846801 B CN 105846801B CN 201511020634 A CN201511020634 A CN 201511020634A CN 105846801 B CN105846801 B CN 105846801B
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- 238000005070 sampling Methods 0.000 claims abstract description 65
- 239000003990 capacitor Substances 0.000 claims description 64
- 238000012545 processing Methods 0.000 claims description 14
- 230000005611 electricity Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
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- 238000004146 energy storage Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0054—Gating switches, e.g. pass gates
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
This application involves a kind of switching circuit, analog-digital converter and integrated circuits.A kind of switching circuit includes: sampling transistor, which includes the source electrode for being connected to input node and the drain electrode for being connected to output node；Control circuit, the control circuit are connected to the grid of sampling transistor, and are configured to control the on or off of sampling transistor；Voltage hold circuit, the voltage hold circuit are arranged between the grid of sampling transistor and source electrode, and are configured to keep the voltage between the grid and source electrode of sampling transistor constant when sampling transistor is connected；And protection circuit, the protection circuit are configured in parallel with control circuit, and are configured to reduce the voltage for being applied to the grid of sampling transistor when sampling transistor is converted to shutdown from conducting.
Description
Technical field
Technology disclosed herein is related to a kind of switching circuit, analog-digital converter and integrated circuit.
Background technique
For the characteristic for the switch for being used to use by analog signal, it is important that will not be due to the electric conduction of switch
It hinders and is distorted the analog signal.Analog-digital converter (ADC) has switching circuit and sampling capacitor.In the adc, due to quilt
In the case where being configured to the switching circuit sampled to analog signal and distorted signals occurring, the transfer characteristic of ADC is corresponding
Ground deteriorates.Sampling transistor is known as by the transistor that the switching circuit of ADC is used to sample analog signal.Hereinafter,
It is not limited to ADC, the transistor for forming the analog switch for turning on and off analog signal is known as sampling transistor herein.Change speech
It, referred to as sample collective's pipe is not limited to ADC, anyway, as long as being used as the crystal of the main switch of analog switching circuit
Pipe can be known as sampling transistor.
Use with the cmos switch of NMOS and PMOS being connected in parallel as being configured to sample analog signal
Switching circuit, but the grid-source voltage Vgs of NMOS and PMOS changes according to input voltage.Just because of this, exist
In cmos switch, conducting resistance depends on input voltage and changes, therefore the distortion of analog signal occurs.
As for by reducing distorted signals --- it is the electric conduction due to depending on input voltage that distorted signals, which occurs,
The variation of resistance --- the technology of the accuracy of Lai Gaijin analog signal processing, it is known that a kind of bootstrapping (bootstrap) switch is (under
Referred to herein as BSW).It is nearly constant that BSW can be such that the grid-source voltage of sampling transistor remains.By in analog signal
Switching circuit in use BSW, can by reduce the distorted signals due to caused by the variation of conducting resistance come improve simulation
The accuracy of signal processing.
In recent years, a significant decrease operating voltage is being carried out to reduce power consumption and further keep circuit element small
The work of type, therefore, the withstanding voltage of circuit element reduce.The withstanding voltage for forming the transistor of BSW also reduces, and
The withstanding voltage of the transistor of BSW has dropped below twice of value of supply voltage.In above-mentioned BSW, if input signal exists
It is swung completely between 0V and supply voltage VDD, then when sampling transistor is when being converted to shutdown from conducting, it may occur however that about electricity
The case where twice of voltage of source voltage is applied to the transistor as a part of circuit.
In order to avoid this problem of withstanding voltage, control circuit is configured to sample when sampling transistor turns off
The grid voltage of transistor is reduced to low potential, which is formed by the two-staged transistor being connected in series, therefore is applied
Voltage to each transistor is lowered.
Pertinent literature
[patent document 1] Japanese Laid-Open Patent Publication the 2005-333465th
[non-patent literature 1] A.M.Abo " Design for reliability of low-voltage,
Switched-capacitor circuits ", California Institute of Technology, California, USA Pasadena city in 1999
The Ph.D. Dissertation of (California Institute of Technology, Pasadena, CA, USA).
" A1.5-V, 10-bit, the 14.3-MS/s CMOS of [non-patent literature 2] A.M.Abo and P.R.Gray
Pipeline analog-to-digital converter ", IEEE J.Solid-State Circuits, May in 1999
The phase page 599 to 606 of volume 34 the 5th.
Summary of the invention
However, still may occur to become in the state of sampling transistor from conducting although applying above-mentioned counter-measure
When changing to the instantaneous state of shutdown, the voltage more than withstanding voltage is applied to the polarized lense pipe being connected in series in control circuit
In a transistor the case where.
According to embodiment, following switching circuit is realized: in the switching circuit, forming any transistor of BSW
Dram-source voltage is no more than withstanding voltage.
According to the one aspect of embodiment, a kind of switching circuit includes: sampling transistor, which, which has, connects
It is connected to the source electrode of input node and is connected to the drain electrode of output node；Control circuit, the control circuit are connected to sampling transistor
Grid, and be configured to control the on or off of sampling transistor；Voltage hold circuit, the voltage hold circuit are set
It sets between the grid and source electrode of sampling transistor, and is configured to keep sampling transistor when sampling transistor is connected
Voltage between grid and source electrode is constant；And protection circuit, the protection circuit are configured in parallel with control circuit, and by
It is configured to reduce the voltage for being applied to the grid of sampling transistor when sampling transistor is converted to shutdown from conducting.
Detailed description of the invention
Figure 1A shows the circuit configuration of cmos switch；
Figure 1B is the figure for the operation of the circuit in explanatory diagram 1A；
Fig. 1 C shows the variation of the grid-source voltage Vgs of transistor；
Fig. 2A shows the circuit configuration of bootstrapped switch (BSW)；
Fig. 2 B is the figure for the operation of the circuit in explanatory diagram 2A；
Fig. 2 C shows the variation of the grid-source voltage Vgs of sampling transistor；
Fig. 3 A and Fig. 3 B are the transistors that can wherein can exceed that in BSW that the switch of its withstanding voltage is replaced by Fig. 2A
Circuit diagram, and Fig. 3 A be shown in which sampling transistor shutdown state, Fig. 3 B be shown in which sampling transistor be connected
State；
Fig. 4 A and Fig. 4 B are the figures for being modified to the BSW for the problem of avoiding withstanding voltage, and Fig. 4 A shows it
The state of middle sampling transistor shutdown, Fig. 4 B are shown in which the state of sampling transistor conducting；
Fig. 5 shows the figure of the operation order of the BSW in Fig. 4 A and Fig. 4 B；
Fig. 6 is the circuit diagram of the bootstrapped switch (BSW) of present embodiment, and it illustrates the shapes of wherein sampling transistor shutdown
State；
Fig. 7 is the circuit diagram of the bootstrapped switch (BSW) of present embodiment, and it illustrates the shapes of wherein sampling transistor conducting
State；
Fig. 8 is to show the figure of the operation order of BSW of present embodiment；
Fig. 9 A is to show the figure of the configuration example of circuit of the switching circuit using present embodiment；
Fig. 9 B is to show the figure of the configuration example of the reception system using the switching circuit of present embodiment；And
Fig. 9 C, which is shown, receives system using the ultrasonic wave of the switching circuit of present embodiment.
Specific embodiment
Before illustrating the switching circuit of embodiment, first common switching circuit is illustrated.
Figure 1A shows the circuit configuration of cmos switch.Figure 1B is the figure for the operation of the circuit in explanatory diagram 1A.Figure
1C shows the variation of the grid-source voltage Vgs of transistor.
Cmos switch is widely used as the switch sampled to analog signal.Cmos switch, which has, is connected in input in parallel
NMOS and PMOS between node and output node, the switch SWX for switching the grid of NOMS between 0V and VDD and will
The switch SWY that the grid of PMOS switches between VDD and 0V.
As shown in Figure 1A, when switch SWX is connected to 0V and switch SWY is connected to VDD, NMOS and PMOS shutdown and
Cmos switch enters off state.As shown in Figure 1B, when switch SWX is connected to VDD and switch SWY is connected to 0V, NMOS
It is connected with PMOS, and cmos switch enters pass-through state (pass-through state) and by the simulation at input node
Input signal Vi is exported at output node as analog output signal Vo.In this case, as shown in Figure 1 C, NMOS and
The voltage Vgs of PMOS changes according to the voltage of input signal Vi, and therefore, in cmos switch, conducting resistance depends on input
Voltage and change, therefore occur analog signal distortion.
As for by reducing distorted signals --- the distorted signals is along with the input electricity depended in cmos switch
The variation of the conducting resistance of pressure and occur --- a kind of technology of the accuracy of Lai Gaijin analog signal processing, it is known that bootstrapped switch
(hereinafter referred to as BSW).
Fig. 2A shows the circuit configuration of bootstrapped switch (BSW).Fig. 2 B is the operation for the circuit in explanatory diagram 2A
Figure.Fig. 2 C shows the variation of the grid-source voltage Vgs of sampling transistor.
BSW has NMOS transistor M0 corresponding with sampling transistor, energy-storage capacitor element C0 and three switch SW1
To SW3.M0 is connected between input node and output node, and is used as using analog input signal Vi as analog output signal
The main transistor that Vo is transmitted.SW1, C0 and SW2 are connected in series in 0V power supply (the second potential power source) and VDD power supply (first
Potential power source) between.The voltage of VDD power supply (the first potential power source) is such as 1.0V to 1.2V, and is higher than 0V power supply (second
Potential power source) voltage (0V).A terminal of C0 is switched to the grid for being connected to VDD power supply or being connected to M0 by SW2.
SW1, which switches to another terminal of C0, to be connected to 0V power supply or is connected to input node (source electrode of M0).SW3 is by M0's
Grid is connected to 0V power supply and is not attached between 0V power supply and switches over.
As shown in Figure 2 A, when SW1 is connected to 0V power supply, SW2 is connected to VDD power supply and SW3 is connected to 0V power supply, then
M0 is turned off and BSW enters off state.At this point, C0 is charged to VDD.As shown in Figure 2 B, when SW1 be connected to input node,
When SW2 is connected to the grid of M0 and SW3 and disconnects, then voltage Vi+VDD --- the i.e. voltage Vi of input signal with charge after C0
The sum of voltage VDD --- be applied to the grid of M0, therefore M0 is connected.For this reason, the simulation at input node is defeated
Enter signal and is output to output node as analog output signal Vo.As described above, the grid voltage of M0 is Vi+VDD, and such as
Shown in Fig. 2 C, the grid-source voltage Vgs of M0 keeps nearly constant.
Sampling switch by using BSW as analog signal, it is possible to reduce the signal occurred when conducting resistance variation
Distortion, to improve the accuracy of analog signal processing.
However, the withstanding voltage for forming the transistor of BSW is less than twice of value of supply voltage, and in BSW reality
On realized by transistor in the case where, when BSW makes transistor be converted to shutdown from conducting, be more than in portion of transistor
The case where withstanding voltage.If it exceeds withstanding voltage, then the transistor will be destroyed.
Fig. 3 A and Fig. 3 B are the transistors in the BSW that can be wherein replaced by Fig. 2A more than the switch of its withstanding voltage
Circuit diagram, and Fig. 3 A be shown in which sampling transistor shutdown state, Fig. 3 B be shown in which sampling transistor be connected
State.
As shown in Figure 3A and Figure 3B, SW3 is realized by the NMOS transistor M5 being connected between the grid of M0 and 0V power supply.
Control signal Phi is applied to the grid of M5.
As shown in Figure 3A, when Φ=VDD (high level), SW1 is connected to 0V power supply, and SW2 is connected to VDD power supply, and SW3 connects
It is connected to 0V power supply, M5 conducting, and the grid (node G) of M0 becomes 0V, therefore, M0 is turned off and BSW enters off state.This
When, C0 is charged to VDD.Terminal at the high-pressure side of C0 is indicated that the terminal at the low-pressure side of C0 is indicated by L by H.
As shown in Figure 3B, when Φ=0V (low level), SW1 is connected to input node, and SW2 is connected to the grid of M0, M5
Grid become 0V and M5 and turn off, and input signal Vi+VDD is applied to the grid (node G) of M0, therefore, M0 conducting
And BSW enters on state.
For example, it is contemplated that the case where wherein Vi is swung completely between 0V and VDD.As Vi=VDD, node G becomes 2 ×
The dram-source voltage of VDD and M5 become 2 × VDD, therefore have been more than withstanding voltage.
Fig. 4 A and Fig. 4 B are the figures for being modified to the BSW for the problem of avoiding withstanding voltage.Fig. 4 A is shown in which to adopt
The state of sample transistor shutdown, Fig. 4 B are shown in which the state of sampling transistor conducting.
Circuit in Fig. 4 A and Fig. 4 B is to be inserted into NMOS transistor M4 between the drain electrode of M5 and node G in figure 3 a
Circuit.VDD is applied to the grid of M4.As shown in Figure 4 A, as Φ=VDD, M5 conducting, and the connecting node D2 of M4 and M5
Become 0V, therefore, M4 is switched on, and node G becomes 0V, and M0 is turned off.
As shown in Figure 4 B, as Φ=0V, node G becomes Vi+VDD, M5 shutdown, and M0 is connected.At this point, due to node
D2 becomes VDD, therefore M4 is turned off, and the dram-source voltage of M5 becomes VDD, and the dram-source voltage of M4 becomes Vi (most
Greatly VDD), therefore, the dram-source voltage of M5 is no more than withstanding voltage.
As it was earlier mentioned, energy-storage capacitor C0 is charged to supply voltage VDD in the state of M0 shutdown (Fig. 4 A), and
And the grid voltage of M0 is controlled as 0V.On the other hand, in the state that M0 is connected (Fig. 4 B), the grid-source voltage of M0 is
VDD and almost constant.As described above, the Vgs of the transistor of M4 and M5 is less likely more than Fig. 4 A under steady state
With the withstanding voltage of the BSW in Fig. 4 B.However, it is also possible to which instantaneously occurring is more than that the voltage of withstanding voltage is applied to the feelings of M4
Condition.Conducting is become from shutdown to M0 below and is illustrated from the instantaneous state that conducting becomes shutdown.
Fig. 5 is to show the figure of the operation order of the BSW in Fig. 4 A and Fig. 4 B.
When M0 is converted to conducting from shutdown, controlling signal Phi from VDD becomes 0V.At this point, by the shutdown of M5, node D2
Become VDD from 0V.Then, node G (SW2) is connected to by the shutdown of M4, node H and node L is connected to input node
(Vi), the voltage of node L, node H and node G increase according to analog signal Vi.In Fig. 5, Vi=VDD, therefore, node L
Voltage increase to the voltage of VDD, node H and node G and increase to 2 × VDD.
When M0 is converted to shutdown from conducting, controlling signal Phi from 0V becomes VDD.At this point, by the conducting of M5, node D2
Become 0V from VDD.Then, M4 is connected, and node G is connected to 0V (becoming 0V from VDD+Vi), and node L is connected to 0V (SW1), and
Node H is connected to VDD (SW2).
When M0 is converted to shutdown from conducting, M4 and M5 are responsible for node G being reduced to 0V.When M5 conducting and node D2 from
When VDD becomes 0V, if the threshold value of M4 is taken Vth (M4), the dram-source voltage of M4 increases, until the voltage of node D2
Until becoming less than or equal to VDD-Vth (M4).
The ideal voltage of node G is VDD+Vi, and therefore, drain electrode-source voltage VDS of M4 increases to Vi+Vth (M4).As above
It is described, when M0 is converted to shutdown from conducting, occur in which that the dram-source voltage of M4 is more than the feelings of the withstanding voltage of transistor
Condition.
When M0 is converted to shutdown from conducting, in the circuit configuration for the BSW being shown in FIG. 4, the dram-source voltage of M4
Inevitably increase to Vi+Vth (M4).Just because of this, in the BSW of the embodiment illustrated below, drain electrode-is avoided
The increase of source voltage VDS, so that transistor (M4) is no more than withstanding voltage when M0 is converted to shutdown from conducting.
Fig. 6 is the circuit diagram of the bootstrapped switch (BSW) of present embodiment, and it illustrates the shapes of wherein sampling transistor shutdown
State.
Fig. 7 is the circuit diagram of the bootstrapped switch (BSW) of present embodiment, and it illustrates the shapes of wherein sampling transistor conducting
State.
In Fig. 6, appended drawing reference 10 indicates control signal generating circuit, is configured to according to control 1 next life of signal Phi
At control signal Phi 2 and Φ 3.Control signal Phi 2 is the signal obtained by delayed control signal Φ 1, and control signal Phi 3 is
The signal obtained by further delayed control signal Φ 1.
The BSW of present embodiment has the input node and simulate from its output for being connected to that analog input signal Vi is entered
Sampling transistor M0 between the output node of output signal Vo.M0 is using analog input signal Vi as analog output signal Vo
The main transistor being transmitted.
The BSW of present embodiment also has the PMOS transistor M3 being connected in series between VDD power supply and 0V power supply, energy storage
Capacitor C0 and NMOS transistor M6.The high pressure side terminal of energy-storage capacitor C0 is indicated that energy-storage capacitor C0's is low by node H
Pressure side terminal is indicated by node L.The grid of M3 is connected to the grid (node G) of M0, and controls signal Phi 3 and be applied to M6's
Grid.The BSW of present embodiment also has the NMOS transistor being connected between input node and the node L of energy-storage capacitor C0
M1, and the PMOS transistor M2 being connected between the grid (node G) of M0 and the node H of energy-storage capacitor C0.The grid of M1
It is connected to the grid (node G) of M0, and controls the grid that signal Phi 3 is applied to M2.M1 and M6 is formed in Fig. 4 A and Fig. 4 B
SW1.M2 and M3 forms the SW2 in Fig. 4 A and Fig. 4 B.
The BSW of present embodiment also has the NMOS crystal being connected in series between the grid (node G) of M0 and 0V power supply
Pipe M4 and M5.VDD is applied to the grid of M4, and controls the grid that signal Phi 2 is applied to M5.M4 in present embodiment
With M5 in Fig. 4 A and Fig. 4 B M4 and M5 it is corresponding.
Above-mentioned configuration is identical as the configuration of BSW in Fig. 4 A and Fig. 4 B.
The BSW of present embodiment also has the decaying capacitor being connected in series between the grid (node G) of M0 and 0V power supply
Device CVD1 and attenuation capacitor CVD2, and the NMOS crystal being connected between connecting node D1 and the 0V power supply of CVD1 and CVD2
Pipe M11.Control signal Phi 1 is applied to the grid of M11.Herein, it is known as protecting by the circuit that CVD1, CVD2 and M11 are formed
Circuit.In other words, the circuit in BSW and Fig. 4 A and Fig. 4 B of present embodiment is the difference is that be added to protection electricity
Road.
The withstanding voltage that attenuation capacitor CVD1 is set to protect M11 to realize M11, and when M0 is converted to from conducting
When shutdown, the voltage of node G is reduced.Apply to the control signal Phi 1 of M11 in the dram-source voltage of M5 conducting and M4
The dram-source voltage of M4 is reduced before increasing in advance.Attenuation capacitor CVD2 is set to prevent the steady state be connected in M0
Under due to reduce attenuation capacitor CVD1 and attenuation capacitor CVD2 series capacitance and be attenuated the voltage of node G.It is former
Because being, if the voltage of node G is attenuated when M0 conducting, the grid-source voltage of M0 is reduced and conducting resistance increases.
Other basic operations are identical as the basic operation of circuit in Fig. 4 A and Fig. 4 B, and to the circuit for including additional protection circuit
Operation is illustrated.
As shown in fig. 6, as Φ 1=VDD and M0 in an off state, as in the circuit in Fig. 4 A and Fig. 4 B,
Energy-storage capacitor C0 is charged to supply voltage VDD, M5 and M4 conducting, and the grid voltage of M0 is controlled as 0V.At this point,
The grid of M11 is VDD, and therefore, M11 is connected and node D1 is also controlled by as 0V.
On the other hand, as shown in fig. 7, as Φ 1=0V and M0 in the conductive state, such as the circuit in Fig. 4 A and Fig. 4 B
In like that, M5 and M4 shutdown, the grid voltage of M0 become Vi+VDD, and the grid-source voltage Vgs of M0 become VDD and
It is almost constant.
At this point, the grid of M11 is 0V, and therefore, M11 shutdown, and the voltage of node D1 becomes by by the voltage of node G
The voltage obtained with the ratio of the capacitor of attenuation capacitor CVD1 and the capacitor of attenuation capacitor CVD2 partial pressure.
Then, conducting will be converted to from shutdown to wherein M0 and be illustrated from the state that conducting is converted to shutdown.
Fig. 8 is to show the figure of the operation order of BSW of present embodiment.Fig. 8 shows the case where Vi=VDD.
Firstly, the case where being converted to conducting from shutdown to M0 is illustrated.
Control signal Phi 1 becomes 0V from VDD.It is added to the M11 shutdown of the BSW of present embodiment, therefore, for node G,
The attenuation capacitor CVD1 and attenuation capacitor CVD2 of series connection are connected between node G and 0V power supply.D1 becomes passing through
The electricity that the voltage of node G is obtained with the ratio of the capacitor of attenuation capacitor CVD1 and the capacitor of attenuation capacitor CVD2 partial pressure
Pressure.
Then, when controlling signal Phi 2 becomes 0V from VDD, M5 shutdown.In response to this, node D2 from 0V become VDD and
M4 shutdown.
Finally, the node H of energy-storage capacitor C0 is connected to node G by control signal Phi 3, node L is connected to input section
Point, and Vi is applied.Due to this point, node L, node H and node G enter the state fluctuated according to analog signal Vi.
In fig. 8, VI=VDD, therefore, the node L of energy-storage capacitor C0 become VDD, and the section of energy-storage capacitor C0
The voltage of point H and node G increase to 2 × VDD.
Following formula (1) shows the voltage of the node G when M0 conducting.
G=(VDD+Vi) × C0/ (C0+C) (1)
Here, C=CVD1 × CVD2/ (CVD1+CVD2).
Then, the case where being converted to shutdown from conducting to M0 is illustrated.
Control signal Phi 1 becomes VDD from 0V.It is added to the M11 conducting of the BSW of present embodiment, therefore, results in and is saving
The state for only having attenuation capacitor CVD1 to be connected to node G between point G and 0V power supply.
Then, when controlling signal Phi 2 becomes VDD from 0V, M5 conducting, and node D2 becomes 0V from VDD.In response to
This, M4 conducting, and node G is connected to 0V (becoming 0V from VDD+Vi).
Finally, by control signal Phi 3, the node L of energy-storage capacitor C0 is connected to 0V, and the section of energy-storage capacitor C0
Point H is connected to VDD.
When M0 is converted to shutdown from conducting, M4 and M5 are responsible for node G being down to 0V.However, with Fig. 4 A and Fig. 4 B
Circuit is different, in the BSW of present embodiment, before node G is down to 0V by M4 and M5, by connecting attenuation capacitor CVD1
It is connected to node G, the voltage of node G is divided with the ratio of the capacitor of energy-storage capacitor C0 and the capacitor of attenuation capacitor CVD1
Pressure.
By the way that the voltage of node G is divided with the ratio of the capacitor of energy-storage capacitor C0 and the capacitor of attenuation capacitor CVD1
To reduce the voltage of node G, it is possible to reduce the dram-source voltage of M4.
Following formula (2) shows the voltage of node G at this time (referring to " being decayed by CVD1 " in Fig. 8).
G=(VDD+Vi) × C0/ (C0+CVD1) (2)
Hereafter, when M5 is connected and node D2 becomes 0V from VDD, the dram-source voltage VDS of M4 increases, until VDS
Until the voltage for reaching more than the threshold value of M4.
However, it is possible to create following design: drain electrode-source since M4 can be reduced in advance by attenuation capacitor CVD1
Pole tension, so that being no more than withstanding voltage.
As discussed above, in the circuit shown in Fig. 4 A and Fig. 4 B, when M0 is converted to shutdown from conducting,
The dram-source voltage of M4 inevitably increases to Vi+Vth.The reason is that having to make M0 be converted to shutdown from conducting
Necessity reduces the voltage of node D2, until reaching more than the voltage of threshold value.
In contrast, in the circuit of the BSW of present embodiment, node G is being become 0V's from VDD+Vi from M4 and M5
Before timing, the voltage decline of M11 conducting and node G.By determining energy-storage capacitor C0 and decaying according to expression formula (2)
Capacitor CVD1, can the arbitrarily devised node G when M11 is connected voltage.Due to this point, drain electrode-source of M4 can solve
The problem of pole tension VDS is more than withstanding voltage.Therefore, the capacitance of attenuation capacitor CVD1 becomes the electricity with energy-storage capacitor C0
The value that capacitance is closer to.
In addition, using attenuation capacitor CVD2 to reduce attenuation capacitor CVD1 and decaying under the steady state of M0 conducting
The series capacitance of capacitor CVD2.By determining energy-storage capacitor C0, attenuation capacitor CVD1 and decaying according to expression formula (1)
Capacitor CVD2, can arbitrarily devised node G at this time voltage.
The conducting resistance of switch will not worsen, because by reducing attenuation capacitor CVD1 and attenuation capacitor CVD2
Series capacitance, the decaying of the node G when M0 is connected can be inhibited.Therefore, the capacitance of attenuation capacitor CVD2 becomes and declines
The capacitance of powered down container CVD1 compares sufficiently small value.
Then, the circuit of switching circuit and the example of system of application present embodiment are illustrated.
Fig. 9 A is to show the figure of the configuration example of circuit of the switching circuit using present embodiment.Fig. 9 B is to show
Using the figure of the configuration example of the reception system of the switching circuit of present embodiment.Fig. 9 C shows opening using present embodiment
The ultrasonic wave on powered-down road receives system.
As shown in Figure 9 A, adc circuit 20 has the sample circuit 21 for being configured to sample the analog signal of input,
And it is configured to for the analog signal of sampling being converted into the ADC unit 22 of digital signal.The conversion method of ADC unit 22 can be with
It is any method.Sample circuit 21 has switching circuit 23 and sampling capacitor 24.By by the switching circuit of present embodiment
Using for switching circuit 23, can be formed through low withstanding voltage circuit element and improve its analog signal processing (is herein AD
Conversion process) accuracy adc circuit.Adc circuit 20 can be formed single semiconductor device or by
Be formed as a part of semiconductor device.
As shown in Figure 9 B, the reception system of radio communication equipment has antenna 31, low-noise amplifier (LNA) 32, mistake
Filter 33, converter unit 34, PLL 35, adc circuit 36 and digital baseband transmission system circuit unit 37.By will be in Fig. 9 A
Adc circuit apply be adc circuit 36, can be formed through low withstanding voltage circuit element and improve its analog signal processing
The reception system of the accuracy of (reception processing).For example, each of adc circuit 36 and digital baseband signal processing unit 37
It can be formed single semiconductor device.
As shown in Figure 9 C, ultrasonic wave receives system, and there is ultrasonic transducer 41, low-noise amplifier (LNA) 43, time to increase
Beneficial correcting circuit 43, filter 44, adc circuit 45 and digital operation processing circuit unit 46.By the way that the ADC of 9A in figure is electric
It is adc circuit 45 that road, which is applied, and can be formed through low withstanding voltage circuit element and improve its analog signal processing (is super herein
Acoustic receiver processing) accuracy ultrasonic wave receive system.For example, adc circuit 45 and digital operation processing circuit unit 46
Each of can be formed single semiconductor device.
Claims (6)
1. a kind of switching circuit, comprising:
Sampling transistor, the sampling transistor include the source electrode for being connected to input node and the drain electrode for being connected to output node；
Control circuit, the control circuit are connected to the grid of the sampling transistor, and are configured to control the sampling
The on or off of transistor；
Voltage hold circuit, the voltage hold circuit are arranged between the grid and source electrode of the sampling transistor, and
The voltage between grid and source electrode for being configured to keep the sampling transistor when the sampling transistor is connected is constant；With
And
Circuit is protected, the protection circuit includes the first decaying capacity cell, the second decaying capacity cell and attenuator switch,
In, the first decaying capacity cell and the second decaying capacity cell be connected in series in the grid of the sampling transistor with
Between first potential power source, the attenuator switch is connected to the first decaying capacity cell and the second decaying capacity cell
Connecting node and first potential power source between, the protection circuit is configured in parallel with the control circuit, and
It is configured to reduce the electricity for being applied to the grid of the sampling transistor when the sampling transistor is converted to shutdown from conducting
Pressure, and do not reduce the voltage for being applied to the grid of the sampling transistor when sampling transistor conducting.
2. switching circuit according to claim 1, wherein
The voltage hold circuit includes:
Storage capacitor element；
First charge switch, first charge switch are configured to for a terminal of the storage capacitor element being connected to
Two potential power sources；
Second charge switch, second charge switch are configured to the another terminal of the storage capacitor element being connected to institute
The first potential power source is stated, the voltage of first potential power source is lower than the voltage of second potential power source；
Connection switch is inputted, the input connection switch is connected to the described another of the input node and the storage capacitor element
Between one terminal；And
Grid connection switch, the grid connection switch are connected to the grid and the storage capacitor element of the sampling transistor
One terminal between,
When sampling transistor conducting, the input connection switch and grid connection switch conducting, described first fills
Electric switch and second charge switch shutdown, and the storage capacitor element provides the to the grid of the sampling transistor
One voltage, the first voltage are obtained and being added the voltage of the storage capacitor element with the voltage of the input node
, and
When sampling transistor shutdown, the input connection switch and grid connection switch shutdown, described first fills
Electric switch and second charge switch conducting, and the storage capacitor element is electrically charged.
3. switching circuit according to claim 2, wherein
The control circuit includes be connected in series between the grid of the sampling transistor and first potential power source
One transistor and second transistor,
When sampling transistor shutdown, the first transistor and second transistor conducting, and
When sampling transistor conducting, at least one transistor in the first transistor and the second transistor is closed
It is disconnected.
4. switching circuit according to claim 3, wherein
When sampling transistor shutdown, the attenuator switch enters on state, and when sampling transistor conducting
The attenuator switch enters off state, and
When the sampling transistor is converted to shutdown from conducting, in grid connection switch shutdown and the first crystal
Before pipe and the second transistor are switched on, the attenuator switch enters on state.
5. a kind of analog-digital converter, comprising:
Sample circuit, the sample circuit are configured to sample analog signal；And
AD conversion unit, the AD conversion unit are configured to the analog signal being converted into digital signal, wherein
The sample circuit includes:
Sampling capacitance element；And
Switching circuit according to any one of claim 1 to 4.
6. a kind of integrated circuit, comprising:
Analog-digital converter according to claim 5；And
Processing circuit, the processing circuit are configured to handle the digital signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015016032A JP6497089B2 (en) | 2015-01-29 | 2015-01-29 | Switch circuit, AD conversion circuit, and integrated circuit |
| JP2015-016032 | 2015-01-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105846801A CN105846801A (en) | 2016-08-10 |
| CN105846801B true CN105846801B (en) | 2019-07-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511020634.4A Active CN105846801B (en) | 2015-01-29 | 2015-12-30 | Switching circuit, analog-digital converter and integrated circuit |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9444483B2 (en) |
| JP (1) | JP6497089B2 (en) |
| CN (1) | CN105846801B (en) |
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| CN106531222B (en) * | 2016-11-10 | 2020-01-24 | 中国电子科技集团公司第四十七研究所 | FPGA driving voltage generating circuit based on FLASH and driving method |
| US10084466B1 (en) * | 2017-12-28 | 2018-09-25 | Texas Instruments Incorporated | Top plate sampling circuit including input-dependent dual clock boost circuits |
| CN108806757A (en) * | 2018-06-19 | 2018-11-13 | 广州领知信息技术有限公司 | High-speed boosting type signal sampling transmitting switch |
| CN112394765A (en) * | 2019-08-19 | 2021-02-23 | 珠海格力电器股份有限公司 | Current source circuit and control device |
| CN110635791B (en) * | 2019-09-06 | 2023-03-31 | 重庆邮电大学 | Grid voltage bootstrap sampling switch circuit adopting mirror image structure |
| CN112929015B (en) * | 2021-01-22 | 2023-10-31 | 东芯半导体股份有限公司 | switching circuit |
| US11804836B1 (en) | 2022-05-20 | 2023-10-31 | Analog Devices, Inc. | Bootstrapped switch with fast turn off |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN105846801A (en) | 2016-08-10 |
| US9444483B2 (en) | 2016-09-13 |
| US20160226506A1 (en) | 2016-08-04 |
| JP6497089B2 (en) | 2019-04-10 |
| JP2016143918A (en) | 2016-08-08 |
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