CN105742173A - Processing method for ultra-thin wafer - Google Patents
Processing method for ultra-thin wafer Download PDFInfo
- Publication number
- CN105742173A CN105742173A CN201610119055.3A CN201610119055A CN105742173A CN 105742173 A CN105742173 A CN 105742173A CN 201610119055 A CN201610119055 A CN 201610119055A CN 105742173 A CN105742173 A CN 105742173A
- Authority
- CN
- China
- Prior art keywords
- wafer
- ultra
- processing method
- circular arc
- arc portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 12
- 235000012431 wafers Nutrition 0.000 claims description 48
- 230000009467 reduction Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 11
- 230000001681 protective effect Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000008569 process Effects 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a processing method for an ultra-thin wafer. The method comprises the following steps: (1) removing the peripheral arc part of the wafer of requiring thinning treatment and making the periphery of the wafer be in a right-angle form; (2) pasting a protective film on the front surface of the wafer from which the peripheral arc part is removed; (3) grinding the back surface of the wafer for thinning treatment on the wafer and thinning the wafer to a specified thickness; and (4) stripping off the protective film pasted on the front surface of the wafer to obtain the thinned wafer which conforms to the requirements. The processing method has the beneficial effects that (1) the method is simple to process; (2) the film is easy to paste; and (3) the subsequent processing technology of a silicon wafer is compatible with a traditional method.
Description
Technical field
The present invention relates to the processing technique field of wafer, the processing method particularly relating to a kind of ultra-thin wafers.
Background technology
In wafer reduction process, being characterized as being in the ultra-thin wafers course of processing, crystal round fringes is very easy to break, its reason be thinning after, crystal round fringes is very sharp, so especially easy breakage.
In order to prevent the edge break of wafer in the ultra-thin wafers course of processing, referring to Fig. 1 to Fig. 4, current method is the edge 13 (referring to Fig. 1 and Fig. 2) on the surface 3 of first grinding crystal wafer 2, then, on the surface 26 adopting adhesive 24 to paste another block wafer 4 on the surface 3 of wafer 2 ground for marginal surface, the back side 5 finally grinding away wafer 3 obtains the wafer 2 of neat in edge.The method complex process, and be also a problem to wafer 2 film on surface after edge grinding.
For this, applicant carried out useful exploration and trial, have found result of the above problems, technical scheme described below produces under this background.
Summary of the invention
The technical problem to be solved: for above-mentioned providing to prevent problem existing for the processing method that the edge break of wafer adopts in the ultra-thin wafers course of processing that a kind of technique is simple, be prone to pad pasting, the processing method of compatible good ultra-thin wafers.
Technical problem solved by the invention can realize by the following technical solutions:
The processing method of a kind of ultra-thin wafers, comprises the following steps:
(1) the periphery circular arc portion needing the wafer of reduction processing is removed so that the rectangular shape of periphery of described wafer；
(2) protecting film is pasted in the front of the wafer removing periphery circular arc portion；
(3) described wafer is carried out reduction processing by the back side grinding described wafer, is thinned to specific thickness；
(4) tear the protecting film being pasted onto in described wafer frontside off, obtain the wafer after satisfactory reduction processing.
In a preferred embodiment of the invention, the radial width of described periphery circular arc portion is 0.5mm～1mm.
Owing to have employed technical scheme as above, the beneficial effects of the present invention is: 1, processing is simple；2, it is prone to pad pasting；3 and the follow-up processing technique of silicon chip and traditional method compatible.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 to Fig. 4 is existing wafer processing method schematic diagram.
Fig. 5 is the structural representation that the present invention removes the wafer of periphery circular arc portion.
Fig. 6 is present invention schematic diagram of pasting protective film on the front of wafer removing periphery circular arc portion.
Fig. 7 is the schematic diagram of the thinning back side of the wafer of coated with protective film of the present invention.
Fig. 8 is the structural representation of product wafer of the present invention.
Detailed description of the invention
For the technological means making the present invention realize, creation characteristic, reach purpose and effect and be easy to understand, below in conjunction with being specifically illustrating, the present invention is expanded on further.
Referring to Fig. 5 to Fig. 8, the processing method of a kind of ultra-thin wafers of the present invention, comprise the following steps:
(1) referring to Fig. 5, special equipment is adopted to be removed by the periphery circular arc portion 11 needing the wafer 10 of reduction processing so that the rectangular shape of periphery of wafer 10, in the present embodiment, the radial width of the periphery circular arc portion 11 of wafer 10 is 0.5mm～1mm.
(2) referring to Fig. 6, a protecting film 20 is pasted in the front 12 of the wafer 10 removing periphery circular arc portion 11, for protecting the front of wafer 10；
(3) referring to Fig. 7, the back side 13 of grinding crystal wafer 10, wafer 10 is carried out reduction processing, is thinned to specific thickness；
(4) tear the protecting film 20 being pasted onto on wafer 10 front 12 off, obtain the wafer 10 after satisfactory reduction processing, referring to Fig. 8.
The ultimate principle of the present invention and principal character and advantages of the present invention have more than been shown and described.Skilled person will appreciate that of the industry; the present invention is not restricted to the described embodiments; described in above-described embodiment and description is that principles of the invention is described; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements both fall within the claimed scope of the invention.Claimed scope is defined by appending claims and equivalent thereof.
Claims (2)
1. the processing method of a ultra-thin wafers, it is characterised in that comprise the following steps:
(1) the periphery circular arc portion needing the wafer of reduction processing is removed so that the rectangular shape of periphery of described wafer；
(2) protecting film is pasted in the front of the wafer removing periphery circular arc portion；
(3) described wafer is carried out reduction processing by the back side grinding described wafer, is thinned to specific thickness；
(4) tear the protecting film being pasted onto in described wafer frontside off, obtain the wafer after satisfactory reduction processing.
2. the processing method of ultra-thin wafers as claimed in claim 1, it is characterised in that the radial width of described periphery circular arc portion is 0.5mm～1mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610119055.3A CN105742173A (en) | 2016-03-02 | 2016-03-02 | Processing method for ultra-thin wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610119055.3A CN105742173A (en) | 2016-03-02 | 2016-03-02 | Processing method for ultra-thin wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105742173A true CN105742173A (en) | 2016-07-06 |
Family
ID=56249798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610119055.3A Pending CN105742173A (en) | 2016-03-02 | 2016-03-02 | Processing method for ultra-thin wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105742173A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211913A (en) * | 2019-05-29 | 2019-09-06 | 浙江荷清柔性电子技术有限公司 | A kind of manufacturing method of flexible chip |
| CN111785611A (en) * | 2020-08-07 | 2020-10-16 | 厦门陆远科技有限公司 | Method for manufacturing thin silicon wafer |
| CN111900083A (en) * | 2020-07-01 | 2020-11-06 | 上海华虹宏力半导体制造有限公司 | IGBT wafer thinning method |
| CN112846948A (en) * | 2019-11-28 | 2021-05-28 | 东莞新科技术研究开发有限公司 | Wafer surface processing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005093882A (en) * | 2003-09-19 | 2005-04-07 | Disco Abrasive Syst Ltd | Method for polishing wafer |
| CN103035482A (en) * | 2012-08-15 | 2013-04-10 | 上海华虹Nec电子有限公司 | Temporary bonding method of silicon wafer |
| JP2013115187A (en) * | 2011-11-28 | 2013-06-10 | Disco Abrasive Syst Ltd | Processing method of wafer |
| CN203998938U (en) * | 2014-07-29 | 2014-12-10 | 中芯国际集成电路制造(北京)有限公司 | Wafer level packaging equipment |
-
2016
- 2016-03-02 CN CN201610119055.3A patent/CN105742173A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005093882A (en) * | 2003-09-19 | 2005-04-07 | Disco Abrasive Syst Ltd | Method for polishing wafer |
| JP2013115187A (en) * | 2011-11-28 | 2013-06-10 | Disco Abrasive Syst Ltd | Processing method of wafer |
| CN103035482A (en) * | 2012-08-15 | 2013-04-10 | 上海华虹Nec电子有限公司 | Temporary bonding method of silicon wafer |
| CN203998938U (en) * | 2014-07-29 | 2014-12-10 | 中芯国际集成电路制造(北京)有限公司 | Wafer level packaging equipment |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211913A (en) * | 2019-05-29 | 2019-09-06 | 浙江荷清柔性电子技术有限公司 | A kind of manufacturing method of flexible chip |
| CN112846948A (en) * | 2019-11-28 | 2021-05-28 | 东莞新科技术研究开发有限公司 | Wafer surface processing method |
| CN112846948B (en) * | 2019-11-28 | 2024-02-23 | 东莞新科技术研究开发有限公司 | Wafer surface processing method |
| CN111900083A (en) * | 2020-07-01 | 2020-11-06 | 上海华虹宏力半导体制造有限公司 | IGBT wafer thinning method |
| CN111900083B (en) * | 2020-07-01 | 2022-08-16 | 上海华虹宏力半导体制造有限公司 | IGBT wafer thinning method |
| CN111785611A (en) * | 2020-08-07 | 2020-10-16 | 厦门陆远科技有限公司 | Method for manufacturing thin silicon wafer |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160706 |
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| RJ01 | Rejection of invention patent application after publication |